OpenWrt – Blame information for rev 4
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1 | office | 1 | From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl> |
2 | Date: Tue, 31 Jan 2017 22:54:54 +0100 |
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3 | Subject: [PATCH] net: phy: broadcom: rehook BCM54612E specific init |
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4 | MIME-Version: 1.0 |
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5 | Content-Type: text/plain; charset=UTF-8 |
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6 | Content-Transfer-Encoding: 8bit |
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7 | |||
8 | This extra BCM54612E code in PHY driver isn't really aneg specific. Even |
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9 | without it aneg works OK but the problem is no packets pass through PHY. |
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10 | |||
11 | Moreover putting this code inside config_aneg callback didn't allow |
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12 | resuming PHY correctly. When driver called phy_stop and phy_start it was |
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13 | putting PHY machine into RESUMING state. After that machine was |
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14 | switching into AN and NOLINK without ever calling phy_start_aneg. This |
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15 | prevented this extra setup from being called and PHY didn't work. |
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16 | |||
17 | This change has been verified to fix network on BCM47186B0 SoC device |
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18 | with BCM54612E. |
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19 | |||
20 | Signed-off-by: Rafał Miłecki <rafal@milecki.pl> |
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21 | Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
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22 | Signed-off-by: David S. Miller <davem@davemloft.net> |
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23 | --- |
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24 | |||
25 | --- a/drivers/net/phy/broadcom.c |
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26 | +++ b/drivers/net/phy/broadcom.c |
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27 | @@ -46,6 +46,34 @@ static int bcm54210e_config_init(struct |
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28 | return 0; |
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29 | } |
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30 | |||
31 | +static int bcm54612e_config_init(struct phy_device *phydev) |
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32 | +{ |
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33 | + /* Clear TX internal delay unless requested. */ |
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34 | + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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35 | + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) { |
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36 | + /* Disable TXD to GTXCLK clock delay (default set) */ |
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37 | + /* Bit 9 is the only field in shadow register 00011 */ |
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38 | + bcm_phy_write_shadow(phydev, 0x03, 0); |
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39 | + } |
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40 | + |
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41 | + /* Clear RX internal delay unless requested. */ |
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42 | + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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43 | + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) { |
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44 | + u16 reg; |
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45 | + |
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46 | + reg = bcm54xx_auxctl_read(phydev, |
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47 | + MII_BCM54XX_AUXCTL_SHDWSEL_MISC); |
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48 | + /* Disable RXD to RXC delay (default set) */ |
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49 | + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; |
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50 | + /* Clear shadow selector field */ |
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51 | + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; |
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52 | + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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53 | + MII_BCM54XX_AUXCTL_MISC_WREN | reg); |
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54 | + } |
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55 | + |
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56 | + return 0; |
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57 | +} |
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58 | + |
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59 | static int bcm54810_config(struct phy_device *phydev) |
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60 | { |
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61 | int rc, val; |
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62 | @@ -250,6 +278,10 @@ static int bcm54xx_config_init(struct ph |
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63 | err = bcm54210e_config_init(phydev); |
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64 | if (err) |
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65 | return err; |
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66 | + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) { |
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67 | + err = bcm54612e_config_init(phydev); |
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68 | + if (err) |
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69 | + return err; |
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70 | } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) { |
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71 | err = bcm54810_config(phydev); |
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72 | if (err) |
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73 | @@ -395,39 +427,6 @@ static int bcm5481_config_aneg(struct ph |
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74 | return ret; |
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75 | } |
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76 | |||
77 | -static int bcm54612e_config_aneg(struct phy_device *phydev) |
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78 | -{ |
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79 | - int ret; |
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80 | - |
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81 | - /* First, auto-negotiate. */ |
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82 | - ret = genphy_config_aneg(phydev); |
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83 | - |
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84 | - /* Clear TX internal delay unless requested. */ |
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85 | - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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86 | - (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) { |
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87 | - /* Disable TXD to GTXCLK clock delay (default set) */ |
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88 | - /* Bit 9 is the only field in shadow register 00011 */ |
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89 | - bcm_phy_write_shadow(phydev, 0x03, 0); |
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90 | - } |
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91 | - |
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92 | - /* Clear RX internal delay unless requested. */ |
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93 | - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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94 | - (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) { |
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95 | - u16 reg; |
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96 | - |
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97 | - reg = bcm54xx_auxctl_read(phydev, |
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98 | - MII_BCM54XX_AUXCTL_SHDWSEL_MISC); |
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99 | - /* Disable RXD to RXC delay (default set) */ |
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100 | - reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW; |
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101 | - /* Clear shadow selector field */ |
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102 | - reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; |
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103 | - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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104 | - MII_BCM54XX_AUXCTL_MISC_WREN | reg); |
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105 | - } |
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106 | - |
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107 | - return ret; |
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108 | -} |
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109 | - |
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110 | static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) |
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111 | { |
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112 | int val; |
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113 | @@ -594,7 +593,7 @@ static struct phy_driver broadcom_driver |
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114 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, |
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115 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
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116 | .config_init = bcm54xx_config_init, |
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117 | - .config_aneg = bcm54612e_config_aneg, |
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118 | + .config_aneg = genphy_config_aneg, |
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119 | .read_status = genphy_read_status, |
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120 | .ack_interrupt = bcm_phy_ack_intr, |
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121 | .config_intr = bcm_phy_config_intr, |