OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From ce81398dccb984855de606b75db25eddecdaa9e5 Mon Sep 17 00:00:00 2001 |
2 | From: Linus Walleij <linus.walleij@linaro.org> |
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3 | Date: Wed, 10 Oct 2018 20:25:39 +0200 |
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4 | Subject: [PATCH 02/18] pinctrl: gemini: Fix up TVC clock group |
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5 | |||
6 | The previous fix made the TVC clock get muxed in on the |
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7 | D-Link DIR-685 instead of giving nagging warnings of this |
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8 | not working. Not good. We didn't want that, as it breaks |
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9 | video. |
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10 | |||
11 | Create a specific group for the TVC CLK, and break out |
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12 | a specific GPIO group for it on the SL3516 so we can use |
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13 | that line as GPIO if we don't need the TVC CLK. |
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14 | |||
15 | Fixes: d17f477c5bc6 ("pinctrl: gemini: Mask and set properly") |
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16 | Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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17 | --- |
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18 | drivers/pinctrl/pinctrl-gemini.c | 44 ++++++++++++++++++++++++++------ |
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19 | 1 file changed, 36 insertions(+), 8 deletions(-) |
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20 | |||
21 | --- a/drivers/pinctrl/pinctrl-gemini.c |
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22 | +++ b/drivers/pinctrl/pinctrl-gemini.c |
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23 | @@ -591,13 +591,16 @@ static const unsigned int tvc_3512_pins[ |
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24 | 319, /* TVC_DATA[1] */ |
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25 | 301, /* TVC_DATA[2] */ |
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26 | 283, /* TVC_DATA[3] */ |
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27 | - 265, /* TVC_CLK */ |
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28 | 320, /* TVC_DATA[4] */ |
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29 | 302, /* TVC_DATA[5] */ |
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30 | 284, /* TVC_DATA[6] */ |
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31 | 266, /* TVC_DATA[7] */ |
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32 | }; |
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33 | |||
34 | +static const unsigned int tvc_clk_3512_pins[] = { |
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35 | + 265, /* TVC_CLK */ |
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36 | +}; |
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37 | + |
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38 | /* NAND flash pins */ |
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39 | static const unsigned int nflash_3512_pins[] = { |
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40 | 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, |
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41 | @@ -629,7 +632,7 @@ static const unsigned int pflash_3512_pi |
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42 | /* Serial flash pins CE0, CE1, DI, DO, CK */ |
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43 | static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; |
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44 | |||
45 | -/* The GPIO0A (0) pin overlap with TVC and extended parallel flash */ |
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46 | +/* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */ |
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47 | static const unsigned int gpio0a_3512_pins[] = { 265 }; |
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48 | |||
49 | /* The GPIO0B (1-4) pins overlap with TVC and ICE */ |
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50 | @@ -823,7 +826,13 @@ static const struct gemini_pin_group gem |
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51 | .num_pins = ARRAY_SIZE(tvc_3512_pins), |
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52 | /* Conflict with character LCD and ICE */ |
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53 | .mask = LCD_PADS_ENABLE, |
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54 | - .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, |
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55 | + .value = TVC_PADS_ENABLE, |
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56 | + }, |
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57 | + { |
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58 | + .name = "tvcclkgrp", |
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59 | + .pins = tvc_clk_3512_pins, |
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60 | + .num_pins = ARRAY_SIZE(tvc_clk_3512_pins), |
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61 | + .value = TVC_CLK_PAD_ENABLE, |
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62 | }, |
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63 | /* |
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64 | * The construction is done such that it is possible to use a serial |
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65 | @@ -860,8 +869,8 @@ static const struct gemini_pin_group gem |
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66 | .name = "gpio0agrp", |
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67 | .pins = gpio0a_3512_pins, |
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68 | .num_pins = ARRAY_SIZE(gpio0a_3512_pins), |
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69 | - /* Conflict with TVC */ |
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70 | - .mask = TVC_PADS_ENABLE, |
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71 | + /* Conflict with TVC CLK */ |
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72 | + .mask = TVC_CLK_PAD_ENABLE, |
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73 | }, |
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74 | { |
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75 | .name = "gpio0bgrp", |
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76 | @@ -1531,13 +1540,16 @@ static const unsigned int tvc_3516_pins[ |
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77 | 311, /* TVC_DATA[1] */ |
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78 | 394, /* TVC_DATA[2] */ |
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79 | 374, /* TVC_DATA[3] */ |
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80 | - 333, /* TVC_CLK */ |
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81 | 354, /* TVC_DATA[4] */ |
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82 | 395, /* TVC_DATA[5] */ |
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83 | 312, /* TVC_DATA[6] */ |
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84 | 334, /* TVC_DATA[7] */ |
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85 | }; |
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86 | |||
87 | +static const unsigned int tvc_clk_3516_pins[] = { |
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88 | + 333, /* TVC_CLK */ |
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89 | +}; |
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90 | + |
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91 | /* NAND flash pins */ |
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92 | static const unsigned int nflash_3516_pins[] = { |
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93 | 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, |
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94 | @@ -1570,7 +1582,7 @@ static const unsigned int pflash_3516_pi |
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95 | static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; |
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96 | |||
97 | /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ |
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98 | -static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 }; |
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99 | +static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 }; |
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100 | |||
101 | /* The GPIO0B (5-7) pins overlap with ICE */ |
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102 | static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; |
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103 | @@ -1602,6 +1614,9 @@ static const unsigned int gpio0j_3516_pi |
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104 | /* The GPIO0K (30,31) pins overlap with NAND flash */ |
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105 | static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; |
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106 | |||
107 | +/* The GPIO0L (0) pins overlap with TVC_CLK */ |
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108 | +static const unsigned int gpio0l_3516_pins[] = { 333 }; |
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109 | + |
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110 | /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ |
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111 | static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; |
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112 | |||
113 | @@ -1761,7 +1776,13 @@ static const struct gemini_pin_group gem |
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114 | .num_pins = ARRAY_SIZE(tvc_3516_pins), |
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115 | /* Conflict with character LCD */ |
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116 | .mask = LCD_PADS_ENABLE, |
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117 | - .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, |
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118 | + .value = TVC_PADS_ENABLE, |
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119 | + }, |
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120 | + { |
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121 | + .name = "tvcclkgrp", |
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122 | + .pins = tvc_clk_3516_pins, |
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123 | + .num_pins = ARRAY_SIZE(tvc_clk_3516_pins), |
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124 | + .value = TVC_CLK_PAD_ENABLE, |
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125 | }, |
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126 | /* |
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127 | * The construction is done such that it is possible to use a serial |
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128 | @@ -1873,6 +1894,13 @@ static const struct gemini_pin_group gem |
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129 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, |
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130 | }, |
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131 | { |
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132 | + .name = "gpio0lgrp", |
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133 | + .pins = gpio0l_3516_pins, |
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134 | + .num_pins = ARRAY_SIZE(gpio0l_3516_pins), |
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135 | + /* Conflict with TVE CLK */ |
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136 | + .mask = TVC_CLK_PAD_ENABLE, |
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137 | + }, |
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138 | + { |
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139 | .name = "gpio1agrp", |
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140 | .pins = gpio1a_3516_pins, |
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141 | .num_pins = ARRAY_SIZE(gpio1a_3516_pins), |