OpenWrt – Blame information for rev 1
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1 | office | 1 | From 4347a0b0699989b889857c9d4ccfbce339859f13 Mon Sep 17 00:00:00 2001 |
2 | From: Linus Walleij <linus.walleij@linaro.org> |
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3 | Date: Mon, 16 Oct 2017 22:54:25 +0200 |
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4 | Subject: [PATCH 19/31] watchdog: ftwdt010: Make interrupt optional |
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5 | |||
6 | The Moxart does not appear to be using the interrupt from the |
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7 | watchdog timer, maybe it's not even routed, so as to support |
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8 | more architectures with this driver, make the interrupt |
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9 | optional. |
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10 | |||
11 | While we are at it: actually enable the use of the interrupt |
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12 | if present by setting the right bit in the control register |
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13 | and define the missing control register bits. |
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14 | |||
15 | Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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16 | Reviewed-by: Guenter Roeck <linux@roeck-us.net> |
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17 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> |
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18 | Signed-off-by: Wim Van Sebroeck <wim@iguana.be> |
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19 | --- |
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20 | drivers/watchdog/ftwdt010_wdt.c | 30 ++++++++++++++++++------------ |
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21 | 1 file changed, 18 insertions(+), 12 deletions(-) |
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22 | |||
23 | --- a/drivers/watchdog/ftwdt010_wdt.c |
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24 | +++ b/drivers/watchdog/ftwdt010_wdt.c |
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25 | @@ -30,6 +30,8 @@ |
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26 | #define WDRESTART_MAGIC 0x5AB9 |
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27 | |||
28 | #define WDCR_CLOCK_5MHZ BIT(4) |
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29 | +#define WDCR_WDEXT BIT(3) |
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30 | +#define WDCR_WDINTR BIT(2) |
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31 | #define WDCR_SYS_RST BIT(1) |
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32 | #define WDCR_ENABLE BIT(0) |
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33 | |||
34 | @@ -39,6 +41,7 @@ struct ftwdt010_wdt { |
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35 | struct watchdog_device wdd; |
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36 | struct device *dev; |
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37 | void __iomem *base; |
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38 | + bool has_irq; |
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39 | }; |
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40 | |||
41 | static inline |
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42 | @@ -50,14 +53,17 @@ struct ftwdt010_wdt *to_ftwdt010_wdt(str |
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43 | static int ftwdt010_wdt_start(struct watchdog_device *wdd) |
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44 | { |
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45 | struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd); |
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46 | + u32 enable; |
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47 | |||
48 | writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); |
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49 | writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); |
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50 | /* set clock before enabling */ |
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51 | - writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, |
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52 | - gwdt->base + FTWDT010_WDCR); |
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53 | - writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, |
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54 | - gwdt->base + FTWDT010_WDCR); |
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55 | + enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST; |
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56 | + writel(enable, gwdt->base + FTWDT010_WDCR); |
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57 | + if (gwdt->has_irq) |
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58 | + enable |= WDCR_WDINTR; |
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59 | + enable |= WDCR_ENABLE; |
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60 | + writel(enable, gwdt->base + FTWDT010_WDCR); |
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61 | |||
62 | return 0; |
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63 | } |
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64 | @@ -133,10 +139,6 @@ static int ftwdt010_wdt_probe(struct pla |
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65 | if (IS_ERR(gwdt->base)) |
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66 | return PTR_ERR(gwdt->base); |
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67 | |||
68 | - irq = platform_get_irq(pdev, 0); |
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69 | - if (!irq) |
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70 | - return -EINVAL; |
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71 | - |
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72 | gwdt->dev = dev; |
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73 | gwdt->wdd.info = &ftwdt010_wdt_info; |
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74 | gwdt->wdd.ops = &ftwdt010_wdt_ops; |
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75 | @@ -158,10 +160,14 @@ static int ftwdt010_wdt_probe(struct pla |
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76 | writel(reg, gwdt->base + FTWDT010_WDCR); |
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77 | } |
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78 | |||
79 | - ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0, |
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80 | - "watchdog bark", gwdt); |
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81 | - if (ret) |
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82 | - return ret; |
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83 | + irq = platform_get_irq(pdev, 0); |
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84 | + if (irq) { |
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85 | + ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0, |
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86 | + "watchdog bark", gwdt); |
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87 | + if (ret) |
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88 | + return ret; |
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89 | + gwdt->has_irq = true; |
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90 | + } |
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91 | |||
92 | ret = devm_watchdog_register_device(dev, &gwdt->wdd); |
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93 | if (ret) { |