OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
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1 | office | 1 | From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 30 Nov 2014 14:53:12 +0100 |
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4 | Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq |
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5 | controller |
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6 | |||
7 | Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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8 | --- |
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9 | .../brcm,bcm6345-periph-intc.txt | 50 +++ |
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10 | drivers/irqchip/Kconfig | 4 + |
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11 | drivers/irqchip/Makefile | 1 + |
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12 | drivers/irqchip/irq-bcm6345-periph.c | 339 ++++++++++++++++++++ |
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13 | include/linux/irqchip/irq-bcm6345-periph.h | 16 + |
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14 | 5 files changed, 410 insertions(+) |
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15 | create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt |
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16 | create mode 100644 drivers/irqchip/irq-bcm6345-periph.c |
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17 | create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h |
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18 | |||
19 | --- /dev/null |
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20 | +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt |
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21 | @@ -0,0 +1,50 @@ |
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22 | +Broadcom BCM6345 Level 1 periphery interrupt controller |
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23 | + |
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24 | +This block is a interrupt controller that is typically connected directly |
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25 | +to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since |
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26 | +BCM6345 has contained this hardware. |
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27 | + |
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28 | +Key elements of the hardware design include: |
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29 | + |
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30 | +- 32, 64, or 128 incoming level IRQ lines |
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31 | + |
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32 | +- All onchip peripherals are wired directly to an L2 input |
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33 | + |
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34 | +- A separate instance of the register set for each CPU, allowing individual |
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35 | + peripheral IRQs to be routed to any CPU |
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36 | + |
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37 | +- No atomic mask/unmask operations |
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38 | + |
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39 | +- No polarity/level/edge settings |
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40 | + |
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41 | +- No FIFO or priority encoder logic; software is expected to read all |
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42 | + 1-4 status words to determine which IRQs are pending |
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43 | + |
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44 | +Required properties: |
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45 | + |
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46 | +- compatible: Should be "brcm,bcm6345-periph-intc". |
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47 | +- reg: Specifies the base physical address and size of the registers. |
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48 | + Multiple register addresses may be specified, and must match the amount of |
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49 | + parent interrupts. |
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50 | +- interrupt-controller: Identifies the node as an interrupt controller. |
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51 | +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt |
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52 | + source, should be 1. |
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53 | +- interrupt-parent: Specifies the phandle to the parent interrupt controller |
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54 | + this one is cascaded from. |
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55 | +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller |
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56 | + node, valid values depend on the type of parent interrupt controller. |
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57 | + Multiple lines are used to route interrupts to different cpus, with the first |
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58 | + assumed to be for the boot CPU. |
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59 | + |
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60 | +Example: |
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61 | + |
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62 | +periph_intc: interrupt-controller@f0406800 { |
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63 | + compatible = "brcm,bcm6345-periph-intc"; |
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64 | + reg = <0x10000020 0x10>, <0x10000030 0x10>; |
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65 | + |
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66 | + interrupt-controller; |
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67 | + #interrupt-cells = <1>; |
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68 | + |
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69 | + interrupt-parent = <&cpu_intc>; |
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70 | + interrupts = <2>, <3>; |
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71 | +}; |
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72 | --- a/drivers/irqchip/Kconfig |
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73 | +++ b/drivers/irqchip/Kconfig |
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74 | @@ -110,6 +110,10 @@ config BRCMSTB_L2_IRQ |
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75 | select GENERIC_IRQ_CHIP |
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76 | select IRQ_DOMAIN |
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77 | |||
78 | +config BCM6345_PERIPH_IRQ |
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79 | + bool |
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80 | + select IRQ_DOMAIN |
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81 | + |
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82 | config DW_APB_ICTL |
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83 | bool |
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84 | select GENERIC_IRQ_CHIP |
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85 | --- a/drivers/irqchip/Makefile |
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86 | +++ b/drivers/irqchip/Makefile |
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87 | @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o |
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88 | obj-$(CONFIG_IRQ_MXS) += irq-mxs.o |
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89 | obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o |
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90 | obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o |
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91 | +obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o |
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92 | obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o |
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93 | obj-$(CONFIG_METAG) += irq-metag-ext.o |
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94 | obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o |
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95 | --- /dev/null |
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96 | +++ b/drivers/irqchip/irq-bcm6345-periph.c |
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97 | @@ -0,0 +1,339 @@ |
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98 | +/* |
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99 | + * This file is subject to the terms and conditions of the GNU General Public |
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100 | + * License. See the file "COPYING" in the main directory of this archive |
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101 | + * for more details. |
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102 | + * |
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103 | + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org> |
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104 | + */ |
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105 | + |
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106 | +#include <linux/ioport.h> |
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107 | +#include <linux/irq.h> |
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108 | +#include <linux/irqchip.h> |
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109 | +#include <linux/irqchip/chained_irq.h> |
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110 | +#include <linux/irqchip/irq-bcm6345-periph.h> |
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111 | +#include <linux/kernel.h> |
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112 | +#include <linux/of.h> |
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113 | +#include <linux/of_irq.h> |
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114 | +#include <linux/of_address.h> |
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115 | +#include <linux/slab.h> |
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116 | +#include <linux/spinlock.h> |
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117 | + |
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118 | +#ifdef CONFIG_BCM63XX |
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119 | +#include <asm/mach-bcm63xx/bcm63xx_irq.h> |
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120 | + |
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121 | +#define VIRQ_BASE IRQ_INTERNAL_BASE |
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122 | +#else |
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123 | +#define VIRQ_BASE 0 |
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124 | +#endif |
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125 | + |
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126 | +#define MAX_WORDS 4 |
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127 | +#define MAX_PARENT_IRQS 2 |
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128 | +#define IRQS_PER_WORD 32 |
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129 | + |
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130 | +struct intc_block { |
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131 | + int parent_irq; |
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132 | + void __iomem *base; |
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133 | + void __iomem *en_reg[MAX_WORDS]; |
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134 | + void __iomem *status_reg[MAX_WORDS]; |
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135 | + u32 mask_cache[MAX_WORDS]; |
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136 | +}; |
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137 | + |
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138 | +struct intc_data { |
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139 | + struct irq_chip chip; |
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140 | + struct intc_block block[MAX_PARENT_IRQS]; |
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141 | + |
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142 | + int num_words; |
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143 | + |
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144 | + struct irq_domain *domain; |
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145 | + raw_spinlock_t lock; |
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146 | +}; |
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147 | + |
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148 | +static void bcm6345_periph_irq_handle(struct irq_desc *desc) |
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149 | +{ |
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150 | + struct intc_data *data = irq_desc_get_handler_data(desc); |
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151 | + struct irq_chip *chip = irq_desc_get_chip(desc); |
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152 | + struct intc_block *block; |
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153 | + unsigned int irq = irq_desc_get_irq(desc); |
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154 | + unsigned int idx; |
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155 | + |
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156 | + chained_irq_enter(chip, desc); |
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157 | + |
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158 | + for (idx = 0; idx < MAX_PARENT_IRQS; idx++) |
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159 | + if (irq == data->block[idx].parent_irq) |
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160 | + block = &data->block[idx]; |
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161 | + |
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162 | + for (idx = 0; idx < data->num_words; idx++) { |
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163 | + int base = idx * IRQS_PER_WORD; |
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164 | + unsigned long pending; |
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165 | + int hw_irq; |
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166 | + |
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167 | + raw_spin_lock(&data->lock); |
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168 | + pending = __raw_readl(block->en_reg[idx]) & |
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169 | + __raw_readl(block->status_reg[idx]); |
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170 | + raw_spin_unlock(&data->lock); |
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171 | + |
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172 | + for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) { |
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173 | + int virq; |
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174 | + |
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175 | + virq = irq_find_mapping(data->domain, base + hw_irq); |
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176 | + generic_handle_irq(virq); |
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177 | + } |
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178 | + } |
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179 | + |
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180 | + chained_irq_exit(chip, desc); |
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181 | +} |
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182 | + |
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183 | +static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit, |
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184 | + bool enable) |
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185 | +{ |
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186 | + u32 val; |
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187 | + |
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188 | + val = __raw_readl(block->en_reg[reg]); |
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189 | + if (enable) |
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190 | + val |= BIT(bit); |
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191 | + else |
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192 | + val &= ~BIT(bit); |
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193 | + __raw_writel(val, block->en_reg[reg]); |
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194 | +} |
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195 | + |
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196 | +static void bcm6345_periph_irq_mask(struct irq_data *data) |
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197 | +{ |
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198 | + unsigned int i, reg, bit; |
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199 | + struct intc_data *priv = data->domain->host_data; |
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200 | + irq_hw_number_t hwirq = irqd_to_hwirq(data); |
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201 | + |
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202 | + reg = hwirq / IRQS_PER_WORD; |
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203 | + bit = hwirq % IRQS_PER_WORD; |
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204 | + |
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205 | + raw_spin_lock(&priv->lock); |
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206 | + for (i = 0; i < MAX_PARENT_IRQS; i++) { |
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207 | + struct intc_block *block = &priv->block[i]; |
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208 | + |
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209 | + if (!block->parent_irq) |
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210 | + break; |
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211 | + |
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212 | + __bcm6345_periph_enable(block, reg, bit, false); |
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213 | + } |
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214 | + raw_spin_unlock(&priv->lock); |
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215 | +} |
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216 | + |
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217 | +static void bcm6345_periph_irq_unmask(struct irq_data *data) |
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218 | +{ |
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219 | + struct intc_data *priv = data->domain->host_data; |
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220 | + irq_hw_number_t hwirq = irqd_to_hwirq(data); |
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221 | + unsigned int i, reg, bit; |
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222 | + |
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223 | + reg = hwirq / IRQS_PER_WORD; |
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224 | + bit = hwirq % IRQS_PER_WORD; |
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225 | + |
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226 | + raw_spin_lock(&priv->lock); |
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227 | + for (i = 0; i < MAX_PARENT_IRQS; i++) { |
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228 | + struct intc_block *block = &priv->block[i]; |
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229 | + |
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230 | + if (!block->parent_irq) |
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231 | + break; |
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232 | + |
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233 | + if (block->mask_cache[reg] & BIT(bit)) |
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234 | + __bcm6345_periph_enable(block, reg, bit, true); |
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235 | + else |
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236 | + __bcm6345_periph_enable(block, reg, bit, false); |
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237 | + } |
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238 | + raw_spin_unlock(&priv->lock); |
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239 | +} |
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240 | + |
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241 | +#ifdef CONFIG_SMP |
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242 | +static int bcm6345_periph_set_affinity(struct irq_data *data, |
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243 | + const struct cpumask *mask, bool force) |
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244 | +{ |
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245 | + irq_hw_number_t hwirq = irqd_to_hwirq(data); |
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246 | + struct intc_data *priv = data->domain->host_data; |
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247 | + unsigned int i, reg, bit; |
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248 | + unsigned long flags; |
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249 | + bool enabled; |
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250 | + int cpu; |
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251 | + |
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252 | + reg = hwirq / IRQS_PER_WORD; |
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253 | + bit = hwirq % IRQS_PER_WORD; |
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254 | + |
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255 | + /* we could route to more than one cpu, but performance |
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256 | + suffers, so fix it to one. |
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257 | + */ |
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258 | + cpu = cpumask_any_and(mask, cpu_online_mask); |
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259 | + if (cpu >= nr_cpu_ids) |
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260 | + return -EINVAL; |
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261 | + |
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262 | + if (cpu >= MAX_PARENT_IRQS) |
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263 | + return -EINVAL; |
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264 | + |
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265 | + if (!priv->block[cpu].parent_irq) |
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266 | + return -EINVAL; |
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267 | + |
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268 | + raw_spin_lock_irqsave(&priv->lock, flags); |
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269 | + enabled = !irqd_irq_masked(data); |
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270 | + for (i = 0; i < MAX_PARENT_IRQS; i++) { |
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271 | + struct intc_block *block = &priv->block[i]; |
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272 | + |
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273 | + if (!block->parent_irq) |
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274 | + break; |
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275 | + |
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276 | + if (i == cpu) { |
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277 | + block->mask_cache[reg] |= BIT(bit); |
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278 | + __bcm6345_periph_enable(block, reg, bit, enabled); |
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279 | + } else { |
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280 | + block->mask_cache[reg] &= ~BIT(bit); |
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281 | + __bcm6345_periph_enable(block, reg, bit, false); |
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282 | + } |
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283 | + } |
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284 | + raw_spin_unlock_irqrestore(&priv->lock, flags); |
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285 | + |
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286 | + return 0; |
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287 | +} |
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288 | +#endif |
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289 | + |
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290 | +static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq, |
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291 | + irq_hw_number_t hw) |
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292 | +{ |
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293 | + struct intc_data *priv = d->host_data; |
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294 | + |
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295 | + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); |
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296 | + |
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297 | + return 0; |
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298 | +} |
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299 | + |
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300 | +static const struct irq_domain_ops bcm6345_periph_domain_ops = { |
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301 | + .xlate = irq_domain_xlate_onecell, |
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302 | + .map = bcm6345_periph_map, |
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303 | +}; |
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304 | + |
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305 | +static int __init __bcm6345_periph_intc_init(struct device_node *node, |
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306 | + int num_blocks, int *irq, |
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307 | + void __iomem **base, int num_words) |
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308 | +{ |
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309 | + struct intc_data *data; |
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310 | + unsigned int i, w, status_offset; |
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311 | + |
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312 | + data = kzalloc(sizeof(*data), GFP_KERNEL); |
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313 | + if (!data) |
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314 | + return -ENOMEM; |
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315 | + |
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316 | + raw_spin_lock_init(&data->lock); |
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317 | + |
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318 | + status_offset = num_words * sizeof(u32); |
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319 | + |
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320 | + for (i = 0; i < num_blocks; i++) { |
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321 | + struct intc_block *block = &data->block[i]; |
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322 | + |
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323 | + block->parent_irq = irq[i]; |
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324 | + block->base = base[i]; |
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325 | + |
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326 | + for (w = 0; w < num_words; w++) { |
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327 | + int word_offset = sizeof(u32) * ((num_words - w) - 1); |
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328 | + |
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329 | + block->en_reg[w] = base[i] + word_offset; |
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330 | + block->status_reg[w] = base[i] + status_offset; |
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331 | + block->status_reg[w] += word_offset; |
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332 | + |
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333 | + /* route all interrupts to line 0 by default */ |
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334 | + if (i == 0) |
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335 | + block->mask_cache[w] = 0xffffffff; |
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336 | + } |
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337 | + |
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338 | + irq_set_handler_data(block->parent_irq, data); |
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339 | + irq_set_chained_handler(block->parent_irq, |
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340 | + bcm6345_periph_irq_handle); |
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341 | + } |
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342 | + |
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343 | + data->num_words = num_words; |
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344 | + |
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345 | + data->chip.name = "bcm6345-periph-intc"; |
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346 | + data->chip.irq_mask = bcm6345_periph_irq_mask; |
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347 | + data->chip.irq_unmask = bcm6345_periph_irq_unmask; |
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348 | + |
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349 | +#ifdef CONFIG_SMP |
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350 | + if (num_blocks > 1) |
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351 | + data->chip.irq_set_affinity = bcm6345_periph_set_affinity; |
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352 | +#endif |
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353 | + |
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354 | + data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words, |
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355 | + VIRQ_BASE, |
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356 | + &bcm6345_periph_domain_ops, data); |
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357 | + if (!data->domain) { |
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358 | + kfree(data); |
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359 | + return -EINVAL; |
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360 | + } |
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361 | + |
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362 | + return 0; |
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363 | +} |
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364 | + |
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365 | +void __init bcm6345_periph_intc_init(int num_blocks, int *irq, |
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366 | + void __iomem **base, int num_words) |
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367 | +{ |
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368 | + __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words); |
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369 | +} |
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370 | + |
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371 | +#ifdef CONFIG_OF |
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372 | +static int __init bcm6345_periph_of_init(struct device_node *node, |
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373 | + struct device_node *parent) |
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374 | +{ |
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375 | + struct resource res; |
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376 | + int num_irqs, ret = -EINVAL; |
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377 | + int irqs[MAX_PARENT_IRQS] = { 0 }; |
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378 | + void __iomem *bases[MAX_PARENT_IRQS] = { NULL }; |
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379 | + int words = 0; |
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380 | + int i; |
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381 | + |
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382 | + num_irqs = of_irq_count(node); |
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383 | + |
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384 | + if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS) |
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385 | + return -EINVAL; |
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386 | + |
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387 | + for (i = 0; i < num_irqs; i++) { |
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388 | + resource_size_t size; |
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389 | + |
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390 | + irqs[i] = irq_of_parse_and_map(node, i); |
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391 | + if (!irqs[i]) |
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392 | + goto out_unmap; |
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393 | + |
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394 | + if (of_address_to_resource(node, i, &res)) |
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395 | + goto out_unmap; |
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396 | + |
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397 | + size = resource_size(&res); |
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398 | + switch (size) { |
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399 | + case 8: |
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400 | + case 16: |
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401 | + case 32: |
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402 | + size = size / 8; |
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403 | + break; |
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404 | + default: |
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405 | + goto out_unmap; |
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406 | + } |
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407 | + |
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408 | + if (words && words != size) { |
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409 | + ret = -EINVAL; |
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410 | + goto out_unmap; |
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411 | + } |
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412 | + words = size; |
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413 | + |
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414 | + bases[i] = of_iomap(node, i); |
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415 | + if (!bases[i]) { |
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416 | + ret = -ENOMEM; |
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417 | + goto out_unmap; |
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418 | + } |
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419 | + } |
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420 | + |
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421 | + ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words); |
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422 | + if (!ret) |
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423 | + return 0; |
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424 | + |
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425 | +out_unmap: |
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426 | + for (i = 0; i < num_irqs; i++) { |
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427 | + iounmap(bases[i]); |
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428 | + irq_dispose_mapping(irqs[i]); |
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429 | + } |
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430 | + |
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431 | + return ret; |
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432 | +} |
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433 | + |
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434 | +IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-l1-intc", |
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435 | + bcm6345_periph_of_init); |
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436 | +#endif |
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437 | --- /dev/null |
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438 | +++ b/include/linux/irqchip/irq-bcm6345-periph.h |
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439 | @@ -0,0 +1,16 @@ |
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440 | +/* |
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441 | + * This file is subject to the terms and conditions of the GNU General Public |
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442 | + * License. See the file "COPYING" in the main directory of this archive |
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443 | + * for more details. |
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444 | + * |
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445 | + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
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446 | + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr> |
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447 | + */ |
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448 | + |
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449 | +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H |
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450 | +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H |
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451 | + |
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452 | +void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base, |
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453 | + int num_words); |
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454 | + |
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455 | +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */ |