OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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1 | office | 1 | From b98027285bd1fa95da0645a4234a5fc1f1a83f92 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Sun, 26 Feb 2017 11:59:52 +0100 |
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4 | Subject: [PATCH V2 8/8] MIPS: BCM63XX: split out swpkt_sar/usb clocks |
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5 | |||
6 | Make the secondary switch clocks their own clocks. This allows proper |
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7 | enable reference counting between SAR/XTM and the main switch clocks, |
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8 | and controlling them individually from drivers. |
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9 | |||
10 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
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11 | --- |
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12 | arch/mips/bcm63xx/clk.c | 61 +++++++++++++++++++++++++++++++++++++++++-------- |
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13 | 1 file changed, 51 insertions(+), 10 deletions(-) |
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14 | |||
15 | --- a/arch/mips/bcm63xx/clk.c |
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16 | +++ b/arch/mips/bcm63xx/clk.c |
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17 | @@ -122,21 +122,56 @@ static struct clk clk_ephy = { |
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18 | }; |
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19 | |||
20 | /* |
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21 | + * Ethernet switch SAR clock |
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22 | + */ |
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23 | +static void swpkt_sar_set(struct clk *clk, int enable) |
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24 | +{ |
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25 | + if (BCMCPU_IS_6368()) |
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26 | + bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable); |
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27 | + else |
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28 | + return; |
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29 | +} |
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30 | + |
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31 | +static struct clk clk_swpkt_sar = { |
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32 | + .set = swpkt_sar_set, |
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33 | +}; |
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34 | + |
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35 | +/* |
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36 | + * Ethernet switch USB clock |
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37 | + */ |
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38 | +static void swpkt_usb_set(struct clk *clk, int enable) |
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39 | +{ |
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40 | + if (BCMCPU_IS_6368()) |
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41 | + bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable); |
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42 | + else |
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43 | + return; |
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44 | +} |
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45 | + |
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46 | +static struct clk clk_swpkt_usb = { |
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47 | + .set = swpkt_usb_set, |
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48 | +}; |
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49 | + |
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50 | +/* |
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51 | * Ethernet switch clock |
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52 | */ |
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53 | static void enetsw_set(struct clk *clk, int enable) |
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54 | { |
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55 | - if (BCMCPU_IS_6328()) |
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56 | + if (BCMCPU_IS_6328()) { |
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57 | bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable); |
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58 | - else if (BCMCPU_IS_6362()) |
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59 | + } else if (BCMCPU_IS_6362()) { |
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60 | bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable); |
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61 | - else if (BCMCPU_IS_6368()) |
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62 | - bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | |
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63 | - CKCTL_6368_SWPKT_USB_EN | |
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64 | - CKCTL_6368_SWPKT_SAR_EN, |
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65 | - enable); |
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66 | - else |
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67 | + } else if (BCMCPU_IS_6368()) { |
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68 | + if (enable) { |
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69 | + clk_enable_unlocked(&clk_swpkt_sar); |
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70 | + clk_enable_unlocked(&clk_swpkt_usb); |
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71 | + } else { |
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72 | + clk_disable_unlocked(&clk_swpkt_usb); |
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73 | + clk_disable_unlocked(&clk_swpkt_sar); |
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74 | + } |
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75 | + bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable); |
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76 | + } else { |
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77 | return; |
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78 | + } |
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79 | |||
80 | if (enable) { |
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81 | /* reset switch core afer clock change */ |
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82 | @@ -261,8 +296,12 @@ static void xtm_set(struct clk *clk, int |
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83 | if (!BCMCPU_IS_6368()) |
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84 | return; |
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85 | |||
86 | - bcm_hwclock_set(CKCTL_6368_SAR_EN | |
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87 | - CKCTL_6368_SWPKT_SAR_EN, enable); |
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88 | + if (enable) |
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89 | + clk_enable_unlocked(&clk_swpkt_sar); |
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90 | + else |
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91 | + clk_disable_unlocked(&clk_swpkt_sar); |
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92 | + |
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93 | + bcm_hwclock_set(CKCTL_6368_SAR_EN, enable); |
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94 | |||
95 | if (enable) { |
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96 | /* reset sar core afer clock change */ |
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97 | @@ -451,6 +490,8 @@ static struct clk_lookup bcm6358_clks[] |
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98 | CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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99 | CLKDEV_INIT(NULL, "spi", &clk_spi), |
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100 | CLKDEV_INIT(NULL, "pcm", &clk_pcm), |
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101 | + CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar), |
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102 | + CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb), |
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103 | CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0), |
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104 | CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1), |
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105 | }; |