OpenWrt – Blame information for rev 1
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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | office | 1 | From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <john@phrozen.org> |
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| 3 | Date: Sun, 24 Jun 2018 09:39:41 +0200 |
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| 4 | Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code |
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| 5 | |||
| 6 | With the target now being fully OF based, we can drop the legacy clock |
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| 7 | registration code. All clocks are now probed via devicetree. |
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| 8 | |||
| 9 | Signed-off-by: John Crispin <john@phrozen.org> |
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| 10 | --- |
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| 11 | arch/mips/ath79/clock.c | 56 ------------------------------------------------ |
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| 12 | arch/mips/ath79/common.h | 3 --- |
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| 13 | 2 files changed, 59 deletions(-) |
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| 14 | |||
| 15 | --- a/arch/mips/ath79/clock.c |
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| 16 | +++ b/arch/mips/ath79/clock.c |
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| 17 | @@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v |
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| 18 | ath79_set_clk(ATH79_CLK_AHB, ahb_rate); |
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| 19 | } |
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| 20 | |||
| 21 | -void __init ath79_clocks_init(void) |
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| 22 | -{ |
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| 23 | - const char *wdt; |
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| 24 | - const char *uart; |
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| 25 | - |
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| 26 | - if (soc_is_ar71xx()) |
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| 27 | - ar71xx_clocks_init(ath79_pll_base); |
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| 28 | - else if (soc_is_ar724x() || soc_is_ar913x()) |
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| 29 | - ar724x_clocks_init(ath79_pll_base); |
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| 30 | - else if (soc_is_ar933x()) |
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| 31 | - ar933x_clocks_init(ath79_pll_base); |
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| 32 | - else if (soc_is_ar934x()) |
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| 33 | - ar934x_clocks_init(ath79_pll_base); |
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| 34 | - else if (soc_is_qca953x()) |
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| 35 | - qca953x_clocks_init(ath79_pll_base); |
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| 36 | - else if (soc_is_qca955x()) |
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| 37 | - qca955x_clocks_init(ath79_pll_base); |
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| 38 | - else if (soc_is_qca956x() || soc_is_tp9343()) |
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| 39 | - qca956x_clocks_init(ath79_pll_base); |
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| 40 | - else |
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| 41 | - BUG(); |
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| 42 | - |
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| 43 | - if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) { |
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| 44 | - wdt = "ahb"; |
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| 45 | - uart = "ahb"; |
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| 46 | - } else if (soc_is_ar933x()) { |
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| 47 | - wdt = "ahb"; |
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| 48 | - uart = "ref"; |
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| 49 | - } else { |
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| 50 | - wdt = "ref"; |
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| 51 | - uart = "ref"; |
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| 52 | - } |
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| 53 | - |
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| 54 | - clk_add_alias("wdt", NULL, wdt, NULL); |
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| 55 | - clk_add_alias("uart", NULL, uart, NULL); |
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| 56 | -} |
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| 57 | - |
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| 58 | -unsigned long __init |
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| 59 | -ath79_get_sys_clk_rate(const char *id) |
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| 60 | -{ |
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| 61 | - struct clk *clk; |
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| 62 | - unsigned long rate; |
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| 63 | - |
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| 64 | - clk = clk_get(NULL, id); |
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| 65 | - if (IS_ERR(clk)) |
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| 66 | - panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); |
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| 67 | - |
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| 68 | - rate = clk_get_rate(clk); |
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| 69 | - clk_put(clk); |
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| 70 | - |
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| 71 | - return rate; |
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| 72 | -} |
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| 73 | - |
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| 74 | -#ifdef CONFIG_OF |
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| 75 | static void __init ath79_clocks_init_dt(struct device_node *np) |
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| 76 | { |
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| 77 | struct clk *ref_clk; |
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| 78 | @@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p |
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| 79 | CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); |
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| 80 | CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); |
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| 81 | CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); |
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| 82 | - |
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| 83 | -#endif |
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| 84 | --- a/arch/mips/ath79/common.h |
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| 85 | +++ b/arch/mips/ath79/common.h |
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| 86 | @@ -19,9 +19,6 @@ |
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| 87 | #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) |
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| 88 | #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024) |
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| 89 | |||
| 90 | -void ath79_clocks_init(void); |
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| 91 | -unsigned long ath79_get_sys_clk_rate(const char *id); |
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| 92 | - |
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| 93 | void ath79_ddr_ctrl_init(void); |
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| 94 | |||
| 95 | #endif /* __ATH79_COMMON_H */ |