OpenWrt – Blame information for rev 4

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1 office 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
3 #include "ath79.dtsi"
4  
5 / {
6 compatible = "qca,ar7240";
7  
8 #address-cells = <1>;
9 #size-cells = <1>;
10  
11 chosen {
12 bootargs = "console=ttyS0,115200";
13 };
14  
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18  
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
23 reg = <0>;
24 };
25 };
26  
27 ahb: ahb {
28 apb {
29 ddr_ctrl: memory-controller@18000000 {
30 compatible = "qca,ar9132-ddr-controller",
31 "qca,ar7240-ddr-controller";
32 reg = <0x18000000 0x100>;
33  
34 #qca,ddr-wb-channel-cells = <1>;
35 };
36  
37 uart: uart@18020000 {
38 compatible = "ns16550a";
39 reg = <0x18020000 0x20>;
40 interrupts = <3>;
41  
42 clocks = <&pll ATH79_CLK_AHB>;
43 clock-names = "uart";
44  
45 reg-io-width = <4>;
46 reg-shift = <2>;
47 no-loopback-test;
48  
49 status = "disabled";
50 };
51  
52 gpio: gpio@18040000 {
53 compatible = "qca,ar7240-gpio",
54 "qca,ar7100-gpio";
55 reg = <0x18040000 0x30>;
56 interrupts = <2>;
57  
58 ngpios = <18>;
59  
60 gpio-controller;
61 #gpio-cells = <2>;
62  
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 };
66  
67 pinmux: pinmux@18040028 {
68 compatible = "pinctrl-single";
69  
70 reg = <0x18040028 0x8>;
71  
72 pinctrl-single,bit-per-mux;
73 pinctrl-single,register-width = <32>;
74 pinctrl-single,function-mask = <0x1>;
75 #pinctrl-cells = <2>;
76  
77 jtag_disable_pins: pinmux_jtag_disable_pins {
78 pinctrl-single,bits = <0x0 0x1 0x1>;
79 };
80 };
81  
82 pll: pll-controller@18050000 {
83 compatible = "qca,ar7240-pll", "syscon";
84 reg = <0x18050000 0x3c>;
85  
86 clock-names = "ref";
87 /* The board must provides the ref clock */
88  
89 #clock-cells = <1>;
90 clock-output-names = "cpu", "ddr", "ahb";
91 };
92  
93 wdt: wdt@18060008 {
94 compatible = "qca,ar7130-wdt";
95 reg = <0x18060008 0x8>;
96  
97 interrupts = <4>;
98  
99 clocks = <&pll ATH79_CLK_AHB>;
100 clock-names = "wdt";
101 };
102  
103 rst: reset-controller@1806001c {
104 compatible = "qca,ar7240-reset",
105 "qca,ar7100-reset";
106 reg = <0x1806001c 0x4>;
107  
108 #reset-cells = <1>;
109 };
110  
111 pcie: pcie-controller@180c0000 {
112 compatible = "qcom,ar7240-pci";
113 #address-cells = <3>;
114 #size-cells = <2>;
115 bus-range = <0x0 0x0>;
116 reg = <0x180c0000 0x1000>, /* CRP */
117 <0x180f0000 0x100>, /* CTRL */
118 <0x14000000 0x1000>; /* CFG */
119 reg-names = "crp_base", "ctrl_base", "cfg_base";
120 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
121 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
122 interrupt-parent = <&cpuintc>;
123 interrupts = <2>;
124  
125 interrupt-controller;
126 #interrupt-cells = <1>;
127  
128 interrupt-map-mask = <0 0 0 1>;
129 interrupt-map = <0 0 0 0 &pcie 0>;
130 status = "disabled";
131 };
132 };
133  
134 spi: spi@1f000000 {
135 compatible = "qca,ar7240-spi",
136 "qca,ar7100-spi";
137 reg = <0x1f000000 0x10>;
138  
139 clocks = <&pll ATH79_CLK_AHB>;
140 clock-names = "ahb";
141  
142 status = "disabled";
143  
144 #address-cells = <1>;
145 #size-cells = <0>;
146 };
147 };
148 };
149  
150 &cpuintc {
151 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
152 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
153 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
154 };