OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
2 | #include <dt-bindings/clock/ath79-clk.h> |
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3 | #include "ath79.dtsi" |
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4 | |||
5 | / { |
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6 | compatible = "qca,ar7240"; |
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7 | |||
8 | #address-cells = <1>; |
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9 | #size-cells = <1>; |
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10 | |||
11 | chosen { |
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12 | bootargs = "console=ttyS0,115200"; |
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13 | }; |
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14 | |||
15 | cpus { |
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16 | #address-cells = <1>; |
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17 | #size-cells = <0>; |
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18 | |||
19 | cpu@0 { |
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20 | device_type = "cpu"; |
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21 | compatible = "mips,mips24Kc"; |
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22 | clocks = <&pll ATH79_CLK_CPU>; |
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23 | reg = <0>; |
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24 | }; |
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25 | }; |
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26 | |||
27 | ahb: ahb { |
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28 | apb { |
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29 | ddr_ctrl: memory-controller@18000000 { |
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30 | compatible = "qca,ar9132-ddr-controller", |
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31 | "qca,ar7240-ddr-controller"; |
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32 | reg = <0x18000000 0x100>; |
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33 | |||
34 | #qca,ddr-wb-channel-cells = <1>; |
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35 | }; |
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36 | |||
37 | uart: uart@18020000 { |
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38 | compatible = "ns16550a"; |
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39 | reg = <0x18020000 0x20>; |
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40 | interrupts = <3>; |
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41 | |||
42 | clocks = <&pll ATH79_CLK_AHB>; |
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43 | clock-names = "uart"; |
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44 | |||
45 | reg-io-width = <4>; |
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46 | reg-shift = <2>; |
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47 | no-loopback-test; |
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48 | |||
49 | status = "disabled"; |
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50 | }; |
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51 | |||
52 | gpio: gpio@18040000 { |
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53 | compatible = "qca,ar7240-gpio", |
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54 | "qca,ar7100-gpio"; |
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55 | reg = <0x18040000 0x30>; |
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56 | interrupts = <2>; |
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57 | |||
58 | ngpios = <18>; |
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59 | |||
60 | gpio-controller; |
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61 | #gpio-cells = <2>; |
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62 | |||
63 | interrupt-controller; |
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64 | #interrupt-cells = <2>; |
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65 | }; |
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66 | |||
67 | pinmux: pinmux@18040028 { |
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68 | compatible = "pinctrl-single"; |
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69 | |||
70 | reg = <0x18040028 0x8>; |
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71 | |||
72 | pinctrl-single,bit-per-mux; |
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73 | pinctrl-single,register-width = <32>; |
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74 | pinctrl-single,function-mask = <0x1>; |
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75 | #pinctrl-cells = <2>; |
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76 | |||
77 | jtag_disable_pins: pinmux_jtag_disable_pins { |
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78 | pinctrl-single,bits = <0x0 0x1 0x1>; |
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79 | }; |
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80 | }; |
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81 | |||
82 | pll: pll-controller@18050000 { |
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83 | compatible = "qca,ar7240-pll", "syscon"; |
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84 | reg = <0x18050000 0x3c>; |
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85 | |||
86 | clock-names = "ref"; |
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87 | /* The board must provides the ref clock */ |
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88 | |||
89 | #clock-cells = <1>; |
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90 | clock-output-names = "cpu", "ddr", "ahb"; |
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91 | }; |
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92 | |||
93 | wdt: wdt@18060008 { |
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94 | compatible = "qca,ar7130-wdt"; |
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95 | reg = <0x18060008 0x8>; |
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96 | |||
97 | interrupts = <4>; |
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98 | |||
99 | clocks = <&pll ATH79_CLK_AHB>; |
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100 | clock-names = "wdt"; |
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101 | }; |
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102 | |||
103 | rst: reset-controller@1806001c { |
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104 | compatible = "qca,ar7240-reset", |
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105 | "qca,ar7100-reset"; |
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106 | reg = <0x1806001c 0x4>; |
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107 | |||
108 | #reset-cells = <1>; |
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109 | }; |
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110 | |||
111 | pcie: pcie-controller@180c0000 { |
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112 | compatible = "qcom,ar7240-pci"; |
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113 | #address-cells = <3>; |
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114 | #size-cells = <2>; |
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115 | bus-range = <0x0 0x0>; |
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116 | reg = <0x180c0000 0x1000>, /* CRP */ |
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117 | <0x180f0000 0x100>, /* CTRL */ |
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118 | <0x14000000 0x1000>; /* CFG */ |
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119 | reg-names = "crp_base", "ctrl_base", "cfg_base"; |
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120 | ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */ |
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121 | 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */ |
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122 | interrupt-parent = <&cpuintc>; |
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123 | interrupts = <2>; |
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124 | |||
125 | interrupt-controller; |
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126 | #interrupt-cells = <1>; |
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127 | |||
128 | interrupt-map-mask = <0 0 0 1>; |
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129 | interrupt-map = <0 0 0 0 &pcie 0>; |
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130 | status = "disabled"; |
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131 | }; |
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132 | }; |
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133 | |||
134 | spi: spi@1f000000 { |
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135 | compatible = "qca,ar7240-spi", |
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136 | "qca,ar7100-spi"; |
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137 | reg = <0x1f000000 0x10>; |
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138 | |||
139 | clocks = <&pll ATH79_CLK_AHB>; |
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140 | clock-names = "ahb"; |
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141 | |||
142 | status = "disabled"; |
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143 | |||
144 | #address-cells = <1>; |
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145 | #size-cells = <0>; |
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146 | }; |
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147 | }; |
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148 | }; |
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149 | |||
150 | &cpuintc { |
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151 | qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; |
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152 | qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, |
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153 | <&ddr_ctrl 0>, <&ddr_ctrl 1>; |
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154 | }; |