OpenWrt – Blame information for rev 1
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1 | office | 1 | //*---------------------------------------------------------------------------- |
2 | //* ATMEL Microcontroller Software Support - ROUSSET - |
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3 | //*---------------------------------------------------------------------------- |
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4 | //* The software is delivered "AS IS" without warranty or condition of any |
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5 | //* kind, either express, implied or statutory. This includes without |
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6 | //* limitation any warranty or condition with respect to merchantability or |
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7 | //* fitness for any particular purpose, or against the infringements of |
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8 | //* intellectual property rights of others. |
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9 | //*---------------------------------------------------------------------------- |
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10 | //* File Name : lib_AT91RM9200.h |
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11 | //* Object : AT91RM9200 inlined functions |
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12 | //* Generated : AT91 SW Application Group 11/19/2003 (17:20:51) |
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13 | //* |
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14 | //* CVS Reference : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002// |
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15 | //* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// |
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16 | //* CVS Reference : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003// |
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17 | //* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// |
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18 | //* CVS Reference : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003// |
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19 | //* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// |
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20 | //* CVS Reference : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002// |
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21 | //* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// |
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22 | //* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// |
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23 | //* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002// |
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24 | //* CVS Reference : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002// |
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25 | //* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002// |
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26 | //* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// |
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27 | //* CVS Reference : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003// |
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28 | //*---------------------------------------------------------------------------- |
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29 | |||
30 | #ifndef lib_AT91RM9200_H |
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31 | #define lib_AT91RM9200_H |
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32 | |||
33 | /* ***************************************************************************** |
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34 | SOFTWARE API FOR PDC |
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35 | ***************************************************************************** */ |
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36 | //*---------------------------------------------------------------------------- |
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37 | //* \fn AT91F_PDC_SetNextRx |
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38 | //* \brief Set the next receive transfer descriptor |
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39 | //*---------------------------------------------------------------------------- |
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40 | static inline void AT91F_PDC_SetNextRx ( |
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41 | AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
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42 | char *address, // \arg address to the next bloc to be received |
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43 | unsigned int bytes) // \arg number of bytes to be received |
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44 | { |
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45 | pPDC->PDC_RNPR = (unsigned int) address; |
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46 | pPDC->PDC_RNCR = bytes; |
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47 | } |
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48 | |||
49 | //*---------------------------------------------------------------------------- |
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50 | //* \fn AT91F_PDC_SetNextTx |
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51 | //* \brief Set the next transmit transfer descriptor |
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52 | //*---------------------------------------------------------------------------- |
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53 | static inline void AT91F_PDC_SetNextTx ( |
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54 | AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
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55 | char *address, // \arg address to the next bloc to be transmitted |
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56 | unsigned int bytes) // \arg number of bytes to be transmitted |
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57 | { |
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58 | pPDC->PDC_TNPR = (unsigned int) address; |
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59 | pPDC->PDC_TNCR = bytes; |
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60 | } |
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61 | |||
62 | //*---------------------------------------------------------------------------- |
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63 | //* \fn AT91F_PDC_SetRx |
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64 | //* \brief Set the receive transfer descriptor |
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65 | //*---------------------------------------------------------------------------- |
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66 | static inline void AT91F_PDC_SetRx ( |
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67 | AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
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68 | char *address, // \arg address to the next bloc to be received |
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69 | unsigned int bytes) // \arg number of bytes to be received |
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70 | { |
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71 | pPDC->PDC_RPR = (unsigned int) address; |
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72 | pPDC->PDC_RCR = bytes; |
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73 | } |
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74 | |||
75 | //*---------------------------------------------------------------------------- |
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76 | //* \fn AT91F_PDC_SetTx |
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77 | //* \brief Set the transmit transfer descriptor |
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78 | //*---------------------------------------------------------------------------- |
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79 | static inline void AT91F_PDC_SetTx ( |
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80 | AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
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81 | char *address, // \arg address to the next bloc to be transmitted |
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82 | unsigned int bytes) // \arg number of bytes to be transmitted |
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83 | { |
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84 | pPDC->PDC_TPR = (unsigned int) address; |
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85 | pPDC->PDC_TCR = bytes; |
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86 | } |
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87 | |||
88 | //*---------------------------------------------------------------------------- |
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89 | //* \fn AT91F_PDC_EnableTx |
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90 | //* \brief Enable transmit |
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91 | //*---------------------------------------------------------------------------- |
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92 | static inline void AT91F_PDC_EnableTx ( |
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93 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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94 | { |
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95 | pPDC->PDC_PTCR = AT91C_PDC_TXTEN; |
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96 | } |
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97 | |||
98 | //*---------------------------------------------------------------------------- |
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99 | //* \fn AT91F_PDC_EnableRx |
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100 | //* \brief Enable receive |
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101 | //*---------------------------------------------------------------------------- |
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102 | static inline void AT91F_PDC_EnableRx ( |
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103 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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104 | { |
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105 | pPDC->PDC_PTCR = AT91C_PDC_RXTEN; |
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106 | } |
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107 | |||
108 | //*---------------------------------------------------------------------------- |
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109 | //* \fn AT91F_PDC_DisableTx |
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110 | //* \brief Disable transmit |
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111 | //*---------------------------------------------------------------------------- |
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112 | static inline void AT91F_PDC_DisableTx ( |
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113 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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114 | { |
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115 | pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; |
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116 | } |
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117 | |||
118 | //*---------------------------------------------------------------------------- |
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119 | //* \fn AT91F_PDC_DisableRx |
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120 | //* \brief Disable receive |
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121 | //*---------------------------------------------------------------------------- |
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122 | static inline void AT91F_PDC_DisableRx ( |
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123 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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124 | { |
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125 | pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; |
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126 | } |
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127 | |||
128 | //*---------------------------------------------------------------------------- |
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129 | //* \fn AT91F_PDC_IsTxEmpty |
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130 | //* \brief Test if the current transfer descriptor has been sent |
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131 | //*---------------------------------------------------------------------------- |
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132 | static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete |
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133 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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134 | { |
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135 | return !(pPDC->PDC_TCR); |
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136 | } |
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137 | |||
138 | //*---------------------------------------------------------------------------- |
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139 | //* \fn AT91F_PDC_IsNextTxEmpty |
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140 | //* \brief Test if the next transfer descriptor has been moved to the current td |
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141 | //*---------------------------------------------------------------------------- |
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142 | static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete |
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143 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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144 | { |
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145 | return !(pPDC->PDC_TNCR); |
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146 | } |
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147 | |||
148 | //*---------------------------------------------------------------------------- |
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149 | //* \fn AT91F_PDC_IsRxEmpty |
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150 | //* \brief Test if the current transfer descriptor has been filled |
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151 | //*---------------------------------------------------------------------------- |
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152 | static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete |
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153 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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154 | { |
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155 | return !(pPDC->PDC_RCR); |
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156 | } |
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157 | |||
158 | //*---------------------------------------------------------------------------- |
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159 | //* \fn AT91F_PDC_IsNextRxEmpty |
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160 | //* \brief Test if the next transfer descriptor has been moved to the current td |
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161 | //*---------------------------------------------------------------------------- |
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162 | static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete |
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163 | AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
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164 | { |
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165 | return !(pPDC->PDC_RNCR); |
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166 | } |
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167 | |||
168 | //*---------------------------------------------------------------------------- |
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169 | //* \fn AT91F_PDC_Open |
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170 | //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX |
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171 | //*---------------------------------------------------------------------------- |
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172 | static inline void AT91F_PDC_Open ( |
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173 | AT91PS_PDC pPDC) // \arg pointer to a PDC controller |
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174 | { |
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175 | //* Disable the RX and TX PDC transfer requests |
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176 | AT91F_PDC_DisableRx(pPDC); |
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177 | AT91F_PDC_DisableTx(pPDC); |
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178 | |||
179 | //* Reset all Counter register Next buffer first |
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180 | AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); |
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181 | AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); |
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182 | AT91F_PDC_SetTx(pPDC, (char *) 0, 0); |
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183 | AT91F_PDC_SetRx(pPDC, (char *) 0, 0); |
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184 | |||
185 | //* Enable the RX and TX PDC transfer requests |
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186 | AT91F_PDC_EnableRx(pPDC); |
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187 | AT91F_PDC_EnableTx(pPDC); |
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188 | } |
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189 | |||
190 | //*---------------------------------------------------------------------------- |
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191 | //* \fn AT91F_PDC_Close |
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192 | //* \brief Close PDC: disable TX and RX reset transfer descriptors |
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193 | //*---------------------------------------------------------------------------- |
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194 | static inline void AT91F_PDC_Close ( |
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195 | AT91PS_PDC pPDC) // \arg pointer to a PDC controller |
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196 | { |
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197 | //* Disable the RX and TX PDC transfer requests |
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198 | AT91F_PDC_DisableRx(pPDC); |
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199 | AT91F_PDC_DisableTx(pPDC); |
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200 | |||
201 | //* Reset all Counter register Next buffer first |
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202 | AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); |
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203 | AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); |
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204 | AT91F_PDC_SetTx(pPDC, (char *) 0, 0); |
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205 | AT91F_PDC_SetRx(pPDC, (char *) 0, 0); |
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206 | |||
207 | } |
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208 | |||
209 | //*---------------------------------------------------------------------------- |
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210 | //* \fn AT91F_PDC_SendFrame |
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211 | //* \brief Close PDC: disable TX and RX reset transfer descriptors |
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212 | //*---------------------------------------------------------------------------- |
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213 | static inline unsigned int AT91F_PDC_SendFrame( |
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214 | AT91PS_PDC pPDC, |
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215 | char *pBuffer, |
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216 | unsigned int szBuffer, |
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217 | char *pNextBuffer, |
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218 | unsigned int szNextBuffer ) |
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219 | { |
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220 | if (AT91F_PDC_IsTxEmpty(pPDC)) { |
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221 | //* Buffer and next buffer can be initialized |
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222 | AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); |
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223 | AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); |
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224 | return 2; |
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225 | } |
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226 | else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { |
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227 | //* Only one buffer can be initialized |
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228 | AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); |
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229 | return 1; |
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230 | } |
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231 | else { |
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232 | //* All buffer are in use... |
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233 | return 0; |
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234 | } |
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235 | } |
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236 | |||
237 | //*---------------------------------------------------------------------------- |
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238 | //* \fn AT91F_PDC_ReceiveFrame |
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239 | //* \brief Close PDC: disable TX and RX reset transfer descriptors |
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240 | //*---------------------------------------------------------------------------- |
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241 | static inline unsigned int AT91F_PDC_ReceiveFrame ( |
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242 | AT91PS_PDC pPDC, |
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243 | char *pBuffer, |
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244 | unsigned int szBuffer, |
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245 | char *pNextBuffer, |
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246 | unsigned int szNextBuffer ) |
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247 | { |
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248 | if (AT91F_PDC_IsRxEmpty(pPDC)) { |
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249 | //* Buffer and next buffer can be initialized |
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250 | AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); |
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251 | AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); |
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252 | return 2; |
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253 | } |
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254 | else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { |
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255 | //* Only one buffer can be initialized |
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256 | AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); |
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257 | return 1; |
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258 | } |
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259 | else { |
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260 | //* All buffer are in use... |
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261 | return 0; |
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262 | } |
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263 | } |
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264 | /* ***************************************************************************** |
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265 | SOFTWARE API FOR DBGU |
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266 | ***************************************************************************** */ |
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267 | //*---------------------------------------------------------------------------- |
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268 | //* \fn AT91F_DBGU_InterruptEnable |
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269 | //* \brief Enable DBGU Interrupt |
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270 | //*---------------------------------------------------------------------------- |
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271 | static inline void AT91F_DBGU_InterruptEnable( |
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272 | AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller |
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273 | unsigned int flag) // \arg dbgu interrupt to be enabled |
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274 | { |
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275 | pDbgu->DBGU_IER = flag; |
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276 | } |
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277 | |||
278 | //*---------------------------------------------------------------------------- |
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279 | //* \fn AT91F_DBGU_InterruptDisable |
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280 | //* \brief Disable DBGU Interrupt |
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281 | //*---------------------------------------------------------------------------- |
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282 | static inline void AT91F_DBGU_InterruptDisable( |
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283 | AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller |
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284 | unsigned int flag) // \arg dbgu interrupt to be disabled |
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285 | { |
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286 | pDbgu->DBGU_IDR = flag; |
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287 | } |
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288 | |||
289 | //*---------------------------------------------------------------------------- |
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290 | //* \fn AT91F_DBGU_GetInterruptMaskStatus |
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291 | //* \brief Return DBGU Interrupt Mask Status |
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292 | //*---------------------------------------------------------------------------- |
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293 | static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status |
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294 | AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller |
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295 | { |
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296 | return pDbgu->DBGU_IMR; |
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297 | } |
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298 | |||
299 | //*---------------------------------------------------------------------------- |
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300 | //* \fn AT91F_DBGU_IsInterruptMasked |
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301 | //* \brief Test if DBGU Interrupt is Masked |
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302 | //*---------------------------------------------------------------------------- |
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303 | static inline int AT91F_DBGU_IsInterruptMasked( |
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304 | AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller |
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305 | unsigned int flag) // \arg flag to be tested |
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306 | { |
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307 | return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); |
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308 | } |
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309 | |||
310 | /* ***************************************************************************** |
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311 | SOFTWARE API FOR RTC |
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312 | ***************************************************************************** */ |
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313 | //*---------------------------------------------------------------------------- |
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314 | //* \fn AT91F_RTC_InterruptEnable |
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315 | //* \brief Enable RTC Interrupt |
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316 | //*---------------------------------------------------------------------------- |
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317 | static inline void AT91F_RTC_InterruptEnable( |
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318 | AT91PS_RTC pRtc, // \arg pointer to a RTC controller |
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319 | unsigned int flag) // \arg RTC interrupt to be enabled |
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320 | { |
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321 | pRtc->RTC_IER = flag; |
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322 | } |
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323 | |||
324 | //*---------------------------------------------------------------------------- |
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325 | //* \fn AT91F_RTC_InterruptDisable |
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326 | //* \brief Disable RTC Interrupt |
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327 | //*---------------------------------------------------------------------------- |
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328 | static inline void AT91F_RTC_InterruptDisable( |
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329 | AT91PS_RTC pRtc, // \arg pointer to a RTC controller |
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330 | unsigned int flag) // \arg RTC interrupt to be disabled |
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331 | { |
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332 | pRtc->RTC_IDR = flag; |
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333 | } |
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334 | |||
335 | //*---------------------------------------------------------------------------- |
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336 | //* \fn AT91F_RTC_GetInterruptMaskStatus |
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337 | //* \brief Return RTC Interrupt Mask Status |
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338 | //*---------------------------------------------------------------------------- |
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339 | static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status |
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340 | AT91PS_RTC pRtc) // \arg pointer to a RTC controller |
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341 | { |
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342 | return pRtc->RTC_IMR; |
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343 | } |
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344 | |||
345 | //*---------------------------------------------------------------------------- |
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346 | //* \fn AT91F_RTC_IsInterruptMasked |
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347 | //* \brief Test if RTC Interrupt is Masked |
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348 | //*---------------------------------------------------------------------------- |
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349 | static inline int AT91F_RTC_IsInterruptMasked( |
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350 | AT91PS_RTC pRtc, // \arg pointer to a RTC controller |
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351 | unsigned int flag) // \arg flag to be tested |
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352 | { |
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353 | return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag); |
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354 | } |
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355 | |||
356 | /* ***************************************************************************** |
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357 | SOFTWARE API FOR SSC |
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358 | ***************************************************************************** */ |
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359 | //* Define the standard I2S mode configuration |
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360 | |||
361 | //* Configuration to set in the SSC Transmit Clock Mode Register |
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362 | //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits |
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363 | //* nb_slot_by_frame : number of channels |
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364 | #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ |
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365 | AT91C_SSC_CKS_DIV +\ |
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366 | AT91C_SSC_CKO_CONTINOUS +\ |
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367 | AT91C_SSC_CKG_NONE +\ |
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368 | AT91C_SSC_START_FALL_RF +\ |
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369 | AT91C_SSC_STTOUT +\ |
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370 | ((1<<16) & AT91C_SSC_STTDLY) +\ |
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371 | ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) |
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372 | |||
373 | |||
374 | //* Configuration to set in the SSC Transmit Frame Mode Register |
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375 | //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits |
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376 | //* nb_slot_by_frame : number of channels |
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377 | #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ |
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378 | (nb_bit_by_slot-1) +\ |
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379 | AT91C_SSC_MSBF +\ |
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380 | (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ |
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381 | (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ |
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382 | AT91C_SSC_FSOS_NEGATIVE) |
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383 | |||
384 | |||
385 | //*---------------------------------------------------------------------------- |
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386 | //* \fn AT91F_SSC_SetBaudrate |
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387 | //* \brief Set the baudrate according to the CPU clock |
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388 | //*---------------------------------------------------------------------------- |
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389 | static inline void AT91F_SSC_SetBaudrate ( |
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390 | AT91PS_SSC pSSC, // \arg pointer to a SSC controller |
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391 | unsigned int mainClock, // \arg peripheral clock |
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392 | unsigned int speed) // \arg SSC baudrate |
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393 | { |
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394 | unsigned int baud_value; |
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395 | //* Define the baud rate divisor register |
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396 | if (speed == 0) |
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397 | baud_value = 0; |
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398 | else |
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399 | { |
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400 | baud_value = (unsigned int) (mainClock * 10)/(2*speed); |
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401 | if ((baud_value % 10) >= 5) |
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402 | baud_value = (baud_value / 10) + 1; |
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403 | else |
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404 | baud_value /= 10; |
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405 | } |
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406 | |||
407 | pSSC->SSC_CMR = baud_value; |
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408 | } |
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409 | |||
410 | //*---------------------------------------------------------------------------- |
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411 | //* \fn AT91F_SSC_Configure |
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412 | //* \brief Configure SSC |
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413 | //*---------------------------------------------------------------------------- |
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414 | static inline void AT91F_SSC_Configure ( |
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415 | AT91PS_SSC pSSC, // \arg pointer to a SSC controller |
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416 | unsigned int syst_clock, // \arg System Clock Frequency |
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417 | unsigned int baud_rate, // \arg Expected Baud Rate Frequency |
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418 | unsigned int clock_rx, // \arg Receiver Clock Parameters |
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419 | unsigned int mode_rx, // \arg mode Register to be programmed |
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420 | unsigned int clock_tx, // \arg Transmitter Clock Parameters |
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421 | unsigned int mode_tx) // \arg mode Register to be programmed |
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422 | { |
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423 | //* Disable interrupts |
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424 | pSSC->SSC_IDR = (unsigned int) -1; |
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425 | |||
426 | //* Reset receiver and transmitter |
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427 | pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; |
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428 | |||
429 | //* Define the Clock Mode Register |
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430 | AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); |
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431 | |||
432 | //* Write the Receive Clock Mode Register |
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433 | pSSC->SSC_RCMR = clock_rx; |
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434 | |||
435 | //* Write the Transmit Clock Mode Register |
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436 | pSSC->SSC_TCMR = clock_tx; |
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437 | |||
438 | //* Write the Receive Frame Mode Register |
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439 | pSSC->SSC_RFMR = mode_rx; |
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440 | |||
441 | //* Write the Transmit Frame Mode Register |
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442 | pSSC->SSC_TFMR = mode_tx; |
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443 | |||
444 | //* Clear Transmit and Receive Counters |
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445 | AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); |
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446 | |||
447 | |||
448 | } |
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449 | |||
450 | //*---------------------------------------------------------------------------- |
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451 | //* \fn AT91F_SSC_EnableRx |
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452 | //* \brief Enable receiving datas |
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453 | //*---------------------------------------------------------------------------- |
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454 | static inline void AT91F_SSC_EnableRx ( |
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455 | AT91PS_SSC pSSC) // \arg pointer to a SSC controller |
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456 | { |
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457 | //* Enable receiver |
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458 | pSSC->SSC_CR = AT91C_SSC_RXEN; |
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459 | } |
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460 | |||
461 | //*---------------------------------------------------------------------------- |
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462 | //* \fn AT91F_SSC_DisableRx |
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463 | //* \brief Disable receiving datas |
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464 | //*---------------------------------------------------------------------------- |
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465 | static inline void AT91F_SSC_DisableRx ( |
||
466 | AT91PS_SSC pSSC) // \arg pointer to a SSC controller |
||
467 | { |
||
468 | //* Disable receiver |
||
469 | pSSC->SSC_CR = AT91C_SSC_RXDIS; |
||
470 | } |
||
471 | |||
472 | //*---------------------------------------------------------------------------- |
||
473 | //* \fn AT91F_SSC_EnableTx |
||
474 | //* \brief Enable sending datas |
||
475 | //*---------------------------------------------------------------------------- |
||
476 | static inline void AT91F_SSC_EnableTx ( |
||
477 | AT91PS_SSC pSSC) // \arg pointer to a SSC controller |
||
478 | { |
||
479 | //* Enable transmitter |
||
480 | pSSC->SSC_CR = AT91C_SSC_TXEN; |
||
481 | } |
||
482 | |||
483 | //*---------------------------------------------------------------------------- |
||
484 | //* \fn AT91F_SSC_DisableTx |
||
485 | //* \brief Disable sending datas |
||
486 | //*---------------------------------------------------------------------------- |
||
487 | static inline void AT91F_SSC_DisableTx ( |
||
488 | AT91PS_SSC pSSC) // \arg pointer to a SSC controller |
||
489 | { |
||
490 | //* Disable transmitter |
||
491 | pSSC->SSC_CR = AT91C_SSC_TXDIS; |
||
492 | } |
||
493 | |||
494 | //*---------------------------------------------------------------------------- |
||
495 | //* \fn AT91F_SSC_EnableIt |
||
496 | //* \brief Enable SSC IT |
||
497 | //*---------------------------------------------------------------------------- |
||
498 | static inline void AT91F_SSC_EnableIt ( |
||
499 | AT91PS_SSC pSSC, // \arg pointer to a SSC controller |
||
500 | unsigned int flag) // \arg IT to be enabled |
||
501 | { |
||
502 | //* Write to the IER register |
||
503 | pSSC->SSC_IER = flag; |
||
504 | } |
||
505 | |||
506 | //*---------------------------------------------------------------------------- |
||
507 | //* \fn AT91F_SSC_DisableIt |
||
508 | //* \brief Disable SSC IT |
||
509 | //*---------------------------------------------------------------------------- |
||
510 | static inline void AT91F_SSC_DisableIt ( |
||
511 | AT91PS_SSC pSSC, // \arg pointer to a SSC controller |
||
512 | unsigned int flag) // \arg IT to be disabled |
||
513 | { |
||
514 | //* Write to the IDR register |
||
515 | pSSC->SSC_IDR = flag; |
||
516 | } |
||
517 | |||
518 | //*---------------------------------------------------------------------------- |
||
519 | //* \fn AT91F_SSC_ReceiveFrame |
||
520 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy |
||
521 | //*---------------------------------------------------------------------------- |
||
522 | static inline unsigned int AT91F_SSC_ReceiveFrame ( |
||
523 | AT91PS_SSC pSSC, |
||
524 | char *pBuffer, |
||
525 | unsigned int szBuffer, |
||
526 | char *pNextBuffer, |
||
527 | unsigned int szNextBuffer ) |
||
528 | { |
||
529 | return AT91F_PDC_ReceiveFrame( |
||
530 | (AT91PS_PDC) &(pSSC->SSC_RPR), |
||
531 | pBuffer, |
||
532 | szBuffer, |
||
533 | pNextBuffer, |
||
534 | szNextBuffer); |
||
535 | } |
||
536 | |||
537 | //*---------------------------------------------------------------------------- |
||
538 | //* \fn AT91F_SSC_SendFrame |
||
539 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy |
||
540 | //*---------------------------------------------------------------------------- |
||
541 | static inline unsigned int AT91F_SSC_SendFrame( |
||
542 | AT91PS_SSC pSSC, |
||
543 | char *pBuffer, |
||
544 | unsigned int szBuffer, |
||
545 | char *pNextBuffer, |
||
546 | unsigned int szNextBuffer ) |
||
547 | { |
||
548 | return AT91F_PDC_SendFrame( |
||
549 | (AT91PS_PDC) &(pSSC->SSC_RPR), |
||
550 | pBuffer, |
||
551 | szBuffer, |
||
552 | pNextBuffer, |
||
553 | szNextBuffer); |
||
554 | } |
||
555 | |||
556 | //*---------------------------------------------------------------------------- |
||
557 | //* \fn AT91F_SSC_GetInterruptMaskStatus |
||
558 | //* \brief Return SSC Interrupt Mask Status |
||
559 | //*---------------------------------------------------------------------------- |
||
560 | static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status |
||
561 | AT91PS_SSC pSsc) // \arg pointer to a SSC controller |
||
562 | { |
||
563 | return pSsc->SSC_IMR; |
||
564 | } |
||
565 | |||
566 | //*---------------------------------------------------------------------------- |
||
567 | //* \fn AT91F_SSC_IsInterruptMasked |
||
568 | //* \brief Test if SSC Interrupt is Masked |
||
569 | //*---------------------------------------------------------------------------- |
||
570 | static inline int AT91F_SSC_IsInterruptMasked( |
||
571 | AT91PS_SSC pSsc, // \arg pointer to a SSC controller |
||
572 | unsigned int flag) // \arg flag to be tested |
||
573 | { |
||
574 | return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); |
||
575 | } |
||
576 | |||
577 | /* ***************************************************************************** |
||
578 | SOFTWARE API FOR SPI |
||
579 | ***************************************************************************** */ |
||
580 | //*---------------------------------------------------------------------------- |
||
581 | //* \fn AT91F_SPI_Open |
||
582 | //* \brief Open a SPI Port |
||
583 | //*---------------------------------------------------------------------------- |
||
584 | static inline unsigned int AT91F_SPI_Open ( |
||
585 | const unsigned int null) // \arg |
||
586 | { |
||
587 | /* NOT DEFINED AT THIS MOMENT */ |
||
588 | return ( 0 ); |
||
589 | } |
||
590 | |||
591 | //*---------------------------------------------------------------------------- |
||
592 | //* \fn AT91F_SPI_CfgCs |
||
593 | //* \brief Configure SPI chip select register |
||
594 | //*---------------------------------------------------------------------------- |
||
595 | static inline void AT91F_SPI_CfgCs ( |
||
596 | int cs, // SPI cs number (0 to 3) |
||
597 | int val) // chip select register |
||
598 | { |
||
599 | //* Write to the CSR register |
||
600 | *(AT91C_SPI_CSR + cs) = val; |
||
601 | } |
||
602 | |||
603 | //*---------------------------------------------------------------------------- |
||
604 | //* \fn AT91F_SPI_EnableIt |
||
605 | //* \brief Enable SPI interrupt |
||
606 | //*---------------------------------------------------------------------------- |
||
607 | static inline void AT91F_SPI_EnableIt ( |
||
608 | AT91PS_SPI pSPI, // pointer to a SPI controller |
||
609 | unsigned int flag) // IT to be enabled |
||
610 | { |
||
611 | //* Write to the IER register |
||
612 | pSPI->SPI_IER = flag; |
||
613 | } |
||
614 | |||
615 | //*---------------------------------------------------------------------------- |
||
616 | //* \fn AT91F_SPI_DisableIt |
||
617 | //* \brief Disable SPI interrupt |
||
618 | //*---------------------------------------------------------------------------- |
||
619 | static inline void AT91F_SPI_DisableIt ( |
||
620 | AT91PS_SPI pSPI, // pointer to a SPI controller |
||
621 | unsigned int flag) // IT to be disabled |
||
622 | { |
||
623 | //* Write to the IDR register |
||
624 | pSPI->SPI_IDR = flag; |
||
625 | } |
||
626 | |||
627 | //*---------------------------------------------------------------------------- |
||
628 | //* \fn AT91F_SPI_Reset |
||
629 | //* \brief Reset the SPI controller |
||
630 | //*---------------------------------------------------------------------------- |
||
631 | static inline void AT91F_SPI_Reset ( |
||
632 | AT91PS_SPI pSPI // pointer to a SPI controller |
||
633 | ) |
||
634 | { |
||
635 | //* Write to the CR register |
||
636 | pSPI->SPI_CR = AT91C_SPI_SWRST; |
||
637 | } |
||
638 | |||
639 | //*---------------------------------------------------------------------------- |
||
640 | //* \fn AT91F_SPI_Enable |
||
641 | //* \brief Enable the SPI controller |
||
642 | //*---------------------------------------------------------------------------- |
||
643 | static inline void AT91F_SPI_Enable ( |
||
644 | AT91PS_SPI pSPI // pointer to a SPI controller |
||
645 | ) |
||
646 | { |
||
647 | //* Write to the CR register |
||
648 | pSPI->SPI_CR = AT91C_SPI_SPIEN; |
||
649 | } |
||
650 | |||
651 | //*---------------------------------------------------------------------------- |
||
652 | //* \fn AT91F_SPI_Disable |
||
653 | //* \brief Disable the SPI controller |
||
654 | //*---------------------------------------------------------------------------- |
||
655 | static inline void AT91F_SPI_Disable ( |
||
656 | AT91PS_SPI pSPI // pointer to a SPI controller |
||
657 | ) |
||
658 | { |
||
659 | //* Write to the CR register |
||
660 | pSPI->SPI_CR = AT91C_SPI_SPIDIS; |
||
661 | } |
||
662 | |||
663 | //*---------------------------------------------------------------------------- |
||
664 | //* \fn AT91F_SPI_CfgMode |
||
665 | //* \brief Enable the SPI controller |
||
666 | //*---------------------------------------------------------------------------- |
||
667 | static inline void AT91F_SPI_CfgMode ( |
||
668 | AT91PS_SPI pSPI, // pointer to a SPI controller |
||
669 | int mode) // mode register |
||
670 | { |
||
671 | //* Write to the MR register |
||
672 | pSPI->SPI_MR = mode; |
||
673 | } |
||
674 | |||
675 | //*---------------------------------------------------------------------------- |
||
676 | //* \fn AT91F_SPI_CfgPCS |
||
677 | //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected |
||
678 | //*---------------------------------------------------------------------------- |
||
679 | static inline void AT91F_SPI_CfgPCS ( |
||
680 | AT91PS_SPI pSPI, // pointer to a SPI controller |
||
681 | char PCS_Device) // PCS of the Device |
||
682 | { |
||
683 | //* Write to the MR register |
||
684 | pSPI->SPI_MR &= 0xFFF0FFFF; |
||
685 | pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); |
||
686 | } |
||
687 | |||
688 | //*---------------------------------------------------------------------------- |
||
689 | //* \fn AT91F_SPI_ReceiveFrame |
||
690 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy |
||
691 | //*---------------------------------------------------------------------------- |
||
692 | static inline unsigned int AT91F_SPI_ReceiveFrame ( |
||
693 | AT91PS_SPI pSPI, |
||
694 | char *pBuffer, |
||
695 | unsigned int szBuffer, |
||
696 | char *pNextBuffer, |
||
697 | unsigned int szNextBuffer ) |
||
698 | { |
||
699 | return AT91F_PDC_ReceiveFrame( |
||
700 | (AT91PS_PDC) &(pSPI->SPI_RPR), |
||
701 | pBuffer, |
||
702 | szBuffer, |
||
703 | pNextBuffer, |
||
704 | szNextBuffer); |
||
705 | } |
||
706 | |||
707 | //*---------------------------------------------------------------------------- |
||
708 | //* \fn AT91F_SPI_SendFrame |
||
709 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy |
||
710 | //*---------------------------------------------------------------------------- |
||
711 | static inline unsigned int AT91F_SPI_SendFrame( |
||
712 | AT91PS_SPI pSPI, |
||
713 | char *pBuffer, |
||
714 | unsigned int szBuffer, |
||
715 | char *pNextBuffer, |
||
716 | unsigned int szNextBuffer ) |
||
717 | { |
||
718 | return AT91F_PDC_SendFrame( |
||
719 | (AT91PS_PDC) &(pSPI->SPI_RPR), |
||
720 | pBuffer, |
||
721 | szBuffer, |
||
722 | pNextBuffer, |
||
723 | szNextBuffer); |
||
724 | } |
||
725 | |||
726 | //*---------------------------------------------------------------------------- |
||
727 | //* \fn AT91F_SPI_Close |
||
728 | //* \brief Close SPI: disable IT disable transfert, close PDC |
||
729 | //*---------------------------------------------------------------------------- |
||
730 | static inline void AT91F_SPI_Close ( |
||
731 | AT91PS_SPI pSPI) // \arg pointer to a SPI controller |
||
732 | { |
||
733 | //* Reset all the Chip Select register |
||
734 | pSPI->SPI_CSR[0] = 0 ; |
||
735 | pSPI->SPI_CSR[1] = 0 ; |
||
736 | pSPI->SPI_CSR[2] = 0 ; |
||
737 | pSPI->SPI_CSR[3] = 0 ; |
||
738 | |||
739 | //* Reset the SPI mode |
||
740 | pSPI->SPI_MR = 0 ; |
||
741 | |||
742 | //* Disable all interrupts |
||
743 | pSPI->SPI_IDR = 0xFFFFFFFF ; |
||
744 | |||
745 | //* Abort the Peripheral Data Transfers |
||
746 | AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); |
||
747 | |||
748 | //* Disable receiver and transmitter and stop any activity immediately |
||
749 | pSPI->SPI_CR = AT91C_SPI_SPIDIS; |
||
750 | } |
||
751 | |||
752 | //*---------------------------------------------------------------------------- |
||
753 | //* \fn AT91F_SPI_PutChar |
||
754 | //* \brief Send a character,does not check if ready to send |
||
755 | //*---------------------------------------------------------------------------- |
||
756 | static inline void AT91F_SPI_PutChar ( |
||
757 | AT91PS_SPI pSPI, |
||
758 | unsigned int character, |
||
759 | unsigned int cs_number ) |
||
760 | { |
||
761 | unsigned int value_for_cs; |
||
762 | value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number |
||
763 | pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); |
||
764 | } |
||
765 | |||
766 | //*---------------------------------------------------------------------------- |
||
767 | //* \fn AT91F_SPI_GetChar |
||
768 | //* \brief Receive a character,does not check if a character is available |
||
769 | //*---------------------------------------------------------------------------- |
||
770 | static inline int AT91F_SPI_GetChar ( |
||
771 | const AT91PS_SPI pSPI) |
||
772 | { |
||
773 | return((pSPI->SPI_RDR) & 0xFFFF); |
||
774 | } |
||
775 | |||
776 | //*---------------------------------------------------------------------------- |
||
777 | //* \fn AT91F_SPI_GetInterruptMaskStatus |
||
778 | //* \brief Return SPI Interrupt Mask Status |
||
779 | //*---------------------------------------------------------------------------- |
||
780 | static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status |
||
781 | AT91PS_SPI pSpi) // \arg pointer to a SPI controller |
||
782 | { |
||
783 | return pSpi->SPI_IMR; |
||
784 | } |
||
785 | |||
786 | //*---------------------------------------------------------------------------- |
||
787 | //* \fn AT91F_SPI_IsInterruptMasked |
||
788 | //* \brief Test if SPI Interrupt is Masked |
||
789 | //*---------------------------------------------------------------------------- |
||
790 | static inline int AT91F_SPI_IsInterruptMasked( |
||
791 | AT91PS_SPI pSpi, // \arg pointer to a SPI controller |
||
792 | unsigned int flag) // \arg flag to be tested |
||
793 | { |
||
794 | return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); |
||
795 | } |
||
796 | |||
797 | /* ***************************************************************************** |
||
798 | SOFTWARE API FOR TC |
||
799 | ***************************************************************************** */ |
||
800 | //*---------------------------------------------------------------------------- |
||
801 | //* \fn AT91F_TC_InterruptEnable |
||
802 | //* \brief Enable TC Interrupt |
||
803 | //*---------------------------------------------------------------------------- |
||
804 | static inline void AT91F_TC_InterruptEnable( |
||
805 | AT91PS_TC pTc, // \arg pointer to a TC controller |
||
806 | unsigned int flag) // \arg TC interrupt to be enabled |
||
807 | { |
||
808 | pTc->TC_IER = flag; |
||
809 | } |
||
810 | |||
811 | //*---------------------------------------------------------------------------- |
||
812 | //* \fn AT91F_TC_InterruptDisable |
||
813 | //* \brief Disable TC Interrupt |
||
814 | //*---------------------------------------------------------------------------- |
||
815 | static inline void AT91F_TC_InterruptDisable( |
||
816 | AT91PS_TC pTc, // \arg pointer to a TC controller |
||
817 | unsigned int flag) // \arg TC interrupt to be disabled |
||
818 | { |
||
819 | pTc->TC_IDR = flag; |
||
820 | } |
||
821 | |||
822 | //*---------------------------------------------------------------------------- |
||
823 | //* \fn AT91F_TC_GetInterruptMaskStatus |
||
824 | //* \brief Return TC Interrupt Mask Status |
||
825 | //*---------------------------------------------------------------------------- |
||
826 | static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status |
||
827 | AT91PS_TC pTc) // \arg pointer to a TC controller |
||
828 | { |
||
829 | return pTc->TC_IMR; |
||
830 | } |
||
831 | |||
832 | //*---------------------------------------------------------------------------- |
||
833 | //* \fn AT91F_TC_IsInterruptMasked |
||
834 | //* \brief Test if TC Interrupt is Masked |
||
835 | //*---------------------------------------------------------------------------- |
||
836 | static inline int AT91F_TC_IsInterruptMasked( |
||
837 | AT91PS_TC pTc, // \arg pointer to a TC controller |
||
838 | unsigned int flag) // \arg flag to be tested |
||
839 | { |
||
840 | return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); |
||
841 | } |
||
842 | |||
843 | /* ***************************************************************************** |
||
844 | SOFTWARE API FOR PMC |
||
845 | ***************************************************************************** */ |
||
846 | //*---------------------------------------------------------------------------- |
||
847 | //* \fn AT91F_CKGR_GetMainClock |
||
848 | //* \brief Return Main clock in Hz |
||
849 | //*---------------------------------------------------------------------------- |
||
850 | static inline unsigned int AT91F_CKGR_GetMainClock ( |
||
851 | AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller |
||
852 | unsigned int slowClock) // \arg slowClock in Hz |
||
853 | { |
||
854 | return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; |
||
855 | } |
||
856 | |||
857 | //*---------------------------------------------------------------------------- |
||
858 | //* \fn AT91F_PMC_GetProcessorClock |
||
859 | //* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200) |
||
860 | //*---------------------------------------------------------------------------- |
||
861 | static inline unsigned int AT91F_PMC_GetProcessorClock ( |
||
862 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
863 | AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller |
||
864 | unsigned int slowClock) // \arg slowClock in Hz |
||
865 | { |
||
866 | unsigned int reg = pPMC->PMC_MCKR; |
||
867 | unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); |
||
868 | unsigned int pllDivider, pllMultiplier; |
||
869 | |||
870 | switch (reg & AT91C_PMC_CSS) { |
||
871 | case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected |
||
872 | return slowClock / prescaler; |
||
873 | case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected |
||
874 | return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; |
||
875 | case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected |
||
876 | reg = pCKGR->CKGR_PLLAR; |
||
877 | pllDivider = (reg & AT91C_CKGR_DIVA); |
||
878 | pllMultiplier = ((reg & AT91C_CKGR_MULA) >> 16) + 1; |
||
879 | if (reg & AT91C_CKGR_SRCA) // Source is Main clock |
||
880 | return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; |
||
881 | else // Source is Slow clock |
||
882 | return slowClock / pllDivider * pllMultiplier / prescaler; |
||
883 | case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected |
||
884 | reg = pCKGR->CKGR_PLLBR; |
||
885 | pllDivider = (reg & AT91C_CKGR_DIVB); |
||
886 | pllMultiplier = ((reg & AT91C_CKGR_MULB) >> 16) + 1; |
||
887 | return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; |
||
888 | } |
||
889 | return 0; |
||
890 | } |
||
891 | |||
892 | //*---------------------------------------------------------------------------- |
||
893 | //* \fn AT91F_PMC_GetMasterClock |
||
894 | //* \brief Return master clock in Hz (just for AT91RM9200) |
||
895 | //*---------------------------------------------------------------------------- |
||
896 | static inline unsigned int AT91F_PMC_GetMasterClock ( |
||
897 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
898 | AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller |
||
899 | unsigned int slowClock) // \arg slowClock in Hz |
||
900 | { |
||
901 | return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) / |
||
902 | (((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1); |
||
903 | } |
||
904 | |||
905 | //*---------------------------------------------------------------------------- |
||
906 | //* \fn AT91F_PMC_EnablePeriphClock |
||
907 | //* \brief Enable peripheral clock |
||
908 | //*---------------------------------------------------------------------------- |
||
909 | static inline void AT91F_PMC_EnablePeriphClock ( |
||
910 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
911 | unsigned int periphIds) // \arg IDs of peripherals to enable |
||
912 | { |
||
913 | pPMC->PMC_PCER = periphIds; |
||
914 | } |
||
915 | |||
916 | //*---------------------------------------------------------------------------- |
||
917 | //* \fn AT91F_PMC_DisablePeriphClock |
||
918 | //* \brief Enable peripheral clock |
||
919 | //*---------------------------------------------------------------------------- |
||
920 | static inline void AT91F_PMC_DisablePeriphClock ( |
||
921 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
922 | unsigned int periphIds) // \arg IDs of peripherals to enable |
||
923 | { |
||
924 | pPMC->PMC_PCDR = periphIds; |
||
925 | } |
||
926 | |||
927 | //*---------------------------------------------------------------------------- |
||
928 | //* \fn AT91F_PMC_EnablePCK |
||
929 | //* \brief Enable peripheral clock |
||
930 | //*---------------------------------------------------------------------------- |
||
931 | static inline void AT91F_PMC_EnablePCK ( |
||
932 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
933 | unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 |
||
934 | unsigned int ccs, // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK |
||
935 | unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64 |
||
936 | { |
||
937 | pPMC->PMC_PCKR[pck] = ccs | pres; |
||
938 | pPMC->PMC_SCER = (1 << pck) << 8; |
||
939 | } |
||
940 | |||
941 | //*---------------------------------------------------------------------------- |
||
942 | //* \fn AT91F_PMC_DisablePCK |
||
943 | //* \brief Enable peripheral clock |
||
944 | //*---------------------------------------------------------------------------- |
||
945 | static inline void AT91F_PMC_DisablePCK ( |
||
946 | AT91PS_PMC pPMC, // \arg pointer to PMC controller |
||
947 | unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 |
||
948 | { |
||
949 | pPMC->PMC_SCDR = (1 << pck) << 8; |
||
950 | } |
||
951 | |||
952 | /* ***************************************************************************** |
||
953 | SOFTWARE API FOR PIO |
||
954 | ***************************************************************************** */ |
||
955 | //*---------------------------------------------------------------------------- |
||
956 | //* \fn AT91F_PIO_CfgPeriph |
||
957 | //* \brief Enable pins to be drived by peripheral |
||
958 | //*---------------------------------------------------------------------------- |
||
959 | static inline void AT91F_PIO_CfgPeriph( |
||
960 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
961 | unsigned int periphAEnable, // \arg PERIPH A to enable |
||
962 | unsigned int periphBEnable) // \arg PERIPH B to enable |
||
963 | |||
964 | { |
||
965 | pPio->PIO_ASR = periphAEnable; |
||
966 | pPio->PIO_BSR = periphBEnable; |
||
967 | pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode |
||
968 | } |
||
969 | |||
970 | //*---------------------------------------------------------------------------- |
||
971 | //* \fn AT91F_PIO_CfgOutput |
||
972 | //* \brief Enable PIO in output mode |
||
973 | //*---------------------------------------------------------------------------- |
||
974 | static inline void AT91F_PIO_CfgOutput( |
||
975 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
976 | unsigned int pioEnable) // \arg PIO to be enabled |
||
977 | { |
||
978 | pPio->PIO_PER = pioEnable; // Set in PIO mode |
||
979 | pPio->PIO_OER = pioEnable; // Configure in Output |
||
980 | } |
||
981 | |||
982 | //*---------------------------------------------------------------------------- |
||
983 | //* \fn AT91F_PIO_CfgInput |
||
984 | //* \brief Enable PIO in input mode |
||
985 | //*---------------------------------------------------------------------------- |
||
986 | static inline void AT91F_PIO_CfgInput( |
||
987 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
988 | unsigned int inputEnable) // \arg PIO to be enabled |
||
989 | { |
||
990 | // Disable output |
||
991 | pPio->PIO_ODR = inputEnable; |
||
992 | pPio->PIO_PER = inputEnable; |
||
993 | } |
||
994 | |||
995 | //*---------------------------------------------------------------------------- |
||
996 | //* \fn AT91F_PIO_CfgOpendrain |
||
997 | //* \brief Configure PIO in open drain |
||
998 | //*---------------------------------------------------------------------------- |
||
999 | static inline void AT91F_PIO_CfgOpendrain( |
||
1000 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1001 | unsigned int multiDrvEnable) // \arg pio to be configured in open drain |
||
1002 | { |
||
1003 | // Configure the multi-drive option |
||
1004 | pPio->PIO_MDDR = ~multiDrvEnable; |
||
1005 | pPio->PIO_MDER = multiDrvEnable; |
||
1006 | } |
||
1007 | |||
1008 | //*---------------------------------------------------------------------------- |
||
1009 | //* \fn AT91F_PIO_CfgPullup |
||
1010 | //* \brief Enable pullup on PIO |
||
1011 | //*---------------------------------------------------------------------------- |
||
1012 | static inline void AT91F_PIO_CfgPullup( |
||
1013 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1014 | unsigned int pullupEnable) // \arg enable pullup on PIO |
||
1015 | { |
||
1016 | // Connect or not Pullup |
||
1017 | pPio->PIO_PPUDR = ~pullupEnable; |
||
1018 | pPio->PIO_PPUER = pullupEnable; |
||
1019 | } |
||
1020 | |||
1021 | //*---------------------------------------------------------------------------- |
||
1022 | //* \fn AT91F_PIO_CfgDirectDrive |
||
1023 | //* \brief Enable direct drive on PIO |
||
1024 | //*---------------------------------------------------------------------------- |
||
1025 | static inline void AT91F_PIO_CfgDirectDrive( |
||
1026 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1027 | unsigned int directDrive) // \arg PIO to be configured with direct drive |
||
1028 | |||
1029 | { |
||
1030 | // Configure the Direct Drive |
||
1031 | pPio->PIO_OWDR = ~directDrive; |
||
1032 | pPio->PIO_OWER = directDrive; |
||
1033 | } |
||
1034 | |||
1035 | //*---------------------------------------------------------------------------- |
||
1036 | //* \fn AT91F_PIO_CfgInputFilter |
||
1037 | //* \brief Enable input filter on input PIO |
||
1038 | //*---------------------------------------------------------------------------- |
||
1039 | static inline void AT91F_PIO_CfgInputFilter( |
||
1040 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1041 | unsigned int inputFilter) // \arg PIO to be configured with input filter |
||
1042 | |||
1043 | { |
||
1044 | // Configure the Direct Drive |
||
1045 | pPio->PIO_IFDR = ~inputFilter; |
||
1046 | pPio->PIO_IFER = inputFilter; |
||
1047 | } |
||
1048 | |||
1049 | //*---------------------------------------------------------------------------- |
||
1050 | //* \fn AT91F_PIO_GetInput |
||
1051 | //* \brief Return PIO input value |
||
1052 | //*---------------------------------------------------------------------------- |
||
1053 | static inline unsigned int AT91F_PIO_GetInput( // \return PIO input |
||
1054 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1055 | { |
||
1056 | return pPio->PIO_PDSR; |
||
1057 | } |
||
1058 | |||
1059 | //*---------------------------------------------------------------------------- |
||
1060 | //* \fn AT91F_PIO_IsInputSet |
||
1061 | //* \brief Test if PIO is input flag is active |
||
1062 | //*---------------------------------------------------------------------------- |
||
1063 | static inline int AT91F_PIO_IsInputSet( |
||
1064 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1065 | unsigned int flag) // \arg flag to be tested |
||
1066 | { |
||
1067 | return (AT91F_PIO_GetInput(pPio) & flag); |
||
1068 | } |
||
1069 | |||
1070 | |||
1071 | //*---------------------------------------------------------------------------- |
||
1072 | //* \fn AT91F_PIO_SetOutput |
||
1073 | //* \brief Set to 1 output PIO |
||
1074 | //*---------------------------------------------------------------------------- |
||
1075 | static inline void AT91F_PIO_SetOutput( |
||
1076 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1077 | unsigned int flag) // \arg output to be set |
||
1078 | { |
||
1079 | pPio->PIO_SODR = flag; |
||
1080 | } |
||
1081 | |||
1082 | //*---------------------------------------------------------------------------- |
||
1083 | //* \fn AT91F_PIO_ClearOutput |
||
1084 | //* \brief Set to 0 output PIO |
||
1085 | //*---------------------------------------------------------------------------- |
||
1086 | static inline void AT91F_PIO_ClearOutput( |
||
1087 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1088 | unsigned int flag) // \arg output to be cleared |
||
1089 | { |
||
1090 | pPio->PIO_CODR = flag; |
||
1091 | } |
||
1092 | |||
1093 | //*---------------------------------------------------------------------------- |
||
1094 | //* \fn AT91F_PIO_ForceOutput |
||
1095 | //* \brief Force output when Direct drive option is enabled |
||
1096 | //*---------------------------------------------------------------------------- |
||
1097 | static inline void AT91F_PIO_ForceOutput( |
||
1098 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1099 | unsigned int flag) // \arg output to be forced |
||
1100 | { |
||
1101 | pPio->PIO_ODSR = flag; |
||
1102 | } |
||
1103 | |||
1104 | //*---------------------------------------------------------------------------- |
||
1105 | //* \fn AT91F_PIO_Enable |
||
1106 | //* \brief Enable PIO |
||
1107 | //*---------------------------------------------------------------------------- |
||
1108 | static inline void AT91F_PIO_Enable( |
||
1109 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1110 | unsigned int flag) // \arg pio to be enabled |
||
1111 | { |
||
1112 | pPio->PIO_PER = flag; |
||
1113 | } |
||
1114 | |||
1115 | //*---------------------------------------------------------------------------- |
||
1116 | //* \fn AT91F_PIO_Disable |
||
1117 | //* \brief Disable PIO |
||
1118 | //*---------------------------------------------------------------------------- |
||
1119 | static inline void AT91F_PIO_Disable( |
||
1120 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1121 | unsigned int flag) // \arg pio to be disabled |
||
1122 | { |
||
1123 | pPio->PIO_PDR = flag; |
||
1124 | } |
||
1125 | |||
1126 | //*---------------------------------------------------------------------------- |
||
1127 | //* \fn AT91F_PIO_GetStatus |
||
1128 | //* \brief Return PIO Status |
||
1129 | //*---------------------------------------------------------------------------- |
||
1130 | static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status |
||
1131 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1132 | { |
||
1133 | return pPio->PIO_PSR; |
||
1134 | } |
||
1135 | |||
1136 | //*---------------------------------------------------------------------------- |
||
1137 | //* \fn AT91F_PIO_IsSet |
||
1138 | //* \brief Test if PIO is Set |
||
1139 | //*---------------------------------------------------------------------------- |
||
1140 | static inline int AT91F_PIO_IsSet( |
||
1141 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1142 | unsigned int flag) // \arg flag to be tested |
||
1143 | { |
||
1144 | return (AT91F_PIO_GetStatus(pPio) & flag); |
||
1145 | } |
||
1146 | |||
1147 | //*---------------------------------------------------------------------------- |
||
1148 | //* \fn AT91F_PIO_OutputEnable |
||
1149 | //* \brief Output Enable PIO |
||
1150 | //*---------------------------------------------------------------------------- |
||
1151 | static inline void AT91F_PIO_OutputEnable( |
||
1152 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1153 | unsigned int flag) // \arg pio output to be enabled |
||
1154 | { |
||
1155 | pPio->PIO_OER = flag; |
||
1156 | } |
||
1157 | |||
1158 | //*---------------------------------------------------------------------------- |
||
1159 | //* \fn AT91F_PIO_OutputDisable |
||
1160 | //* \brief Output Enable PIO |
||
1161 | //*---------------------------------------------------------------------------- |
||
1162 | static inline void AT91F_PIO_OutputDisable( |
||
1163 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1164 | unsigned int flag) // \arg pio output to be disabled |
||
1165 | { |
||
1166 | pPio->PIO_ODR = flag; |
||
1167 | } |
||
1168 | |||
1169 | //*---------------------------------------------------------------------------- |
||
1170 | //* \fn AT91F_PIO_GetOutputStatus |
||
1171 | //* \brief Return PIO Output Status |
||
1172 | //*---------------------------------------------------------------------------- |
||
1173 | static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status |
||
1174 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1175 | { |
||
1176 | return pPio->PIO_OSR; |
||
1177 | } |
||
1178 | |||
1179 | //*---------------------------------------------------------------------------- |
||
1180 | //* \fn AT91F_PIO_IsOuputSet |
||
1181 | //* \brief Test if PIO Output is Set |
||
1182 | //*---------------------------------------------------------------------------- |
||
1183 | static inline int AT91F_PIO_IsOutputSet( |
||
1184 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1185 | unsigned int flag) // \arg flag to be tested |
||
1186 | { |
||
1187 | return (AT91F_PIO_GetOutputStatus(pPio) & flag); |
||
1188 | } |
||
1189 | |||
1190 | //*---------------------------------------------------------------------------- |
||
1191 | //* \fn AT91F_PIO_InputFilterEnable |
||
1192 | //* \brief Input Filter Enable PIO |
||
1193 | //*---------------------------------------------------------------------------- |
||
1194 | static inline void AT91F_PIO_InputFilterEnable( |
||
1195 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1196 | unsigned int flag) // \arg pio input filter to be enabled |
||
1197 | { |
||
1198 | pPio->PIO_IFER = flag; |
||
1199 | } |
||
1200 | |||
1201 | //*---------------------------------------------------------------------------- |
||
1202 | //* \fn AT91F_PIO_InputFilterDisable |
||
1203 | //* \brief Input Filter Disable PIO |
||
1204 | //*---------------------------------------------------------------------------- |
||
1205 | static inline void AT91F_PIO_InputFilterDisable( |
||
1206 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1207 | unsigned int flag) // \arg pio input filter to be disabled |
||
1208 | { |
||
1209 | pPio->PIO_IFDR = flag; |
||
1210 | } |
||
1211 | |||
1212 | //*---------------------------------------------------------------------------- |
||
1213 | //* \fn AT91F_PIO_GetInputFilterStatus |
||
1214 | //* \brief Return PIO Input Filter Status |
||
1215 | //*---------------------------------------------------------------------------- |
||
1216 | static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status |
||
1217 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1218 | { |
||
1219 | return pPio->PIO_IFSR; |
||
1220 | } |
||
1221 | |||
1222 | //*---------------------------------------------------------------------------- |
||
1223 | //* \fn AT91F_PIO_IsInputFilterSet |
||
1224 | //* \brief Test if PIO Input filter is Set |
||
1225 | //*---------------------------------------------------------------------------- |
||
1226 | static inline int AT91F_PIO_IsInputFilterSet( |
||
1227 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1228 | unsigned int flag) // \arg flag to be tested |
||
1229 | { |
||
1230 | return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); |
||
1231 | } |
||
1232 | |||
1233 | //*---------------------------------------------------------------------------- |
||
1234 | //* \fn AT91F_PIO_GetOutputDataStatus |
||
1235 | //* \brief Return PIO Output Data Status |
||
1236 | //*---------------------------------------------------------------------------- |
||
1237 | static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status |
||
1238 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1239 | { |
||
1240 | return pPio->PIO_ODSR; |
||
1241 | } |
||
1242 | |||
1243 | //*---------------------------------------------------------------------------- |
||
1244 | //* \fn AT91F_PIO_InterruptEnable |
||
1245 | //* \brief Enable PIO Interrupt |
||
1246 | //*---------------------------------------------------------------------------- |
||
1247 | static inline void AT91F_PIO_InterruptEnable( |
||
1248 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1249 | unsigned int flag) // \arg pio interrupt to be enabled |
||
1250 | { |
||
1251 | pPio->PIO_IER = flag; |
||
1252 | } |
||
1253 | |||
1254 | //*---------------------------------------------------------------------------- |
||
1255 | //* \fn AT91F_PIO_InterruptDisable |
||
1256 | //* \brief Disable PIO Interrupt |
||
1257 | //*---------------------------------------------------------------------------- |
||
1258 | static inline void AT91F_PIO_InterruptDisable( |
||
1259 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1260 | unsigned int flag) // \arg pio interrupt to be disabled |
||
1261 | { |
||
1262 | pPio->PIO_IDR = flag; |
||
1263 | } |
||
1264 | |||
1265 | //*---------------------------------------------------------------------------- |
||
1266 | //* \fn AT91F_PIO_GetInterruptMaskStatus |
||
1267 | //* \brief Return PIO Interrupt Mask Status |
||
1268 | //*---------------------------------------------------------------------------- |
||
1269 | static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status |
||
1270 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1271 | { |
||
1272 | return pPio->PIO_IMR; |
||
1273 | } |
||
1274 | |||
1275 | //*---------------------------------------------------------------------------- |
||
1276 | //* \fn AT91F_PIO_GetInterruptStatus |
||
1277 | //* \brief Return PIO Interrupt Status |
||
1278 | //*---------------------------------------------------------------------------- |
||
1279 | static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status |
||
1280 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1281 | { |
||
1282 | return pPio->PIO_ISR; |
||
1283 | } |
||
1284 | |||
1285 | //*---------------------------------------------------------------------------- |
||
1286 | //* \fn AT91F_PIO_IsInterruptMasked |
||
1287 | //* \brief Test if PIO Interrupt is Masked |
||
1288 | //*---------------------------------------------------------------------------- |
||
1289 | static inline int AT91F_PIO_IsInterruptMasked( |
||
1290 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1291 | unsigned int flag) // \arg flag to be tested |
||
1292 | { |
||
1293 | return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); |
||
1294 | } |
||
1295 | |||
1296 | //*---------------------------------------------------------------------------- |
||
1297 | //* \fn AT91F_PIO_IsInterruptSet |
||
1298 | //* \brief Test if PIO Interrupt is Set |
||
1299 | //*---------------------------------------------------------------------------- |
||
1300 | static inline int AT91F_PIO_IsInterruptSet( |
||
1301 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1302 | unsigned int flag) // \arg flag to be tested |
||
1303 | { |
||
1304 | return (AT91F_PIO_GetInterruptStatus(pPio) & flag); |
||
1305 | } |
||
1306 | |||
1307 | //*---------------------------------------------------------------------------- |
||
1308 | //* \fn AT91F_PIO_MultiDriverEnable |
||
1309 | //* \brief Multi Driver Enable PIO |
||
1310 | //*---------------------------------------------------------------------------- |
||
1311 | static inline void AT91F_PIO_MultiDriverEnable( |
||
1312 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1313 | unsigned int flag) // \arg pio to be enabled |
||
1314 | { |
||
1315 | pPio->PIO_MDER = flag; |
||
1316 | } |
||
1317 | |||
1318 | //*---------------------------------------------------------------------------- |
||
1319 | //* \fn AT91F_PIO_MultiDriverDisable |
||
1320 | //* \brief Multi Driver Disable PIO |
||
1321 | //*---------------------------------------------------------------------------- |
||
1322 | static inline void AT91F_PIO_MultiDriverDisable( |
||
1323 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1324 | unsigned int flag) // \arg pio to be disabled |
||
1325 | { |
||
1326 | pPio->PIO_MDDR = flag; |
||
1327 | } |
||
1328 | |||
1329 | //*---------------------------------------------------------------------------- |
||
1330 | //* \fn AT91F_PIO_GetMultiDriverStatus |
||
1331 | //* \brief Return PIO Multi Driver Status |
||
1332 | //*---------------------------------------------------------------------------- |
||
1333 | static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status |
||
1334 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1335 | { |
||
1336 | return pPio->PIO_MDSR; |
||
1337 | } |
||
1338 | |||
1339 | //*---------------------------------------------------------------------------- |
||
1340 | //* \fn AT91F_PIO_IsMultiDriverSet |
||
1341 | //* \brief Test if PIO MultiDriver is Set |
||
1342 | //*---------------------------------------------------------------------------- |
||
1343 | static inline int AT91F_PIO_IsMultiDriverSet( |
||
1344 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1345 | unsigned int flag) // \arg flag to be tested |
||
1346 | { |
||
1347 | return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); |
||
1348 | } |
||
1349 | |||
1350 | //*---------------------------------------------------------------------------- |
||
1351 | //* \fn AT91F_PIO_A_RegisterSelection |
||
1352 | //* \brief PIO A Register Selection |
||
1353 | //*---------------------------------------------------------------------------- |
||
1354 | static inline void AT91F_PIO_A_RegisterSelection( |
||
1355 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1356 | unsigned int flag) // \arg pio A register selection |
||
1357 | { |
||
1358 | pPio->PIO_ASR = flag; |
||
1359 | } |
||
1360 | |||
1361 | //*---------------------------------------------------------------------------- |
||
1362 | //* \fn AT91F_PIO_B_RegisterSelection |
||
1363 | //* \brief PIO B Register Selection |
||
1364 | //*---------------------------------------------------------------------------- |
||
1365 | static inline void AT91F_PIO_B_RegisterSelection( |
||
1366 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1367 | unsigned int flag) // \arg pio B register selection |
||
1368 | { |
||
1369 | pPio->PIO_BSR = flag; |
||
1370 | } |
||
1371 | |||
1372 | //*---------------------------------------------------------------------------- |
||
1373 | //* \fn AT91F_PIO_Get_AB_RegisterStatus |
||
1374 | //* \brief Return PIO Interrupt Status |
||
1375 | //*---------------------------------------------------------------------------- |
||
1376 | static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status |
||
1377 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1378 | { |
||
1379 | return pPio->PIO_ABSR; |
||
1380 | } |
||
1381 | |||
1382 | //*---------------------------------------------------------------------------- |
||
1383 | //* \fn AT91F_PIO_IsAB_RegisterSet |
||
1384 | //* \brief Test if PIO AB Register is Set |
||
1385 | //*---------------------------------------------------------------------------- |
||
1386 | static inline int AT91F_PIO_IsAB_RegisterSet( |
||
1387 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1388 | unsigned int flag) // \arg flag to be tested |
||
1389 | { |
||
1390 | return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); |
||
1391 | } |
||
1392 | |||
1393 | //*---------------------------------------------------------------------------- |
||
1394 | //* \fn AT91F_PIO_OutputWriteEnable |
||
1395 | //* \brief Output Write Enable PIO |
||
1396 | //*---------------------------------------------------------------------------- |
||
1397 | static inline void AT91F_PIO_OutputWriteEnable( |
||
1398 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1399 | unsigned int flag) // \arg pio output write to be enabled |
||
1400 | { |
||
1401 | pPio->PIO_OWER = flag; |
||
1402 | } |
||
1403 | |||
1404 | //*---------------------------------------------------------------------------- |
||
1405 | //* \fn AT91F_PIO_OutputWriteDisable |
||
1406 | //* \brief Output Write Disable PIO |
||
1407 | //*---------------------------------------------------------------------------- |
||
1408 | static inline void AT91F_PIO_OutputWriteDisable( |
||
1409 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1410 | unsigned int flag) // \arg pio output write to be disabled |
||
1411 | { |
||
1412 | pPio->PIO_OWDR = flag; |
||
1413 | } |
||
1414 | |||
1415 | //*---------------------------------------------------------------------------- |
||
1416 | //* \fn AT91F_PIO_GetOutputWriteStatus |
||
1417 | //* \brief Return PIO Output Write Status |
||
1418 | //*---------------------------------------------------------------------------- |
||
1419 | static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status |
||
1420 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1421 | { |
||
1422 | return pPio->PIO_OWSR; |
||
1423 | } |
||
1424 | |||
1425 | //*---------------------------------------------------------------------------- |
||
1426 | //* \fn AT91F_PIO_IsOutputWriteSet |
||
1427 | //* \brief Test if PIO OutputWrite is Set |
||
1428 | //*---------------------------------------------------------------------------- |
||
1429 | static inline int AT91F_PIO_IsOutputWriteSet( |
||
1430 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1431 | unsigned int flag) // \arg flag to be tested |
||
1432 | { |
||
1433 | return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); |
||
1434 | } |
||
1435 | |||
1436 | //*---------------------------------------------------------------------------- |
||
1437 | //* \fn AT91F_PIO_GetCfgPullup |
||
1438 | //* \brief Return PIO Configuration Pullup |
||
1439 | //*---------------------------------------------------------------------------- |
||
1440 | static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup |
||
1441 | AT91PS_PIO pPio) // \arg pointer to a PIO controller |
||
1442 | { |
||
1443 | return pPio->PIO_PPUSR; |
||
1444 | } |
||
1445 | |||
1446 | //*---------------------------------------------------------------------------- |
||
1447 | //* \fn AT91F_PIO_IsOutputDataStatusSet |
||
1448 | //* \brief Test if PIO Output Data Status is Set |
||
1449 | //*---------------------------------------------------------------------------- |
||
1450 | static inline int AT91F_PIO_IsOutputDataStatusSet( |
||
1451 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1452 | unsigned int flag) // \arg flag to be tested |
||
1453 | { |
||
1454 | return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); |
||
1455 | } |
||
1456 | |||
1457 | //*---------------------------------------------------------------------------- |
||
1458 | //* \fn AT91F_PIO_IsCfgPullupStatusSet |
||
1459 | //* \brief Test if PIO Configuration Pullup Status is Set |
||
1460 | //*---------------------------------------------------------------------------- |
||
1461 | static inline int AT91F_PIO_IsCfgPullupStatusSet( |
||
1462 | AT91PS_PIO pPio, // \arg pointer to a PIO controller |
||
1463 | unsigned int flag) // \arg flag to be tested |
||
1464 | { |
||
1465 | return (~AT91F_PIO_GetCfgPullup(pPio) & flag); |
||
1466 | } |
||
1467 | |||
1468 | /* ***************************************************************************** |
||
1469 | SOFTWARE API FOR TWI |
||
1470 | ***************************************************************************** */ |
||
1471 | //*---------------------------------------------------------------------------- |
||
1472 | //* \fn AT91F_TWI_EnableIt |
||
1473 | //* \brief Enable TWI IT |
||
1474 | //*---------------------------------------------------------------------------- |
||
1475 | static inline void AT91F_TWI_EnableIt ( |
||
1476 | AT91PS_TWI pTWI, // \arg pointer to a TWI controller |
||
1477 | unsigned int flag) // \arg IT to be enabled |
||
1478 | { |
||
1479 | //* Write to the IER register |
||
1480 | pTWI->TWI_IER = flag; |
||
1481 | } |
||
1482 | |||
1483 | //*---------------------------------------------------------------------------- |
||
1484 | //* \fn AT91F_TWI_DisableIt |
||
1485 | //* \brief Disable TWI IT |
||
1486 | //*---------------------------------------------------------------------------- |
||
1487 | static inline void AT91F_TWI_DisableIt ( |
||
1488 | AT91PS_TWI pTWI, // \arg pointer to a TWI controller |
||
1489 | unsigned int flag) // \arg IT to be disabled |
||
1490 | { |
||
1491 | //* Write to the IDR register |
||
1492 | pTWI->TWI_IDR = flag; |
||
1493 | } |
||
1494 | |||
1495 | //*---------------------------------------------------------------------------- |
||
1496 | //* \fn AT91F_TWI_Configure |
||
1497 | //* \brief Configure TWI in master mode |
||
1498 | //*---------------------------------------------------------------------------- |
||
1499 | static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller |
||
1500 | { |
||
1501 | //* Disable interrupts |
||
1502 | pTWI->TWI_IDR = (unsigned int) -1; |
||
1503 | |||
1504 | //* Reset peripheral |
||
1505 | pTWI->TWI_CR = AT91C_TWI_SWRST; |
||
1506 | |||
1507 | //* Set Master mode |
||
1508 | pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; |
||
1509 | |||
1510 | } |
||
1511 | |||
1512 | //*---------------------------------------------------------------------------- |
||
1513 | //* \fn AT91F_TWI_GetInterruptMaskStatus |
||
1514 | //* \brief Return TWI Interrupt Mask Status |
||
1515 | //*---------------------------------------------------------------------------- |
||
1516 | static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status |
||
1517 | AT91PS_TWI pTwi) // \arg pointer to a TWI controller |
||
1518 | { |
||
1519 | return pTwi->TWI_IMR; |
||
1520 | } |
||
1521 | |||
1522 | //*---------------------------------------------------------------------------- |
||
1523 | //* \fn AT91F_TWI_IsInterruptMasked |
||
1524 | //* \brief Test if TWI Interrupt is Masked |
||
1525 | //*---------------------------------------------------------------------------- |
||
1526 | static inline int AT91F_TWI_IsInterruptMasked( |
||
1527 | AT91PS_TWI pTwi, // \arg pointer to a TWI controller |
||
1528 | unsigned int flag) // \arg flag to be tested |
||
1529 | { |
||
1530 | return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); |
||
1531 | } |
||
1532 | |||
1533 | /* ***************************************************************************** |
||
1534 | SOFTWARE API FOR USART |
||
1535 | ***************************************************************************** */ |
||
1536 | //*---------------------------------------------------------------------------- |
||
1537 | //* \fn AT91F_US_Baudrate |
||
1538 | //* \brief Calculate the baudrate |
||
1539 | //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity |
||
1540 | #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ |
||
1541 | AT91C_US_NBSTOP_1_BIT + \ |
||
1542 | AT91C_US_PAR_NONE + \ |
||
1543 | AT91C_US_CHRL_8_BITS + \ |
||
1544 | AT91C_US_CLKS_CLOCK ) |
||
1545 | |||
1546 | //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity |
||
1547 | #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ |
||
1548 | AT91C_US_NBSTOP_1_BIT + \ |
||
1549 | AT91C_US_PAR_NONE + \ |
||
1550 | AT91C_US_CHRL_8_BITS + \ |
||
1551 | AT91C_US_CLKS_EXT ) |
||
1552 | |||
1553 | //* Standard Synchronous Mode : 8 bits , 1 stop , no parity |
||
1554 | #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ |
||
1555 | AT91C_US_USMODE_NORMAL + \ |
||
1556 | AT91C_US_NBSTOP_1_BIT + \ |
||
1557 | AT91C_US_PAR_NONE + \ |
||
1558 | AT91C_US_CHRL_8_BITS + \ |
||
1559 | AT91C_US_CLKS_CLOCK ) |
||
1560 | |||
1561 | //* SCK used Label |
||
1562 | #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) |
||
1563 | |||
1564 | //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity |
||
1565 | #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ |
||
1566 | AT91C_US_CLKS_CLOCK +\ |
||
1567 | AT91C_US_NBSTOP_1_BIT + \ |
||
1568 | AT91C_US_PAR_EVEN + \ |
||
1569 | AT91C_US_CHRL_8_BITS + \ |
||
1570 | AT91C_US_CKLO +\ |
||
1571 | AT91C_US_OVER) |
||
1572 | |||
1573 | //* Standard IRDA mode |
||
1574 | #define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ |
||
1575 | AT91C_US_NBSTOP_1_BIT + \ |
||
1576 | AT91C_US_PAR_NONE + \ |
||
1577 | AT91C_US_CHRL_8_BITS + \ |
||
1578 | AT91C_US_CLKS_CLOCK ) |
||
1579 | |||
1580 | //*---------------------------------------------------------------------------- |
||
1581 | //* \fn AT91F_US_Baudrate |
||
1582 | //* \brief Caluculate baud_value according to the main clock and the baud rate |
||
1583 | //*---------------------------------------------------------------------------- |
||
1584 | static inline unsigned int AT91F_US_Baudrate ( |
||
1585 | const unsigned int main_clock, // \arg peripheral clock |
||
1586 | const unsigned int baud_rate) // \arg UART baudrate |
||
1587 | { |
||
1588 | unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); |
||
1589 | if ((baud_value % 10) >= 5) |
||
1590 | baud_value = (baud_value / 10) + 1; |
||
1591 | else |
||
1592 | baud_value /= 10; |
||
1593 | return baud_value; |
||
1594 | } |
||
1595 | |||
1596 | //*---------------------------------------------------------------------------- |
||
1597 | //* \fn AT91F_US_SetBaudrate |
||
1598 | //* \brief Set the baudrate according to the CPU clock |
||
1599 | //*---------------------------------------------------------------------------- |
||
1600 | static inline void AT91F_US_SetBaudrate ( |
||
1601 | AT91PS_USART pUSART, // \arg pointer to a USART controller |
||
1602 | unsigned int mainClock, // \arg peripheral clock |
||
1603 | unsigned int speed) // \arg UART baudrate |
||
1604 | { |
||
1605 | //* Define the baud rate divisor register |
||
1606 | pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); |
||
1607 | } |
||
1608 | |||
1609 | //*---------------------------------------------------------------------------- |
||
1610 | //* \fn AT91F_US_SetTimeguard |
||
1611 | //* \brief Set USART timeguard |
||
1612 | //*---------------------------------------------------------------------------- |
||
1613 | static inline void AT91F_US_SetTimeguard ( |
||
1614 | AT91PS_USART pUSART, // \arg pointer to a USART controller |
||
1615 | unsigned int timeguard) // \arg timeguard value |
||
1616 | { |
||
1617 | //* Write the Timeguard Register |
||
1618 | pUSART->US_TTGR = timeguard ; |
||
1619 | } |
||
1620 | |||
1621 | //*---------------------------------------------------------------------------- |
||
1622 | //* \fn AT91F_US_EnableIt |
||
1623 | //* \brief Enable USART IT |
||
1624 | //*---------------------------------------------------------------------------- |
||
1625 | static inline void AT91F_US_EnableIt ( |
||
1626 | AT91PS_USART pUSART, // \arg pointer to a USART controller |
||
1627 | unsigned int flag) // \arg IT to be enabled |
||
1628 | { |
||
1629 | //* Write to the IER register |
||
1630 | pUSART->US_IER = flag; |
||
1631 | } |
||
1632 | |||
1633 | //*---------------------------------------------------------------------------- |
||
1634 | //* \fn AT91F_US_DisableIt |
||
1635 | //* \brief Disable USART IT |
||
1636 | //*---------------------------------------------------------------------------- |
||
1637 | static inline void AT91F_US_DisableIt ( |
||
1638 | AT91PS_USART pUSART, // \arg pointer to a USART controller |
||
1639 | unsigned int flag) // \arg IT to be disabled |
||
1640 | { |
||
1641 | //* Write to the IER register |
||
1642 | pUSART->US_IDR = flag; |
||
1643 | } |
||
1644 | |||
1645 | //*---------------------------------------------------------------------------- |
||
1646 | //* \fn AT91F_US_Configure |
||
1647 | //* \brief Configure USART |
||
1648 | //*---------------------------------------------------------------------------- |
||
1649 | static inline void AT91F_US_Configure ( |
||
1650 | AT91PS_USART pUSART, // \arg pointer to a USART controller |
||
1651 | unsigned int mainClock, // \arg peripheral clock |
||
1652 | unsigned int mode , // \arg mode Register to be programmed |
||
1653 | unsigned int baudRate , // \arg baudrate to be programmed |
||
1654 | unsigned int timeguard ) // \arg timeguard to be programmed |
||
1655 | { |
||
1656 | //* Disable interrupts |
||
1657 | pUSART->US_IDR = (unsigned int) -1; |
||
1658 | |||
1659 | //* Reset receiver and transmitter |
||
1660 | pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; |
||
1661 | |||
1662 | //* Define the baud rate divisor register |
||
1663 | AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); |
||
1664 | |||
1665 | //* Write the Timeguard Register |
||
1666 | AT91F_US_SetTimeguard(pUSART, timeguard); |
||
1667 | |||
1668 | //* Clear Transmit and Receive Counters |
||
1669 | AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); |
||
1670 | |||
1671 | //* Define the USART mode |
||
1672 | pUSART->US_MR = mode ; |
||
1673 | |||
1674 | } |
||
1675 | |||
1676 | //*---------------------------------------------------------------------------- |
||
1677 | //* \fn AT91F_US_EnableRx |
||
1678 | //* \brief Enable receiving characters |
||
1679 | //*---------------------------------------------------------------------------- |
||
1680 | static inline void AT91F_US_EnableRx ( |
||
1681 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1682 | { |
||
1683 | //* Enable receiver |
||
1684 | pUSART->US_CR = AT91C_US_RXEN; |
||
1685 | } |
||
1686 | |||
1687 | //*---------------------------------------------------------------------------- |
||
1688 | //* \fn AT91F_US_EnableTx |
||
1689 | //* \brief Enable sending characters |
||
1690 | //*---------------------------------------------------------------------------- |
||
1691 | static inline void AT91F_US_EnableTx ( |
||
1692 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1693 | { |
||
1694 | //* Enable transmitter |
||
1695 | pUSART->US_CR = AT91C_US_TXEN; |
||
1696 | } |
||
1697 | |||
1698 | //*---------------------------------------------------------------------------- |
||
1699 | //* \fn AT91F_US_ResetRx |
||
1700 | //* \brief Reset Receiver and re-enable it |
||
1701 | //*---------------------------------------------------------------------------- |
||
1702 | static inline void AT91F_US_ResetRx ( |
||
1703 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1704 | { |
||
1705 | //* Reset receiver |
||
1706 | pUSART->US_CR = AT91C_US_RSTRX; |
||
1707 | //* Re-Enable receiver |
||
1708 | pUSART->US_CR = AT91C_US_RXEN; |
||
1709 | } |
||
1710 | |||
1711 | //*---------------------------------------------------------------------------- |
||
1712 | //* \fn AT91F_US_ResetTx |
||
1713 | //* \brief Reset Transmitter and re-enable it |
||
1714 | //*---------------------------------------------------------------------------- |
||
1715 | static inline void AT91F_US_ResetTx ( |
||
1716 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1717 | { |
||
1718 | //* Reset transmitter |
||
1719 | pUSART->US_CR = AT91C_US_RSTTX; |
||
1720 | //* Enable transmitter |
||
1721 | pUSART->US_CR = AT91C_US_TXEN; |
||
1722 | } |
||
1723 | |||
1724 | //*---------------------------------------------------------------------------- |
||
1725 | //* \fn AT91F_US_DisableRx |
||
1726 | //* \brief Disable Receiver |
||
1727 | //*---------------------------------------------------------------------------- |
||
1728 | static inline void AT91F_US_DisableRx ( |
||
1729 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1730 | { |
||
1731 | //* Disable receiver |
||
1732 | pUSART->US_CR = AT91C_US_RXDIS; |
||
1733 | } |
||
1734 | |||
1735 | //*---------------------------------------------------------------------------- |
||
1736 | //* \fn AT91F_US_DisableTx |
||
1737 | //* \brief Disable Transmitter |
||
1738 | //*---------------------------------------------------------------------------- |
||
1739 | static inline void AT91F_US_DisableTx ( |
||
1740 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1741 | { |
||
1742 | //* Disable transmitter |
||
1743 | pUSART->US_CR = AT91C_US_TXDIS; |
||
1744 | } |
||
1745 | |||
1746 | //*---------------------------------------------------------------------------- |
||
1747 | //* \fn AT91F_US_Close |
||
1748 | //* \brief Close USART: disable IT disable receiver and transmitter, close PDC |
||
1749 | //*---------------------------------------------------------------------------- |
||
1750 | static inline void AT91F_US_Close ( |
||
1751 | AT91PS_USART pUSART) // \arg pointer to a USART controller |
||
1752 | { |
||
1753 | //* Reset the baud rate divisor register |
||
1754 | pUSART->US_BRGR = 0 ; |
||
1755 | |||
1756 | //* Reset the USART mode |
||
1757 | pUSART->US_MR = 0 ; |
||
1758 | |||
1759 | //* Reset the Timeguard Register |
||
1760 | pUSART->US_TTGR = 0; |
||
1761 | |||
1762 | //* Disable all interrupts |
||
1763 | pUSART->US_IDR = 0xFFFFFFFF ; |
||
1764 | |||
1765 | //* Abort the Peripheral Data Transfers |
||
1766 | AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); |
||
1767 | |||
1768 | //* Disable receiver and transmitter and stop any activity immediately |
||
1769 | pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; |
||
1770 | } |
||
1771 | |||
1772 | //*---------------------------------------------------------------------------- |
||
1773 | //* \fn AT91F_US_TxReady |
||
1774 | //* \brief Return 1 if a character can be written in US_THR |
||
1775 | //*---------------------------------------------------------------------------- |
||
1776 | static inline unsigned int AT91F_US_TxReady ( |
||
1777 | AT91PS_USART pUSART ) // \arg pointer to a USART controller |
||
1778 | { |
||
1779 | return (pUSART->US_CSR & AT91C_US_TXRDY); |
||
1780 | } |
||
1781 | |||
1782 | //*---------------------------------------------------------------------------- |
||
1783 | //* \fn AT91F_US_RxReady |
||
1784 | //* \brief Return 1 if a character can be read in US_RHR |
||
1785 | //*---------------------------------------------------------------------------- |
||
1786 | static inline unsigned int AT91F_US_RxReady ( |
||
1787 | AT91PS_USART pUSART ) // \arg pointer to a USART controller |
||
1788 | { |
||
1789 | return (pUSART->US_CSR & AT91C_US_RXRDY); |
||
1790 | } |
||
1791 | |||
1792 | //*---------------------------------------------------------------------------- |
||
1793 | //* \fn AT91F_US_Error |
||
1794 | //* \brief Return the error flag |
||
1795 | //*---------------------------------------------------------------------------- |
||
1796 | static inline unsigned int AT91F_US_Error ( |
||
1797 | AT91PS_USART pUSART ) // \arg pointer to a USART controller |
||
1798 | { |
||
1799 | return (pUSART->US_CSR & |
||
1800 | (AT91C_US_OVRE | // Overrun error |
||
1801 | AT91C_US_FRAME | // Framing error |
||
1802 | AT91C_US_PARE)); // Parity error |
||
1803 | } |
||
1804 | |||
1805 | //*---------------------------------------------------------------------------- |
||
1806 | //* \fn AT91F_US_PutChar |
||
1807 | //* \brief Send a character,does not check if ready to send |
||
1808 | //*---------------------------------------------------------------------------- |
||
1809 | static inline void AT91F_US_PutChar ( |
||
1810 | AT91PS_USART pUSART, |
||
1811 | int character ) |
||
1812 | { |
||
1813 | pUSART->US_THR = (character & 0x1FF); |
||
1814 | } |
||
1815 | |||
1816 | //*---------------------------------------------------------------------------- |
||
1817 | //* \fn AT91F_US_GetChar |
||
1818 | //* \brief Receive a character,does not check if a character is available |
||
1819 | //*---------------------------------------------------------------------------- |
||
1820 | static inline int AT91F_US_GetChar ( |
||
1821 | const AT91PS_USART pUSART) |
||
1822 | { |
||
1823 | return((pUSART->US_RHR) & 0x1FF); |
||
1824 | } |
||
1825 | |||
1826 | //*---------------------------------------------------------------------------- |
||
1827 | //* \fn AT91F_US_SendFrame |
||
1828 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy |
||
1829 | //*---------------------------------------------------------------------------- |
||
1830 | static inline unsigned int AT91F_US_SendFrame( |
||
1831 | AT91PS_USART pUSART, |
||
1832 | char *pBuffer, |
||
1833 | unsigned int szBuffer, |
||
1834 | char *pNextBuffer, |
||
1835 | unsigned int szNextBuffer ) |
||
1836 | { |
||
1837 | return AT91F_PDC_SendFrame( |
||
1838 | (AT91PS_PDC) &(pUSART->US_RPR), |
||
1839 | pBuffer, |
||
1840 | szBuffer, |
||
1841 | pNextBuffer, |
||
1842 | szNextBuffer); |
||
1843 | } |
||
1844 | |||
1845 | //*---------------------------------------------------------------------------- |
||
1846 | //* \fn AT91F_US_ReceiveFrame |
||
1847 | //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy |
||
1848 | //*---------------------------------------------------------------------------- |
||
1849 | static inline unsigned int AT91F_US_ReceiveFrame ( |
||
1850 | AT91PS_USART pUSART, |
||
1851 | char *pBuffer, |
||
1852 | unsigned int szBuffer, |
||
1853 | char *pNextBuffer, |
||
1854 | unsigned int szNextBuffer ) |
||
1855 | { |
||
1856 | return AT91F_PDC_ReceiveFrame( |
||
1857 | (AT91PS_PDC) &(pUSART->US_RPR), |
||
1858 | pBuffer, |
||
1859 | szBuffer, |
||
1860 | pNextBuffer, |
||
1861 | szNextBuffer); |
||
1862 | } |
||
1863 | |||
1864 | //*---------------------------------------------------------------------------- |
||
1865 | //* \fn AT91F_US_SetIrdaFilter |
||
1866 | //* \brief Set the value of IrDa filter tregister |
||
1867 | //*---------------------------------------------------------------------------- |
||
1868 | static inline void AT91F_US_SetIrdaFilter ( |
||
1869 | AT91PS_USART pUSART, |
||
1870 | unsigned char value |
||
1871 | ) |
||
1872 | { |
||
1873 | pUSART->US_IF = value; |
||
1874 | } |
||
1875 | |||
1876 | /* ***************************************************************************** |
||
1877 | SOFTWARE API FOR MCI |
||
1878 | ***************************************************************************** */ |
||
1879 | //* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock |
||
1880 | #define AT91C_MCI_MR_PDCMODE (AT91C_MCI_CLKDIV |\ |
||
1881 | AT91C_MCI_PWSDIV |\ |
||
1882 | (AT91C_MCI_PWSDIV<<1) |\ |
||
1883 | AT91C_MCI_PDCMODE) |
||
1884 | |||
1885 | //* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer |
||
1886 | #define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) |
||
1887 | |||
1888 | //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A |
||
1889 | #define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) |
||
1890 | |||
1891 | //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B |
||
1892 | #define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) |
||
1893 | |||
1894 | //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A |
||
1895 | #define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) |
||
1896 | |||
1897 | //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B |
||
1898 | #define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) |
||
1899 | |||
1900 | |||
1901 | |||
1902 | //*---------------------------------------------------------------------------- |
||
1903 | //* \fn AT91F_MCI_Configure |
||
1904 | //* \brief Configure the MCI |
||
1905 | //*---------------------------------------------------------------------------- |
||
1906 | static inline void AT91F_MCI_Configure ( |
||
1907 | AT91PS_MCI pMCI, // \arg pointer to a MCI controller |
||
1908 | unsigned int DTOR_register, // \arg Data Timeout Register to be programmed |
||
1909 | unsigned int MR_register, // \arg Mode Register to be programmed |
||
1910 | unsigned int SDCR_register) // \arg SDCard Register to be programmed |
||
1911 | { |
||
1912 | //* Reset the MCI |
||
1913 | pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; |
||
1914 | |||
1915 | //* Disable all the interrupts |
||
1916 | pMCI->MCI_IDR = 0xFFFFFFFF; |
||
1917 | |||
1918 | //* Set the Data Timeout Register |
||
1919 | pMCI->MCI_DTOR = DTOR_register; |
||
1920 | |||
1921 | //* Set the Mode Register |
||
1922 | pMCI->MCI_MR = MR_register; |
||
1923 | |||
1924 | //* Set the SDCard Register |
||
1925 | pMCI->MCI_SDCR = SDCR_register; |
||
1926 | } |
||
1927 | |||
1928 | //*---------------------------------------------------------------------------- |
||
1929 | //* \fn AT91F_MCI_EnableIt |
||
1930 | //* \brief Enable MCI IT |
||
1931 | //*---------------------------------------------------------------------------- |
||
1932 | static inline void AT91F_MCI_EnableIt ( |
||
1933 | AT91PS_MCI pMCI, // \arg pointer to a MCI controller |
||
1934 | unsigned int flag) // \arg IT to be enabled |
||
1935 | { |
||
1936 | //* Write to the IER register |
||
1937 | pMCI->MCI_IER = flag; |
||
1938 | } |
||
1939 | |||
1940 | //*---------------------------------------------------------------------------- |
||
1941 | //* \fn AT91F_MCI_DisableIt |
||
1942 | //* \brief Disable MCI IT |
||
1943 | //*---------------------------------------------------------------------------- |
||
1944 | static inline void AT91F_MCI_DisableIt ( |
||
1945 | AT91PS_MCI pMCI, // \arg pointer to a MCI controller |
||
1946 | unsigned int flag) // \arg IT to be disabled |
||
1947 | { |
||
1948 | //* Write to the IDR register |
||
1949 | pMCI->MCI_IDR = flag; |
||
1950 | } |
||
1951 | |||
1952 | //*---------------------------------------------------------------------------- |
||
1953 | //* \fn AT91F_MCI_Enable_Interface |
||
1954 | //* \brief Enable the MCI Interface |
||
1955 | //*---------------------------------------------------------------------------- |
||
1956 | static inline void AT91F_MCI_Enable_Interface ( |
||
1957 | AT91PS_MCI pMCI) // \arg pointer to a MCI controller |
||
1958 | { |
||
1959 | //* Enable the MCI |
||
1960 | pMCI->MCI_CR = AT91C_MCI_MCIEN; |
||
1961 | } |
||
1962 | |||
1963 | //*---------------------------------------------------------------------------- |
||
1964 | //* \fn AT91F_MCI_Disable_Interface |
||
1965 | //* \brief Disable the MCI Interface |
||
1966 | //*---------------------------------------------------------------------------- |
||
1967 | static inline void AT91F_MCI_Disable_Interface ( |
||
1968 | AT91PS_MCI pMCI) // \arg pointer to a MCI controller |
||
1969 | { |
||
1970 | //* Disable the MCI |
||
1971 | pMCI->MCI_CR = AT91C_MCI_MCIDIS; |
||
1972 | } |
||
1973 | |||
1974 | //*---------------------------------------------------------------------------- |
||
1975 | //* \fn AT91F_MCI_Cfg_ModeRegister |
||
1976 | //* \brief Configure the MCI Mode Register |
||
1977 | //*---------------------------------------------------------------------------- |
||
1978 | static inline void AT91F_MCI_Cfg_ModeRegister ( |
||
1979 | AT91PS_MCI pMCI, // \arg pointer to a MCI controller |
||
1980 | unsigned int mode_register) // \arg value to set in the mode register |
||
1981 | { |
||
1982 | //* Configure the MCI MR |
||
1983 | pMCI->MCI_MR = mode_register; |
||
1984 | } |
||
1985 | /* ***************************************************************************** |
||
1986 | SOFTWARE API FOR AIC |
||
1987 | ***************************************************************************** */ |
||
1988 | #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] |
||
1989 | |||
1990 | //*---------------------------------------------------------------------------- |
||
1991 | //* \fn AT91F_AIC_ConfigureIt |
||
1992 | //* \brief Interrupt Handler Initialization |
||
1993 | //*---------------------------------------------------------------------------- |
||
1994 | static inline unsigned int AT91F_AIC_ConfigureIt ( |
||
1995 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
1996 | unsigned int irq_id, // \arg interrupt number to initialize |
||
1997 | unsigned int priority, // \arg priority to give to the interrupt |
||
1998 | unsigned int src_type, // \arg activation and sense of activation |
||
1999 | void (*newHandler) (void) ) // \arg address of the interrupt handler |
||
2000 | { |
||
2001 | unsigned int oldHandler; |
||
2002 | unsigned int mask ; |
||
2003 | |||
2004 | oldHandler = pAic->AIC_SVR[irq_id]; |
||
2005 | |||
2006 | mask = 0x1 << irq_id ; |
||
2007 | //* Disable the interrupt on the interrupt controller |
||
2008 | pAic->AIC_IDCR = mask ; |
||
2009 | //* Save the interrupt handler routine pointer and the interrupt priority |
||
2010 | pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; |
||
2011 | //* Store the Source Mode Register |
||
2012 | pAic->AIC_SMR[irq_id] = src_type | priority ; |
||
2013 | //* Clear the interrupt on the interrupt controller |
||
2014 | pAic->AIC_ICCR = mask ; |
||
2015 | |||
2016 | return oldHandler; |
||
2017 | } |
||
2018 | |||
2019 | //*---------------------------------------------------------------------------- |
||
2020 | //* \fn AT91F_AIC_EnableIt |
||
2021 | //* \brief Enable corresponding IT number |
||
2022 | //*---------------------------------------------------------------------------- |
||
2023 | static inline void AT91F_AIC_EnableIt ( |
||
2024 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2025 | unsigned int irq_id ) // \arg interrupt number to initialize |
||
2026 | { |
||
2027 | //* Enable the interrupt on the interrupt controller |
||
2028 | pAic->AIC_IECR = 0x1 << irq_id ; |
||
2029 | } |
||
2030 | |||
2031 | //*---------------------------------------------------------------------------- |
||
2032 | //* \fn AT91F_AIC_DisableIt |
||
2033 | //* \brief Disable corresponding IT number |
||
2034 | //*---------------------------------------------------------------------------- |
||
2035 | static inline void AT91F_AIC_DisableIt ( |
||
2036 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2037 | unsigned int irq_id ) // \arg interrupt number to initialize |
||
2038 | { |
||
2039 | unsigned int mask = 0x1 << irq_id; |
||
2040 | //* Disable the interrupt on the interrupt controller |
||
2041 | pAic->AIC_IDCR = mask ; |
||
2042 | //* Clear the interrupt on the Interrupt Controller ( if one is pending ) |
||
2043 | pAic->AIC_ICCR = mask ; |
||
2044 | } |
||
2045 | |||
2046 | //*---------------------------------------------------------------------------- |
||
2047 | //* \fn AT91F_AIC_ClearIt |
||
2048 | //* \brief Clear corresponding IT number |
||
2049 | //*---------------------------------------------------------------------------- |
||
2050 | static inline void AT91F_AIC_ClearIt ( |
||
2051 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2052 | unsigned int irq_id) // \arg interrupt number to initialize |
||
2053 | { |
||
2054 | //* Clear the interrupt on the Interrupt Controller ( if one is pending ) |
||
2055 | pAic->AIC_ICCR = (0x1 << irq_id); |
||
2056 | } |
||
2057 | |||
2058 | //*---------------------------------------------------------------------------- |
||
2059 | //* \fn AT91F_AIC_AcknowledgeIt |
||
2060 | //* \brief Acknowledge corresponding IT number |
||
2061 | //*---------------------------------------------------------------------------- |
||
2062 | static inline void AT91F_AIC_AcknowledgeIt ( |
||
2063 | AT91PS_AIC pAic) // \arg pointer to the AIC registers |
||
2064 | { |
||
2065 | pAic->AIC_EOICR = pAic->AIC_EOICR; |
||
2066 | } |
||
2067 | |||
2068 | //*---------------------------------------------------------------------------- |
||
2069 | //* \fn AT91F_AIC_SetExceptionVector |
||
2070 | //* \brief Configure vector handler |
||
2071 | //*---------------------------------------------------------------------------- |
||
2072 | static inline unsigned int AT91F_AIC_SetExceptionVector ( |
||
2073 | unsigned int *pVector, // \arg pointer to the AIC registers |
||
2074 | void (*Handler) () ) // \arg Interrupt Handler |
||
2075 | { |
||
2076 | unsigned int oldVector = *pVector; |
||
2077 | |||
2078 | if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) |
||
2079 | *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; |
||
2080 | else |
||
2081 | *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; |
||
2082 | |||
2083 | return oldVector; |
||
2084 | } |
||
2085 | |||
2086 | //*---------------------------------------------------------------------------- |
||
2087 | //* \fn AT91F_AIC_Trig |
||
2088 | //* \brief Trig an IT |
||
2089 | //*---------------------------------------------------------------------------- |
||
2090 | static inline void AT91F_AIC_Trig ( |
||
2091 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2092 | unsigned int irq_id) // \arg interrupt number |
||
2093 | { |
||
2094 | pAic->AIC_ISCR = (0x1 << irq_id) ; |
||
2095 | } |
||
2096 | |||
2097 | //*---------------------------------------------------------------------------- |
||
2098 | //* \fn AT91F_AIC_IsActive |
||
2099 | //* \brief Test if an IT is active |
||
2100 | //*---------------------------------------------------------------------------- |
||
2101 | static inline unsigned int AT91F_AIC_IsActive ( |
||
2102 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2103 | unsigned int irq_id) // \arg Interrupt Number |
||
2104 | { |
||
2105 | return (pAic->AIC_ISR & (0x1 << irq_id)); |
||
2106 | } |
||
2107 | |||
2108 | //*---------------------------------------------------------------------------- |
||
2109 | //* \fn AT91F_AIC_IsPending |
||
2110 | //* \brief Test if an IT is pending |
||
2111 | //*---------------------------------------------------------------------------- |
||
2112 | static inline unsigned int AT91F_AIC_IsPending ( |
||
2113 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2114 | unsigned int irq_id) // \arg Interrupt Number |
||
2115 | { |
||
2116 | return (pAic->AIC_IPR & (0x1 << irq_id)); |
||
2117 | } |
||
2118 | |||
2119 | //*---------------------------------------------------------------------------- |
||
2120 | //* \fn AT91F_AIC_Open |
||
2121 | //* \brief Set exception vectors and AIC registers to default values |
||
2122 | //*---------------------------------------------------------------------------- |
||
2123 | static inline void AT91F_AIC_Open( |
||
2124 | AT91PS_AIC pAic, // \arg pointer to the AIC registers |
||
2125 | void (*IrqHandler) (), // \arg Default IRQ vector exception |
||
2126 | void (*FiqHandler) (), // \arg Default FIQ vector exception |
||
2127 | void (*DefaultHandler) (), // \arg Default Handler set in ISR |
||
2128 | void (*SpuriousHandler) (), // \arg Default Spurious Handler |
||
2129 | unsigned int protectMode) // \arg Debug Control Register |
||
2130 | { |
||
2131 | int i; |
||
2132 | |||
2133 | // Disable all interrupts and set IVR to the default handler |
||
2134 | for (i = 0; i < 32; ++i) { |
||
2135 | AT91F_AIC_DisableIt(pAic, i); |
||
2136 | AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); |
||
2137 | } |
||
2138 | |||
2139 | // Set the IRQ exception vector |
||
2140 | AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); |
||
2141 | // Set the Fast Interrupt exception vector |
||
2142 | AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); |
||
2143 | |||
2144 | pAic->AIC_SPU = (unsigned int) SpuriousHandler; |
||
2145 | pAic->AIC_DCR = protectMode; |
||
2146 | } |
||
2147 | /* ***************************************************************************** |
||
2148 | SOFTWARE API FOR UDP |
||
2149 | ***************************************************************************** */ |
||
2150 | //*---------------------------------------------------------------------------- |
||
2151 | //* \fn AT91F_UDP_EnableIt |
||
2152 | //* \brief Enable UDP IT |
||
2153 | //*---------------------------------------------------------------------------- |
||
2154 | static inline void AT91F_UDP_EnableIt ( |
||
2155 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2156 | unsigned int flag) // \arg IT to be enabled |
||
2157 | { |
||
2158 | //* Write to the IER register |
||
2159 | pUDP->UDP_IER = flag; |
||
2160 | } |
||
2161 | |||
2162 | //*---------------------------------------------------------------------------- |
||
2163 | //* \fn AT91F_UDP_DisableIt |
||
2164 | //* \brief Disable UDP IT |
||
2165 | //*---------------------------------------------------------------------------- |
||
2166 | static inline void AT91F_UDP_DisableIt ( |
||
2167 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2168 | unsigned int flag) // \arg IT to be disabled |
||
2169 | { |
||
2170 | //* Write to the IDR register |
||
2171 | pUDP->UDP_IDR = flag; |
||
2172 | } |
||
2173 | |||
2174 | //*---------------------------------------------------------------------------- |
||
2175 | //* \fn AT91F_UDP_SetAddress |
||
2176 | //* \brief Set UDP functional address |
||
2177 | //*---------------------------------------------------------------------------- |
||
2178 | static inline void AT91F_UDP_SetAddress ( |
||
2179 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2180 | unsigned char address) // \arg new UDP address |
||
2181 | { |
||
2182 | pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); |
||
2183 | } |
||
2184 | |||
2185 | //*---------------------------------------------------------------------------- |
||
2186 | //* \fn AT91F_UDP_EnableEp |
||
2187 | //* \brief Enable Endpoint |
||
2188 | //*---------------------------------------------------------------------------- |
||
2189 | static inline void AT91F_UDP_EnableEp ( |
||
2190 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2191 | unsigned int flag) // \arg endpoints to be enabled |
||
2192 | { |
||
2193 | pUDP->UDP_GLBSTATE |= flag; |
||
2194 | } |
||
2195 | |||
2196 | //*---------------------------------------------------------------------------- |
||
2197 | //* \fn AT91F_UDP_DisableEp |
||
2198 | //* \brief Enable Endpoint |
||
2199 | //*---------------------------------------------------------------------------- |
||
2200 | static inline void AT91F_UDP_DisableEp ( |
||
2201 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2202 | unsigned int flag) // \arg endpoints to be enabled |
||
2203 | { |
||
2204 | pUDP->UDP_GLBSTATE &= ~(flag); |
||
2205 | } |
||
2206 | |||
2207 | //*---------------------------------------------------------------------------- |
||
2208 | //* \fn AT91F_UDP_SetState |
||
2209 | //* \brief Set UDP Device state |
||
2210 | //*---------------------------------------------------------------------------- |
||
2211 | static inline void AT91F_UDP_SetState ( |
||
2212 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2213 | unsigned int flag) // \arg new UDP address |
||
2214 | { |
||
2215 | pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); |
||
2216 | pUDP->UDP_GLBSTATE |= flag; |
||
2217 | } |
||
2218 | |||
2219 | //*---------------------------------------------------------------------------- |
||
2220 | //* \fn AT91F_UDP_GetState |
||
2221 | //* \brief return UDP Device state |
||
2222 | //*---------------------------------------------------------------------------- |
||
2223 | static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state |
||
2224 | AT91PS_UDP pUDP) // \arg pointer to a UDP controller |
||
2225 | { |
||
2226 | return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); |
||
2227 | } |
||
2228 | |||
2229 | //*---------------------------------------------------------------------------- |
||
2230 | //* \fn AT91F_UDP_ResetEp |
||
2231 | //* \brief Reset UDP endpoint |
||
2232 | //*---------------------------------------------------------------------------- |
||
2233 | static inline void AT91F_UDP_ResetEp ( // \return the UDP device state |
||
2234 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2235 | unsigned int flag) // \arg Endpoints to be reset |
||
2236 | { |
||
2237 | pUDP->UDP_RSTEP = flag; |
||
2238 | } |
||
2239 | |||
2240 | //*---------------------------------------------------------------------------- |
||
2241 | //* \fn AT91F_UDP_EpStall |
||
2242 | //* \brief Endpoint will STALL requests |
||
2243 | //*---------------------------------------------------------------------------- |
||
2244 | static inline void AT91F_UDP_EpStall( |
||
2245 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2246 | unsigned char endpoint) // \arg endpoint number |
||
2247 | { |
||
2248 | pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; |
||
2249 | } |
||
2250 | |||
2251 | //*---------------------------------------------------------------------------- |
||
2252 | //* \fn AT91F_UDP_EpWrite |
||
2253 | //* \brief Write value in the DPR |
||
2254 | //*---------------------------------------------------------------------------- |
||
2255 | static inline void AT91F_UDP_EpWrite( |
||
2256 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2257 | unsigned char endpoint, // \arg endpoint number |
||
2258 | unsigned char value) // \arg value to be written in the DPR |
||
2259 | { |
||
2260 | pUDP->UDP_FDR[endpoint] = value; |
||
2261 | } |
||
2262 | |||
2263 | //*---------------------------------------------------------------------------- |
||
2264 | //* \fn AT91F_UDP_EpRead |
||
2265 | //* \brief Return value from the DPR |
||
2266 | //*---------------------------------------------------------------------------- |
||
2267 | static inline unsigned int AT91F_UDP_EpRead( |
||
2268 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2269 | unsigned char endpoint) // \arg endpoint number |
||
2270 | { |
||
2271 | return pUDP->UDP_FDR[endpoint]; |
||
2272 | } |
||
2273 | |||
2274 | //*---------------------------------------------------------------------------- |
||
2275 | //* \fn AT91F_UDP_EpEndOfWr |
||
2276 | //* \brief Notify the UDP that values in DPR are ready to be sent |
||
2277 | //*---------------------------------------------------------------------------- |
||
2278 | static inline void AT91F_UDP_EpEndOfWr( |
||
2279 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2280 | unsigned char endpoint) // \arg endpoint number |
||
2281 | { |
||
2282 | pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; |
||
2283 | } |
||
2284 | |||
2285 | //*---------------------------------------------------------------------------- |
||
2286 | //* \fn AT91F_UDP_EpClear |
||
2287 | //* \brief Clear flag in the endpoint CSR register |
||
2288 | //*---------------------------------------------------------------------------- |
||
2289 | static inline void AT91F_UDP_EpClear( |
||
2290 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2291 | unsigned char endpoint, // \arg endpoint number |
||
2292 | unsigned int flag) // \arg flag to be cleared |
||
2293 | { |
||
2294 | pUDP->UDP_CSR[endpoint] &= ~(flag); |
||
2295 | } |
||
2296 | |||
2297 | //*---------------------------------------------------------------------------- |
||
2298 | //* \fn AT91F_UDP_EpSet |
||
2299 | //* \brief Set flag in the endpoint CSR register |
||
2300 | //*---------------------------------------------------------------------------- |
||
2301 | static inline void AT91F_UDP_EpSet( |
||
2302 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2303 | unsigned char endpoint, // \arg endpoint number |
||
2304 | unsigned int flag) // \arg flag to be cleared |
||
2305 | { |
||
2306 | pUDP->UDP_CSR[endpoint] |= flag; |
||
2307 | } |
||
2308 | |||
2309 | //*---------------------------------------------------------------------------- |
||
2310 | //* \fn AT91F_UDP_EpStatus |
||
2311 | //* \brief Return the endpoint CSR register |
||
2312 | //*---------------------------------------------------------------------------- |
||
2313 | static inline unsigned int AT91F_UDP_EpStatus( |
||
2314 | AT91PS_UDP pUDP, // \arg pointer to a UDP controller |
||
2315 | unsigned char endpoint) // \arg endpoint number |
||
2316 | { |
||
2317 | return pUDP->UDP_CSR[endpoint]; |
||
2318 | } |
||
2319 | |||
2320 | //*---------------------------------------------------------------------------- |
||
2321 | //* \fn AT91F_UDP_GetInterruptMaskStatus |
||
2322 | //* \brief Return UDP Interrupt Mask Status |
||
2323 | //*---------------------------------------------------------------------------- |
||
2324 | static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status |
||
2325 | AT91PS_UDP pUdp) // \arg pointer to a UDP controller |
||
2326 | { |
||
2327 | return pUdp->UDP_IMR; |
||
2328 | } |
||
2329 | |||
2330 | //*---------------------------------------------------------------------------- |
||
2331 | //* \fn AT91F_UDP_IsInterruptMasked |
||
2332 | //* \brief Test if UDP Interrupt is Masked |
||
2333 | //*---------------------------------------------------------------------------- |
||
2334 | static inline int AT91F_UDP_IsInterruptMasked( |
||
2335 | AT91PS_UDP pUdp, // \arg pointer to a UDP controller |
||
2336 | unsigned int flag) // \arg flag to be tested |
||
2337 | { |
||
2338 | return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); |
||
2339 | } |
||
2340 | |||
2341 | /* ***************************************************************************** |
||
2342 | SOFTWARE API FOR ST |
||
2343 | ***************************************************************************** */ |
||
2344 | //*---------------------------------------------------------------------------- |
||
2345 | //* \fn AT91F_ST_SetPeriodInterval |
||
2346 | //* \brief Set Periodic Interval Interrupt (period in ms) |
||
2347 | //*---------------------------------------------------------------------------- |
||
2348 | static inline void AT91F_ST_SetPeriodInterval( |
||
2349 | AT91PS_ST pSt, |
||
2350 | unsigned int period) |
||
2351 | { |
||
2352 | volatile int status; |
||
2353 | pSt->ST_IDR = AT91C_ST_PITS; /* Interrupt disable Register */ |
||
2354 | |||
2355 | status = pSt->ST_SR; |
||
2356 | pSt->ST_PIMR = period << 5; /* Period Interval Mode Register == timer interval = 1ms*/ |
||
2357 | } |
||
2358 | |||
2359 | //*---------------------------------------------------------------------------- |
||
2360 | //* \fn AT91F_ST_EnableIt |
||
2361 | //* \brief Enable system timer interrupt |
||
2362 | //*---------------------------------------------------------------------------- |
||
2363 | static inline void AT91F_ST_EnableIt( |
||
2364 | AT91PS_ST pSt, |
||
2365 | unsigned int flag) |
||
2366 | { |
||
2367 | pSt->ST_IER = flag; |
||
2368 | } |
||
2369 | |||
2370 | //*---------------------------------------------------------------------------- |
||
2371 | //* \fn AT91F_ST_DisableIt |
||
2372 | //* \brief Disable system timer interrupt |
||
2373 | //*---------------------------------------------------------------------------- |
||
2374 | static inline void AT91F_ST_DisableIt( |
||
2375 | AT91PS_ST pSt, |
||
2376 | unsigned int flag) |
||
2377 | { |
||
2378 | pSt->ST_IDR = flag; |
||
2379 | } |
||
2380 | |||
2381 | //*---------------------------------------------------------------------------- |
||
2382 | //* \fn AT91F_ST_GetInterruptMaskStatus |
||
2383 | //* \brief Return ST Interrupt Mask Status |
||
2384 | //*---------------------------------------------------------------------------- |
||
2385 | static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status |
||
2386 | AT91PS_ST pSt) // \arg pointer to a ST controller |
||
2387 | { |
||
2388 | return pSt->ST_IMR; |
||
2389 | } |
||
2390 | |||
2391 | //*---------------------------------------------------------------------------- |
||
2392 | //* \fn AT91F_ST_IsInterruptMasked |
||
2393 | //* \brief Test if ST Interrupt is Masked |
||
2394 | //*---------------------------------------------------------------------------- |
||
2395 | static inline int AT91F_ST_IsInterruptMasked( |
||
2396 | AT91PS_ST pSt, // \arg pointer to a ST controller |
||
2397 | unsigned int flag) // \arg flag to be tested |
||
2398 | { |
||
2399 | return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag); |
||
2400 | } |
||
2401 | //*---------------------------------------------------------------------------- |
||
2402 | //* \fn AT91F_EBI_CfgPIO |
||
2403 | //* \brief Configure PIO controllers to drive EBI signals |
||
2404 | //*---------------------------------------------------------------------------- |
||
2405 | static inline void AT91F_EBI_CfgPIO (void) |
||
2406 | { |
||
2407 | // Configure PIO controllers to periph mode |
||
2408 | AT91F_PIO_CfgPeriph( |
||
2409 | AT91C_BASE_PIOC, // PIO controller base address |
||
2410 | ((unsigned int) AT91C_PC8_A24 ) | |
||
2411 | ((unsigned int) AT91C_PC7_A23 ), // Peripheral A |
||
2412 | 0); // Peripheral B |
||
2413 | } |
||
2414 | |||
2415 | //*---------------------------------------------------------------------------- |
||
2416 | //* \fn AT91F_DBGU_CfgPMC |
||
2417 | //* \brief Enable Peripheral clock in PMC for DBGU |
||
2418 | //*---------------------------------------------------------------------------- |
||
2419 | static inline void AT91F_DBGU_CfgPMC (void) |
||
2420 | { |
||
2421 | AT91F_PMC_EnablePeriphClock( |
||
2422 | AT91C_BASE_PMC, // PIO controller base address |
||
2423 | ((unsigned int) 1 << AT91C_ID_SYS)); |
||
2424 | } |
||
2425 | |||
2426 | //*---------------------------------------------------------------------------- |
||
2427 | //* \fn AT91F_DBGU_CfgPIO |
||
2428 | //* \brief Configure PIO controllers to drive DBGU signals |
||
2429 | //*---------------------------------------------------------------------------- |
||
2430 | static inline void AT91F_DBGU_CfgPIO (void) |
||
2431 | { |
||
2432 | // Configure PIO controllers to periph mode |
||
2433 | AT91F_PIO_CfgPeriph( |
||
2434 | AT91C_BASE_PIOA, // PIO controller base address |
||
2435 | ((unsigned int) AT91C_PA31_DTXD ) | |
||
2436 | ((unsigned int) AT91C_PA30_DRXD ), // Peripheral A |
||
2437 | 0); // Peripheral B |
||
2438 | } |
||
2439 | |||
2440 | //*---------------------------------------------------------------------------- |
||
2441 | //* \fn AT91F_SYS_CfgPMC |
||
2442 | //* \brief Enable Peripheral clock in PMC for SYS |
||
2443 | //*---------------------------------------------------------------------------- |
||
2444 | static inline void AT91F_SYS_CfgPMC (void) |
||
2445 | { |
||
2446 | AT91F_PMC_EnablePeriphClock( |
||
2447 | AT91C_BASE_PMC, // PIO controller base address |
||
2448 | ((unsigned int) 1 << AT91C_ID_SYS)); |
||
2449 | } |
||
2450 | |||
2451 | //*---------------------------------------------------------------------------- |
||
2452 | //* \fn AT91F_UHP_CfgPMC |
||
2453 | //* \brief Enable Peripheral clock in PMC for UHP |
||
2454 | //*---------------------------------------------------------------------------- |
||
2455 | static inline void AT91F_UHP_CfgPMC (void) |
||
2456 | { |
||
2457 | AT91F_PMC_EnablePeriphClock( |
||
2458 | AT91C_BASE_PMC, // PIO controller base address |
||
2459 | ((unsigned int) 1 << AT91C_ID_UHP)); |
||
2460 | } |
||
2461 | |||
2462 | //*---------------------------------------------------------------------------- |
||
2463 | //* \fn AT91F_SDRC_CfgPIO |
||
2464 | //* \brief Configure PIO controllers to drive SDRC signals |
||
2465 | //*---------------------------------------------------------------------------- |
||
2466 | static inline void AT91F_SDRC_CfgPIO (void) |
||
2467 | { |
||
2468 | // Configure PIO controllers to periph mode |
||
2469 | AT91F_PIO_CfgPeriph( |
||
2470 | AT91C_BASE_PIOC, // PIO controller base address |
||
2471 | ((unsigned int) AT91C_PC20_D20 ) | |
||
2472 | ((unsigned int) AT91C_PC21_D21 ) | |
||
2473 | ((unsigned int) AT91C_PC30_D30 ) | |
||
2474 | ((unsigned int) AT91C_PC22_D22 ) | |
||
2475 | ((unsigned int) AT91C_PC31_D31 ) | |
||
2476 | ((unsigned int) AT91C_PC23_D23 ) | |
||
2477 | ((unsigned int) AT91C_PC16_D16 ) | |
||
2478 | ((unsigned int) AT91C_PC24_D24 ) | |
||
2479 | ((unsigned int) AT91C_PC17_D17 ) | |
||
2480 | ((unsigned int) AT91C_PC25_D25 ) | |
||
2481 | ((unsigned int) AT91C_PC18_D18 ) | |
||
2482 | ((unsigned int) AT91C_PC26_D26 ) | |
||
2483 | ((unsigned int) AT91C_PC19_D19 ) | |
||
2484 | ((unsigned int) AT91C_PC27_D27 ) | |
||
2485 | ((unsigned int) AT91C_PC28_D28 ) | |
||
2486 | ((unsigned int) AT91C_PC29_D29 ), // Peripheral A |
||
2487 | 0); // Peripheral B |
||
2488 | } |
||
2489 | |||
2490 | //*---------------------------------------------------------------------------- |
||
2491 | //* \fn AT91F_EMAC_CfgPMC |
||
2492 | //* \brief Enable Peripheral clock in PMC for EMAC |
||
2493 | //*---------------------------------------------------------------------------- |
||
2494 | static inline void AT91F_EMAC_CfgPMC (void) |
||
2495 | { |
||
2496 | AT91F_PMC_EnablePeriphClock( |
||
2497 | AT91C_BASE_PMC, // PIO controller base address |
||
2498 | ((unsigned int) 1 << AT91C_ID_EMAC)); |
||
2499 | } |
||
2500 | |||
2501 | //*---------------------------------------------------------------------------- |
||
2502 | //* \fn AT91F_EMAC_CfgPIO |
||
2503 | //* \brief Configure PIO controllers to drive EMAC signals |
||
2504 | //*---------------------------------------------------------------------------- |
||
2505 | static inline void AT91F_EMAC_CfgPIO (void) |
||
2506 | { |
||
2507 | // Configure PIO controllers to periph mode |
||
2508 | AT91F_PIO_CfgPeriph( |
||
2509 | AT91C_BASE_PIOA, // PIO controller base address |
||
2510 | ((unsigned int) AT91C_PA14_ERXER ) | |
||
2511 | ((unsigned int) AT91C_PA12_ERX0 ) | |
||
2512 | ((unsigned int) AT91C_PA13_ERX1 ) | |
||
2513 | ((unsigned int) AT91C_PA8_ETXEN ) | |
||
2514 | ((unsigned int) AT91C_PA16_EMDIO ) | |
||
2515 | ((unsigned int) AT91C_PA9_ETX0 ) | |
||
2516 | ((unsigned int) AT91C_PA10_ETX1 ) | |
||
2517 | ((unsigned int) AT91C_PA11_ECRS_ECRSDV) | |
||
2518 | ((unsigned int) AT91C_PA15_EMDC ) | |
||
2519 | ((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A |
||
2520 | 0); // Peripheral B |
||
2521 | } |
||
2522 | |||
2523 | //*---------------------------------------------------------------------------- |
||
2524 | //* \fn AT91F_RTC_CfgPMC |
||
2525 | //* \brief Enable Peripheral clock in PMC for RTC |
||
2526 | //*---------------------------------------------------------------------------- |
||
2527 | static inline void AT91F_RTC_CfgPMC (void) |
||
2528 | { |
||
2529 | AT91F_PMC_EnablePeriphClock( |
||
2530 | AT91C_BASE_PMC, // PIO controller base address |
||
2531 | ((unsigned int) 1 << AT91C_ID_SYS)); |
||
2532 | } |
||
2533 | |||
2534 | //*---------------------------------------------------------------------------- |
||
2535 | //* \fn AT91F_SSC2_CfgPMC |
||
2536 | //* \brief Enable Peripheral clock in PMC for SSC2 |
||
2537 | //*---------------------------------------------------------------------------- |
||
2538 | static inline void AT91F_SSC2_CfgPMC (void) |
||
2539 | { |
||
2540 | AT91F_PMC_EnablePeriphClock( |
||
2541 | AT91C_BASE_PMC, // PIO controller base address |
||
2542 | ((unsigned int) 1 << AT91C_ID_SSC2)); |
||
2543 | } |
||
2544 | |||
2545 | //*---------------------------------------------------------------------------- |
||
2546 | //* \fn AT91F_SSC2_CfgPIO |
||
2547 | //* \brief Configure PIO controllers to drive SSC2 signals |
||
2548 | //*---------------------------------------------------------------------------- |
||
2549 | static inline void AT91F_SSC2_CfgPIO (void) |
||
2550 | { |
||
2551 | // Configure PIO controllers to periph mode |
||
2552 | AT91F_PIO_CfgPeriph( |
||
2553 | AT91C_BASE_PIOB, // PIO controller base address |
||
2554 | ((unsigned int) AT91C_PB12_TF2 ) | |
||
2555 | ((unsigned int) AT91C_PB17_RF2 ) | |
||
2556 | ((unsigned int) AT91C_PB13_TK2 ) | |
||
2557 | ((unsigned int) AT91C_PB16_RK2 ) | |
||
2558 | ((unsigned int) AT91C_PB14_TD2 ) | |
||
2559 | ((unsigned int) AT91C_PB15_RD2 ), // Peripheral A |
||
2560 | 0); // Peripheral B |
||
2561 | } |
||
2562 | |||
2563 | //*---------------------------------------------------------------------------- |
||
2564 | //* \fn AT91F_SSC1_CfgPMC |
||
2565 | //* \brief Enable Peripheral clock in PMC for SSC1 |
||
2566 | //*---------------------------------------------------------------------------- |
||
2567 | static inline void AT91F_SSC1_CfgPMC (void) |
||
2568 | { |
||
2569 | AT91F_PMC_EnablePeriphClock( |
||
2570 | AT91C_BASE_PMC, // PIO controller base address |
||
2571 | ((unsigned int) 1 << AT91C_ID_SSC1)); |
||
2572 | } |
||
2573 | |||
2574 | //*---------------------------------------------------------------------------- |
||
2575 | //* \fn AT91F_SSC1_CfgPIO |
||
2576 | //* \brief Configure PIO controllers to drive SSC1 signals |
||
2577 | //*---------------------------------------------------------------------------- |
||
2578 | static inline void AT91F_SSC1_CfgPIO (void) |
||
2579 | { |
||
2580 | // Configure PIO controllers to periph mode |
||
2581 | AT91F_PIO_CfgPeriph( |
||
2582 | AT91C_BASE_PIOB, // PIO controller base address |
||
2583 | ((unsigned int) AT91C_PB11_RF1 ) | |
||
2584 | ((unsigned int) AT91C_PB10_RK1 ) | |
||
2585 | ((unsigned int) AT91C_PB8_TD1 ) | |
||
2586 | ((unsigned int) AT91C_PB9_RD1 ), // Peripheral A |
||
2587 | 0); // Peripheral B |
||
2588 | } |
||
2589 | |||
2590 | //*---------------------------------------------------------------------------- |
||
2591 | //* \fn AT91F_SSC0_CfgPMC |
||
2592 | //* \brief Enable Peripheral clock in PMC for SSC0 |
||
2593 | //*---------------------------------------------------------------------------- |
||
2594 | static inline void AT91F_SSC0_CfgPMC (void) |
||
2595 | { |
||
2596 | AT91F_PMC_EnablePeriphClock( |
||
2597 | AT91C_BASE_PMC, // PIO controller base address |
||
2598 | ((unsigned int) 1 << AT91C_ID_SSC0)); |
||
2599 | } |
||
2600 | |||
2601 | //*---------------------------------------------------------------------------- |
||
2602 | //* \fn AT91F_SPI_CfgPMC |
||
2603 | //* \brief Enable Peripheral clock in PMC for SPI |
||
2604 | //*---------------------------------------------------------------------------- |
||
2605 | static inline void AT91F_SPI_CfgPMC (void) |
||
2606 | { |
||
2607 | AT91F_PMC_EnablePeriphClock( |
||
2608 | AT91C_BASE_PMC, // PIO controller base address |
||
2609 | ((unsigned int) 1 << AT91C_ID_SPI)); |
||
2610 | } |
||
2611 | |||
2612 | //*---------------------------------------------------------------------------- |
||
2613 | //* \fn AT91F_SPI_CfgPIO |
||
2614 | //* \brief Configure PIO controllers to drive SPI signals |
||
2615 | //*---------------------------------------------------------------------------- |
||
2616 | static inline void AT91F_SPI_CfgPIO (void) |
||
2617 | { |
||
2618 | // Configure PIO controllers to periph mode |
||
2619 | AT91F_PIO_CfgPeriph( |
||
2620 | AT91C_BASE_PIOA, // PIO controller base address |
||
2621 | ((unsigned int) AT91C_PA3_NPCS0 ) | |
||
2622 | ((unsigned int) AT91C_PA4_NPCS1 ) | |
||
2623 | ((unsigned int) AT91C_PA1_MOSI ) | |
||
2624 | ((unsigned int) AT91C_PA5_NPCS2 ) | |
||
2625 | ((unsigned int) AT91C_PA6_NPCS3 ) | |
||
2626 | ((unsigned int) AT91C_PA0_MISO ) | |
||
2627 | ((unsigned int) AT91C_PA2_SPCK ), // Peripheral A |
||
2628 | 0); // Peripheral B |
||
2629 | } |
||
2630 | |||
2631 | //*---------------------------------------------------------------------------- |
||
2632 | //* \fn AT91F_TC5_CfgPMC |
||
2633 | //* \brief Enable Peripheral clock in PMC for TC5 |
||
2634 | //*---------------------------------------------------------------------------- |
||
2635 | static inline void AT91F_TC5_CfgPMC (void) |
||
2636 | { |
||
2637 | AT91F_PMC_EnablePeriphClock( |
||
2638 | AT91C_BASE_PMC, // PIO controller base address |
||
2639 | ((unsigned int) 1 << AT91C_ID_TC5)); |
||
2640 | } |
||
2641 | |||
2642 | //*---------------------------------------------------------------------------- |
||
2643 | //* \fn AT91F_TC4_CfgPMC |
||
2644 | //* \brief Enable Peripheral clock in PMC for TC4 |
||
2645 | //*---------------------------------------------------------------------------- |
||
2646 | static inline void AT91F_TC4_CfgPMC (void) |
||
2647 | { |
||
2648 | AT91F_PMC_EnablePeriphClock( |
||
2649 | AT91C_BASE_PMC, // PIO controller base address |
||
2650 | ((unsigned int) 1 << AT91C_ID_TC4)); |
||
2651 | } |
||
2652 | |||
2653 | //*---------------------------------------------------------------------------- |
||
2654 | //* \fn AT91F_TC3_CfgPMC |
||
2655 | //* \brief Enable Peripheral clock in PMC for TC3 |
||
2656 | //*---------------------------------------------------------------------------- |
||
2657 | static inline void AT91F_TC3_CfgPMC (void) |
||
2658 | { |
||
2659 | AT91F_PMC_EnablePeriphClock( |
||
2660 | AT91C_BASE_PMC, // PIO controller base address |
||
2661 | ((unsigned int) 1 << AT91C_ID_TC3)); |
||
2662 | } |
||
2663 | |||
2664 | //*---------------------------------------------------------------------------- |
||
2665 | //* \fn AT91F_TC2_CfgPMC |
||
2666 | //* \brief Enable Peripheral clock in PMC for TC2 |
||
2667 | //*---------------------------------------------------------------------------- |
||
2668 | static inline void AT91F_TC2_CfgPMC (void) |
||
2669 | { |
||
2670 | AT91F_PMC_EnablePeriphClock( |
||
2671 | AT91C_BASE_PMC, // PIO controller base address |
||
2672 | ((unsigned int) 1 << AT91C_ID_TC2)); |
||
2673 | } |
||
2674 | |||
2675 | //*---------------------------------------------------------------------------- |
||
2676 | //* \fn AT91F_TC1_CfgPMC |
||
2677 | //* \brief Enable Peripheral clock in PMC for TC1 |
||
2678 | //*---------------------------------------------------------------------------- |
||
2679 | static inline void AT91F_TC1_CfgPMC (void) |
||
2680 | { |
||
2681 | AT91F_PMC_EnablePeriphClock( |
||
2682 | AT91C_BASE_PMC, // PIO controller base address |
||
2683 | ((unsigned int) 1 << AT91C_ID_TC1)); |
||
2684 | } |
||
2685 | |||
2686 | //*---------------------------------------------------------------------------- |
||
2687 | //* \fn AT91F_TC0_CfgPMC |
||
2688 | //* \brief Enable Peripheral clock in PMC for TC0 |
||
2689 | //*---------------------------------------------------------------------------- |
||
2690 | static inline void AT91F_TC0_CfgPMC (void) |
||
2691 | { |
||
2692 | AT91F_PMC_EnablePeriphClock( |
||
2693 | AT91C_BASE_PMC, // PIO controller base address |
||
2694 | ((unsigned int) 1 << AT91C_ID_TC0)); |
||
2695 | } |
||
2696 | |||
2697 | //*---------------------------------------------------------------------------- |
||
2698 | //* \fn AT91F_SMC2_CfgPIO |
||
2699 | //* \brief Configure PIO controllers to drive SMC2 signals |
||
2700 | //*---------------------------------------------------------------------------- |
||
2701 | static inline void AT91F_SMC2_CfgPIO (void) |
||
2702 | { |
||
2703 | // Configure PIO controllers to periph mode |
||
2704 | AT91F_PIO_CfgPeriph( |
||
2705 | AT91C_BASE_PIOC, // PIO controller base address |
||
2706 | ((unsigned int) AT91C_PC10_NCS4_CFCS) | |
||
2707 | ((unsigned int) AT91C_PC9_A25_CFRNW) | |
||
2708 | ((unsigned int) AT91C_PC12_NCS6_CFCE2) | |
||
2709 | ((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A |
||
2710 | 0); // Peripheral B |
||
2711 | } |
||
2712 | |||
2713 | //*---------------------------------------------------------------------------- |
||
2714 | //* \fn AT91F_PMC_CfgPMC |
||
2715 | //* \brief Enable Peripheral clock in PMC for PMC |
||
2716 | //*---------------------------------------------------------------------------- |
||
2717 | static inline void AT91F_PMC_CfgPMC (void) |
||
2718 | { |
||
2719 | AT91F_PMC_EnablePeriphClock( |
||
2720 | AT91C_BASE_PMC, // PIO controller base address |
||
2721 | ((unsigned int) 1 << AT91C_ID_SYS)); |
||
2722 | } |
||
2723 | |||
2724 | //*---------------------------------------------------------------------------- |
||
2725 | //* \fn AT91F_PMC_CfgPIO |
||
2726 | //* \brief Configure PIO controllers to drive PMC signals |
||
2727 | //*---------------------------------------------------------------------------- |
||
2728 | static inline void AT91F_PMC_CfgPIO (void) |
||
2729 | { |
||
2730 | // Configure PIO controllers to periph mode |
||
2731 | AT91F_PIO_CfgPeriph( |
||
2732 | AT91C_BASE_PIOA, // PIO controller base address |
||
2733 | 0, // Peripheral A |
||
2734 | ((unsigned int) AT91C_PA24_PCK1 )); // Peripheral B |
||
2735 | // Configure PIO controllers to periph mode |
||
2736 | AT91F_PIO_CfgPeriph( |
||
2737 | AT91C_BASE_PIOB, // PIO controller base address |
||
2738 | ((unsigned int) AT91C_PB27_PCK0 ), // Peripheral A |
||
2739 | 0); // Peripheral B |
||
2740 | } |
||
2741 | |||
2742 | //*---------------------------------------------------------------------------- |
||
2743 | //* \fn AT91F_PIOD_CfgPMC |
||
2744 | //* \brief Enable Peripheral clock in PMC for PIOD |
||
2745 | //*---------------------------------------------------------------------------- |
||
2746 | static inline void AT91F_PIOD_CfgPMC (void) |
||
2747 | { |
||
2748 | AT91F_PMC_EnablePeriphClock( |
||
2749 | AT91C_BASE_PMC, // PIO controller base address |
||
2750 | ((unsigned int) 1 << AT91C_ID_PIOD)); |
||
2751 | } |
||
2752 | |||
2753 | //*---------------------------------------------------------------------------- |
||
2754 | //* \fn AT91F_PIOC_CfgPMC |
||
2755 | //* \brief Enable Peripheral clock in PMC for PIOC |
||
2756 | //*---------------------------------------------------------------------------- |
||
2757 | static inline void AT91F_PIOC_CfgPMC (void) |
||
2758 | { |
||
2759 | AT91F_PMC_EnablePeriphClock( |
||
2760 | AT91C_BASE_PMC, // PIO controller base address |
||
2761 | ((unsigned int) 1 << AT91C_ID_PIOC)); |
||
2762 | } |
||
2763 | |||
2764 | //*---------------------------------------------------------------------------- |
||
2765 | //* \fn AT91F_PIOB_CfgPMC |
||
2766 | //* \brief Enable Peripheral clock in PMC for PIOB |
||
2767 | //*---------------------------------------------------------------------------- |
||
2768 | static inline void AT91F_PIOB_CfgPMC (void) |
||
2769 | { |
||
2770 | AT91F_PMC_EnablePeriphClock( |
||
2771 | AT91C_BASE_PMC, // PIO controller base address |
||
2772 | ((unsigned int) 1 << AT91C_ID_PIOB)); |
||
2773 | } |
||
2774 | |||
2775 | //*---------------------------------------------------------------------------- |
||
2776 | //* \fn AT91F_PIOA_CfgPMC |
||
2777 | //* \brief Enable Peripheral clock in PMC for PIOA |
||
2778 | //*---------------------------------------------------------------------------- |
||
2779 | static inline void AT91F_PIOA_CfgPMC (void) |
||
2780 | { |
||
2781 | AT91F_PMC_EnablePeriphClock( |
||
2782 | AT91C_BASE_PMC, // PIO controller base address |
||
2783 | ((unsigned int) 1 << AT91C_ID_PIOA)); |
||
2784 | } |
||
2785 | |||
2786 | //*---------------------------------------------------------------------------- |
||
2787 | //* \fn AT91F_TWI_CfgPMC |
||
2788 | //* \brief Enable Peripheral clock in PMC for TWI |
||
2789 | //*---------------------------------------------------------------------------- |
||
2790 | static inline void AT91F_TWI_CfgPMC (void) |
||
2791 | { |
||
2792 | AT91F_PMC_EnablePeriphClock( |
||
2793 | AT91C_BASE_PMC, // PIO controller base address |
||
2794 | ((unsigned int) 1 << AT91C_ID_TWI)); |
||
2795 | } |
||
2796 | |||
2797 | //*---------------------------------------------------------------------------- |
||
2798 | //* \fn AT91F_TWI_CfgPIO |
||
2799 | //* \brief Configure PIO controllers to drive TWI signals |
||
2800 | //*---------------------------------------------------------------------------- |
||
2801 | static inline void AT91F_TWI_CfgPIO (void) |
||
2802 | { |
||
2803 | // Configure PIO controllers to periph mode |
||
2804 | AT91F_PIO_CfgPeriph( |
||
2805 | AT91C_BASE_PIOA, // PIO controller base address |
||
2806 | ((unsigned int) AT91C_PA25_TWD ) | |
||
2807 | ((unsigned int) AT91C_PA26_TWCK ), // Peripheral A |
||
2808 | 0); // Peripheral B |
||
2809 | } |
||
2810 | |||
2811 | //*---------------------------------------------------------------------------- |
||
2812 | //* \fn AT91F_US3_CfgPMC |
||
2813 | //* \brief Enable Peripheral clock in PMC for US3 |
||
2814 | //*---------------------------------------------------------------------------- |
||
2815 | static inline void AT91F_US3_CfgPMC (void) |
||
2816 | { |
||
2817 | AT91F_PMC_EnablePeriphClock( |
||
2818 | AT91C_BASE_PMC, // PIO controller base address |
||
2819 | ((unsigned int) 1 << AT91C_ID_US3)); |
||
2820 | } |
||
2821 | |||
2822 | //*---------------------------------------------------------------------------- |
||
2823 | //* \fn AT91F_US2_CfgPMC |
||
2824 | //* \brief Enable Peripheral clock in PMC for US2 |
||
2825 | //*---------------------------------------------------------------------------- |
||
2826 | static inline void AT91F_US2_CfgPMC (void) |
||
2827 | { |
||
2828 | AT91F_PMC_EnablePeriphClock( |
||
2829 | AT91C_BASE_PMC, // PIO controller base address |
||
2830 | ((unsigned int) 1 << AT91C_ID_US2)); |
||
2831 | } |
||
2832 | |||
2833 | //*---------------------------------------------------------------------------- |
||
2834 | //* \fn AT91F_US2_CfgPIO |
||
2835 | //* \brief Configure PIO controllers to drive US2 signals |
||
2836 | //*---------------------------------------------------------------------------- |
||
2837 | static inline void AT91F_US2_CfgPIO (void) |
||
2838 | { |
||
2839 | // Configure PIO controllers to periph mode |
||
2840 | AT91F_PIO_CfgPeriph( |
||
2841 | AT91C_BASE_PIOA, // PIO controller base address |
||
2842 | ((unsigned int) AT91C_PA23_TXD2 ) | |
||
2843 | ((unsigned int) AT91C_PA22_RXD2 ), // Peripheral A |
||
2844 | 0); // Peripheral B |
||
2845 | } |
||
2846 | |||
2847 | //*---------------------------------------------------------------------------- |
||
2848 | //* \fn AT91F_US1_CfgPMC |
||
2849 | //* \brief Enable Peripheral clock in PMC for US1 |
||
2850 | //*---------------------------------------------------------------------------- |
||
2851 | static inline void AT91F_US1_CfgPMC (void) |
||
2852 | { |
||
2853 | AT91F_PMC_EnablePeriphClock( |
||
2854 | AT91C_BASE_PMC, // PIO controller base address |
||
2855 | ((unsigned int) 1 << AT91C_ID_US1)); |
||
2856 | } |
||
2857 | |||
2858 | //*---------------------------------------------------------------------------- |
||
2859 | //* \fn AT91F_US1_CfgPIO |
||
2860 | //* \brief Configure PIO controllers to drive US1 signals |
||
2861 | //*---------------------------------------------------------------------------- |
||
2862 | static inline void AT91F_US1_CfgPIO (void) |
||
2863 | { |
||
2864 | // Configure PIO controllers to periph mode |
||
2865 | AT91F_PIO_CfgPeriph( |
||
2866 | AT91C_BASE_PIOB, // PIO controller base address |
||
2867 | ((unsigned int) AT91C_PB21_RXD1 ) | |
||
2868 | ((unsigned int) AT91C_PB26_RTS1 ) | |
||
2869 | ((unsigned int) AT91C_PB25_DSR1 ) | |
||
2870 | ((unsigned int) AT91C_PB24_CTS1 ) | |
||
2871 | ((unsigned int) AT91C_PB19_DTR1 ) | |
||
2872 | ((unsigned int) AT91C_PB23_DCD1 ) | |
||
2873 | ((unsigned int) AT91C_PB20_TXD1 ) | |
||
2874 | ((unsigned int) AT91C_PB18_RI1 ), // Peripheral A |
||
2875 | 0); // Peripheral B |
||
2876 | } |
||
2877 | |||
2878 | //*---------------------------------------------------------------------------- |
||
2879 | //* \fn AT91F_US0_CfgPMC |
||
2880 | //* \brief Enable Peripheral clock in PMC for US0 |
||
2881 | //*---------------------------------------------------------------------------- |
||
2882 | static inline void AT91F_US0_CfgPMC (void) |
||
2883 | { |
||
2884 | AT91F_PMC_EnablePeriphClock( |
||
2885 | AT91C_BASE_PMC, // PIO controller base address |
||
2886 | ((unsigned int) 1 << AT91C_ID_US0)); |
||
2887 | } |
||
2888 | |||
2889 | //*---------------------------------------------------------------------------- |
||
2890 | //* \fn AT91F_US0_CfgPIO |
||
2891 | //* \brief Configure PIO controllers to drive US0 signals |
||
2892 | //*---------------------------------------------------------------------------- |
||
2893 | static inline void AT91F_US0_CfgPIO (void) |
||
2894 | { |
||
2895 | // Configure PIO controllers to periph mode |
||
2896 | AT91F_PIO_CfgPeriph( |
||
2897 | AT91C_BASE_PIOA, // PIO controller base address |
||
2898 | ((unsigned int) AT91C_PA17_TXD0 ) | |
||
2899 | ((unsigned int) AT91C_PA21_RTS0 ) | |
||
2900 | ((unsigned int) AT91C_PA19_SCK0 ) | |
||
2901 | ((unsigned int) AT91C_PA20_CTS0 ), // Peripheral A |
||
2902 | 0); // Peripheral B |
||
2903 | } |
||
2904 | |||
2905 | //*---------------------------------------------------------------------------- |
||
2906 | //* \fn AT91F_MCI_CfgPMC |
||
2907 | //* \brief Enable Peripheral clock in PMC for MCI |
||
2908 | //*---------------------------------------------------------------------------- |
||
2909 | static inline void AT91F_MCI_CfgPMC (void) |
||
2910 | { |
||
2911 | AT91F_PMC_EnablePeriphClock( |
||
2912 | AT91C_BASE_PMC, // PIO controller base address |
||
2913 | ((unsigned int) 1 << AT91C_ID_MCI)); |
||
2914 | } |
||
2915 | |||
2916 | //*---------------------------------------------------------------------------- |
||
2917 | //* \fn AT91F_MCI_CfgPIO |
||
2918 | //* \brief Configure PIO controllers to drive MCI signals |
||
2919 | //*---------------------------------------------------------------------------- |
||
2920 | static inline void AT91F_MCI_CfgPIO (void) |
||
2921 | { |
||
2922 | // Configure PIO controllers to periph mode |
||
2923 | AT91F_PIO_CfgPeriph( |
||
2924 | AT91C_BASE_PIOA, // PIO controller base address |
||
2925 | ((unsigned int) AT91C_PA28_MCCDA ) | |
||
2926 | ((unsigned int) AT91C_PA29_MCDA0 ) | |
||
2927 | ((unsigned int) AT91C_PA27_MCCK ), // Peripheral A |
||
2928 | 0); // Peripheral B |
||
2929 | // Configure PIO controllers to periph mode |
||
2930 | AT91F_PIO_CfgPeriph( |
||
2931 | AT91C_BASE_PIOB, // PIO controller base address |
||
2932 | 0, // Peripheral A |
||
2933 | ((unsigned int) AT91C_PB5_MCDA3 ) | |
||
2934 | ((unsigned int) AT91C_PB3_MCDA1 ) | |
||
2935 | ((unsigned int) AT91C_PB4_MCDA2 )); // Peripheral B |
||
2936 | } |
||
2937 | |||
2938 | //*---------------------------------------------------------------------------- |
||
2939 | //* \fn AT91F_AIC_CfgPMC |
||
2940 | //* \brief Enable Peripheral clock in PMC for AIC |
||
2941 | //*---------------------------------------------------------------------------- |
||
2942 | static inline void AT91F_AIC_CfgPMC (void) |
||
2943 | { |
||
2944 | AT91F_PMC_EnablePeriphClock( |
||
2945 | AT91C_BASE_PMC, // PIO controller base address |
||
2946 | ((unsigned int) 1 << AT91C_ID_IRQ4) | |
||
2947 | ((unsigned int) 1 << AT91C_ID_FIQ) | |
||
2948 | ((unsigned int) 1 << AT91C_ID_IRQ5) | |
||
2949 | ((unsigned int) 1 << AT91C_ID_IRQ6) | |
||
2950 | ((unsigned int) 1 << AT91C_ID_IRQ0) | |
||
2951 | ((unsigned int) 1 << AT91C_ID_IRQ1) | |
||
2952 | ((unsigned int) 1 << AT91C_ID_IRQ2) | |
||
2953 | ((unsigned int) 1 << AT91C_ID_IRQ3)); |
||
2954 | } |
||
2955 | |||
2956 | //*---------------------------------------------------------------------------- |
||
2957 | //* \fn AT91F_UDP_CfgPMC |
||
2958 | //* \brief Enable Peripheral clock in PMC for UDP |
||
2959 | //*---------------------------------------------------------------------------- |
||
2960 | static inline void AT91F_UDP_CfgPMC (void) |
||
2961 | { |
||
2962 | AT91F_PMC_EnablePeriphClock( |
||
2963 | AT91C_BASE_PMC, // PIO controller base address |
||
2964 | ((unsigned int) 1 << AT91C_ID_UDP)); |
||
2965 | } |
||
2966 | |||
2967 | //*---------------------------------------------------------------------------- |
||
2968 | //* \fn AT91F_ST_CfgPMC |
||
2969 | //* \brief Enable Peripheral clock in PMC for ST |
||
2970 | //*---------------------------------------------------------------------------- |
||
2971 | static inline void AT91F_ST_CfgPMC (void) |
||
2972 | { |
||
2973 | AT91F_PMC_EnablePeriphClock( |
||
2974 | AT91C_BASE_PMC, // PIO controller base address |
||
2975 | ((unsigned int) 1 << AT91C_ID_SYS)); |
||
2976 | } |
||
2977 | |||
2978 | #endif // lib_AT91RM9200_H |