OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/ath79/mach-db120.c |
2 | +++ b/arch/mips/ath79/mach-db120.c |
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3 | @@ -2,7 +2,7 @@ |
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4 | * Atheros DB120 reference board support |
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5 | * |
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6 | * Copyright (c) 2011 Qualcomm Atheros |
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7 | - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> |
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8 | + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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9 | * |
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10 | * Permission to use, copy, modify, and/or distribute this software for any |
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11 | * purpose with or without fee is hereby granted, provided that the above |
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12 | @@ -19,16 +19,26 @@ |
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13 | */ |
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14 | |||
15 | #include <linux/pci.h> |
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16 | +#include <linux/phy.h> |
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17 | +#include <linux/platform_device.h> |
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18 | #include <linux/ath9k_platform.h> |
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19 | +#include <linux/ar8216_platform.h> |
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20 | |||
21 | -#include "machtypes.h" |
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22 | +#include <asm/mach-ath79/ar71xx_regs.h> |
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23 | + |
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24 | +#include "common.h" |
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25 | +#include "dev-ap9x-pci.h" |
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26 | +#include "dev-eth.h" |
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27 | #include "dev-gpio-buttons.h" |
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28 | #include "dev-leds-gpio.h" |
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29 | +#include "dev-m25p80.h" |
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30 | +#include "dev-nfc.h" |
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31 | #include "dev-spi.h" |
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32 | #include "dev-usb.h" |
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33 | #include "dev-wmac.h" |
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34 | -#include "pci.h" |
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35 | +#include "machtypes.h" |
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36 | |||
37 | +#define DB120_GPIO_LED_USB 11 |
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38 | #define DB120_GPIO_LED_WLAN_5G 12 |
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39 | #define DB120_GPIO_LED_WLAN_2G 13 |
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40 | #define DB120_GPIO_LED_STATUS 14 |
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41 | @@ -39,8 +49,10 @@ |
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42 | #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ |
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43 | #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) |
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44 | |||
45 | -#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
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46 | -#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
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47 | +#define DB120_MAC0_OFFSET 0 |
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48 | +#define DB120_MAC1_OFFSET 6 |
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49 | +#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
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50 | +#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
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51 | |||
52 | static struct gpio_led db120_leds_gpio[] __initdata = { |
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53 | { |
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54 | @@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] |
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55 | .gpio = DB120_GPIO_LED_WLAN_2G, |
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56 | .active_low = 1, |
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57 | }, |
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58 | + { |
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59 | + .name = "db120:green:usb", |
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60 | + .gpio = DB120_GPIO_LED_USB, |
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61 | + .active_low = 1, |
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62 | + } |
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63 | }; |
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64 | |||
65 | static struct gpio_keys_button db120_gpio_keys[] __initdata = { |
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66 | @@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi |
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67 | }, |
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68 | }; |
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69 | |||
70 | -static struct spi_board_info db120_spi_info[] = { |
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71 | - { |
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72 | - .bus_num = 0, |
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73 | - .chip_select = 0, |
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74 | - .max_speed_hz = 25000000, |
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75 | - .modalias = "s25sl064a", |
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76 | - } |
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77 | +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { |
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78 | + .mode = AR8327_PAD_MAC_RGMII, |
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79 | + .txclk_delay_en = true, |
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80 | + .rxclk_delay_en = true, |
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81 | + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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82 | + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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83 | }; |
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84 | |||
85 | -static struct ath79_spi_platform_data db120_spi_data = { |
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86 | - .bus_num = 0, |
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87 | - .num_chipselect = 1, |
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88 | +static struct ar8327_led_cfg db120_ar8327_led_cfg = { |
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89 | + .led_ctrl0 = 0x00000000, |
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90 | + .led_ctrl1 = 0xc737c737, |
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91 | + .led_ctrl2 = 0x00000000, |
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92 | + .led_ctrl3 = 0x00c30c00, |
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93 | + .open_drain = true, |
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94 | }; |
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95 | |||
96 | -#ifdef CONFIG_PCI |
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97 | -static struct ath9k_platform_data db120_ath9k_data; |
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98 | - |
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99 | -static int db120_pci_plat_dev_init(struct pci_dev *dev) |
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100 | -{ |
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101 | - switch (PCI_SLOT(dev->devfn)) { |
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102 | - case 0: |
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103 | - dev->dev.platform_data = &db120_ath9k_data; |
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104 | - break; |
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105 | - } |
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106 | - |
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107 | - return 0; |
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108 | -} |
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109 | - |
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110 | -static void __init db120_pci_init(u8 *eeprom) |
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111 | -{ |
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112 | - memcpy(db120_ath9k_data.eeprom_data, eeprom, |
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113 | - sizeof(db120_ath9k_data.eeprom_data)); |
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114 | +static struct ar8327_platform_data db120_ar8327_data = { |
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115 | + .pad0_cfg = &db120_ar8327_pad0_cfg, |
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116 | + .port0_cfg = { |
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117 | + .force_link = 1, |
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118 | + .speed = AR8327_PORT_SPEED_1000, |
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119 | + .duplex = 1, |
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120 | + .txpause = 1, |
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121 | + .rxpause = 1, |
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122 | + }, |
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123 | + .led_cfg = &db120_ar8327_led_cfg, |
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124 | +}; |
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125 | |||
126 | - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); |
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127 | - ath79_register_pci(); |
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128 | -} |
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129 | -#else |
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130 | -static inline void db120_pci_init(u8 *eeprom) {} |
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131 | -#endif /* CONFIG_PCI */ |
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132 | +static struct mdio_board_info db120_mdio0_info[] = { |
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133 | + { |
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134 | + .bus_id = "ag71xx-mdio.0", |
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135 | + .mdio_addr = 0, |
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136 | + .platform_data = &db120_ar8327_data, |
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137 | + }, |
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138 | +}; |
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139 | |||
140 | static void __init db120_setup(void) |
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141 | { |
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142 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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143 | |||
144 | + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); |
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145 | + ath79_register_m25p80(NULL); |
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146 | + |
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147 | ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), |
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148 | db120_leds_gpio); |
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149 | ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, |
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150 | ARRAY_SIZE(db120_gpio_keys), |
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151 | db120_gpio_keys); |
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152 | - ath79_register_spi(&db120_spi_data, db120_spi_info, |
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153 | - ARRAY_SIZE(db120_spi_info)); |
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154 | ath79_register_usb(); |
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155 | ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); |
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156 | - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); |
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157 | + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); |
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158 | + |
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159 | + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | |
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160 | + AR934X_ETH_CFG_SW_ONLY_MODE); |
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161 | + |
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162 | + ath79_register_mdio(1, 0x0); |
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163 | + ath79_register_mdio(0, 0x0); |
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164 | + |
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165 | + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); |
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166 | + |
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167 | + mdiobus_register_board_info(db120_mdio0_info, |
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168 | + ARRAY_SIZE(db120_mdio0_info)); |
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169 | + |
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170 | + /* GMAC0 is connected to an AR8327 switch */ |
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171 | + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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172 | + ath79_eth0_data.phy_mask = BIT(0); |
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173 | + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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174 | + ath79_eth0_pll_data.pll_1000 = 0x06000000; |
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175 | + ath79_register_eth(0); |
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176 | + |
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177 | + /* GMAC1 is connected to the internal switch */ |
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178 | + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); |
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179 | + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
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180 | + ath79_eth1_data.speed = SPEED_1000; |
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181 | + ath79_eth1_data.duplex = DUPLEX_FULL; |
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182 | + |
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183 | + ath79_register_eth(1); |
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184 | + |
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185 | + ath79_register_nfc(); |
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186 | } |
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187 | |||
188 | MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", |
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189 | --- a/arch/mips/ath79/Kconfig |
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190 | +++ b/arch/mips/ath79/Kconfig |
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191 | @@ -43,9 +43,12 @@ config ATH79_MACH_AP81 |
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192 | config ATH79_MACH_DB120 |
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193 | bool "Atheros DB120 reference board" |
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194 | select SOC_AR934X |
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195 | + select ATH79_DEV_AP9X_PCI if PCI |
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196 | + select ATH79_DEV_ETH |
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197 | select ATH79_DEV_GPIO_BUTTONS |
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198 | select ATH79_DEV_LEDS_GPIO |
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199 | - select ATH79_DEV_SPI |
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200 | + select ATH79_DEV_M25P80 |
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201 | + select ATH79_DEV_NFC |
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202 | select ATH79_DEV_USB |
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203 | select ATH79_DEV_WMAC |
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204 | help |