OpenWrt – Blame information for rev 1
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1 | office | 1 | /* |
2 | * Cache operations for the cache instruction. |
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3 | * |
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4 | * This file is subject to the terms and conditions of the GNU General Public |
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5 | * License. See the file "COPYING" in the main directory of this archive |
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6 | * for more details. |
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7 | * |
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8 | * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle |
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9 | * (C) Copyright 1999 Silicon Graphics, Inc. |
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10 | */ |
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11 | #ifndef __ASM_CACHEOPS_H |
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12 | #define __ASM_CACHEOPS_H |
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13 | |||
14 | /* |
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15 | * Cache Operations available on all MIPS processors with R4000-style caches |
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16 | */ |
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17 | #define Index_Invalidate_I 0x00 |
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18 | #define Index_Writeback_Inv_D 0x01 |
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19 | #define Index_Load_Tag_I 0x04 |
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20 | #define Index_Load_Tag_D 0x05 |
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21 | #define Index_Store_Tag_I 0x08 |
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22 | #define Index_Store_Tag_D 0x09 |
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23 | #if defined(CONFIG_CPU_LOONGSON2) |
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24 | #define Hit_Invalidate_I 0x00 |
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25 | #else |
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26 | #define Hit_Invalidate_I 0x10 |
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27 | #endif |
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28 | #define Hit_Invalidate_D 0x11 |
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29 | #define Hit_Writeback_Inv_D 0x15 |
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30 | |||
31 | /* |
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32 | * R4000-specific cacheops |
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33 | */ |
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34 | #define Create_Dirty_Excl_D 0x0d |
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35 | #define Fill 0x14 |
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36 | #define Hit_Writeback_I 0x18 |
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37 | #define Hit_Writeback_D 0x19 |
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38 | |||
39 | /* |
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40 | * R4000SC and R4400SC-specific cacheops |
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41 | */ |
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42 | #define Index_Invalidate_SI 0x02 |
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43 | #define Index_Writeback_Inv_SD 0x03 |
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44 | #define Index_Load_Tag_SI 0x06 |
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45 | #define Index_Load_Tag_SD 0x07 |
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46 | #define Index_Store_Tag_SI 0x0A |
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47 | #define Index_Store_Tag_SD 0x0B |
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48 | #define Create_Dirty_Excl_SD 0x0f |
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49 | #define Hit_Invalidate_SI 0x12 |
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50 | #define Hit_Invalidate_SD 0x13 |
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51 | #define Hit_Writeback_Inv_SD 0x17 |
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52 | #define Hit_Writeback_SD 0x1b |
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53 | #define Hit_Set_Virtual_SI 0x1e |
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54 | #define Hit_Set_Virtual_SD 0x1f |
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55 | |||
56 | /* |
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57 | * R5000-specific cacheops |
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58 | */ |
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59 | #define R5K_Page_Invalidate_S 0x17 |
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60 | |||
61 | /* |
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62 | * RM7000-specific cacheops |
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63 | */ |
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64 | #define Page_Invalidate_T 0x16 |
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65 | |||
66 | /* |
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67 | * R10000-specific cacheops |
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68 | * |
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69 | * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. |
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70 | * Most of the _S cacheops are identical to the R4000SC _SD cacheops. |
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71 | */ |
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72 | #define Index_Writeback_Inv_S 0x03 |
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73 | #define Index_Load_Tag_S 0x07 |
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74 | #define Index_Store_Tag_S 0x0B |
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75 | #define Hit_Invalidate_S 0x13 |
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76 | #define Cache_Barrier 0x14 |
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77 | #define Hit_Writeback_Inv_S 0x17 |
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78 | #define Index_Load_Data_I 0x18 |
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79 | #define Index_Load_Data_D 0x19 |
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80 | #define Index_Load_Data_S 0x1b |
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81 | #define Index_Store_Data_I 0x1c |
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82 | #define Index_Store_Data_D 0x1d |
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83 | #define Index_Store_Data_S 0x1f |
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84 | |||
85 | #endif /* __ASM_CACHEOPS_H */ |