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1 office 1 /*
2 * NAND flash driver for the MikroTik RouterBOARD 91x series
3 *
4 * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10  
11 #include <linux/version.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/module.h>
15 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
16 #include <linux/mtd/nand.h>
17 #else
18 #include <linux/mtd/rawnand.h>
19 #endif
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_data/rb91x_nand.h>
27  
28 #include <asm/mach-ath79/ar71xx_regs.h>
29 #include <asm/mach-ath79/ath79.h>
30  
31 #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
32  
33 #define RB91X_NAND_NRWE BIT(12)
34  
35 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
36 BIT(13) | BIT(14) | BIT(15))
37  
38 #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
39 #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
40  
41 #define RB91X_NAND_LOW_DATA_MASK 0x1f
42 #define RB91X_NAND_HIGH_DATA_MASK 0xe0
43 #define RB91X_NAND_HIGH_DATA_SHIFT 8
44  
45 struct rb91x_nand_info {
46 struct nand_chip chip;
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
48 struct mtd_info mtd;
49 #endif
50 struct device *dev;
51  
52 int gpio_nce;
53 int gpio_ale;
54 int gpio_cle;
55 int gpio_rdy;
56 int gpio_read;
57 int gpio_nrw;
58 int gpio_nle;
59 };
60  
61 static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
62 {
63 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
64 return container_of(mtd, struct rb91x_nand_info, mtd);
65 #else
66 struct nand_chip *chip = mtd_to_nand(mtd);
67  
68 return container_of(chip, struct rb91x_nand_info, chip);
69 #endif
70 }
71  
72 static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc)
73 {
74 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
75 return &nfc->mtd;
76 #else
77 return nand_to_mtd(&nfc->chip);
78 #endif
79 }
80  
81  
82 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
83 /*
84 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
85 * will not be able to find the kernel that we load.
86 */
87 static struct nand_ecclayout rb91x_nand_ecclayout = {
88 .eccbytes = 6,
89 .eccpos = { 8, 9, 10, 13, 14, 15 },
90 .oobavail = 9,
91 .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
92 };
93  
94 #else
95  
96 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
97 struct mtd_oob_region *oobregion)
98 {
99 switch (section) {
100 case 0:
101 oobregion->offset = 8;
102 oobregion->length = 3;
103 return 0;
104 case 1:
105 oobregion->offset = 13;
106 oobregion->length = 3;
107 return 0;
108 default:
109 return -ERANGE;
110 }
111 }
112  
113 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
114 struct mtd_oob_region *oobregion)
115 {
116 switch (section) {
117 case 0:
118 oobregion->offset = 0;
119 oobregion->length = 4;
120 return 0;
121 case 1:
122 oobregion->offset = 4;
123 oobregion->length = 1;
124 return 0;
125 case 2:
126 oobregion->offset = 6;
127 oobregion->length = 2;
128 return 0;
129 case 3:
130 oobregion->offset = 11;
131 oobregion->length = 2;
132 return 0;
133 default:
134 return -ERANGE;
135 }
136 }
137  
138 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
139 .ecc = rb91x_ooblayout_ecc,
140 .free = rb91x_ooblayout_free,
141 };
142 #endif /* < 4.6 */
143  
144 static struct mtd_partition rb91x_nand_partitions[] = {
145 {
146 .name = "booter",
147 .offset = 0,
148 .size = (256 * 1024),
149 .mask_flags = MTD_WRITEABLE,
150 }, {
151 .name = "kernel",
152 .offset = (256 * 1024),
153 .size = (4 * 1024 * 1024) - (256 * 1024),
154 }, {
155 .name = "ubi",
156 .offset = MTDPART_OFS_NXTBLK,
157 .size = MTDPART_SIZ_FULL,
158 },
159 };
160  
161 static void rb91x_nand_write(struct rb91x_nand_info *rbni,
162 const u8 *buf,
163 unsigned len)
164 {
165 void __iomem *base = ath79_gpio_base;
166 u32 oe_reg;
167 u32 out_reg;
168 u32 out;
169 unsigned i;
170  
171 /* enable the latch */
172 gpio_set_value_cansleep(rbni->gpio_nle, 0);
173  
174 oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
175 out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
176  
177 /* set data lines to output mode */
178 __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
179 base + AR71XX_GPIO_REG_OE);
180  
181 out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
182 for (i = 0; i != len; i++) {
183 u32 data;
184  
185 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
186 RB91X_NAND_HIGH_DATA_SHIFT;
187 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
188 data |= out;
189 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
190  
191 /* deactivate WE line */
192 data |= RB91X_NAND_NRWE;
193 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
194 /* flush write */
195 __raw_readl(base + AR71XX_GPIO_REG_OUT);
196 }
197  
198 /* restore registers */
199 __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
200 __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
201 /* flush write */
202 __raw_readl(base + AR71XX_GPIO_REG_OUT);
203  
204 /* disable the latch */
205 gpio_set_value_cansleep(rbni->gpio_nle, 1);
206 }
207  
208 static void rb91x_nand_read(struct rb91x_nand_info *rbni,
209 u8 *read_buf,
210 unsigned len)
211 {
212 void __iomem *base = ath79_gpio_base;
213 u32 oe_reg;
214 u32 out_reg;
215 unsigned i;
216  
217 /* enable read mode */
218 gpio_set_value_cansleep(rbni->gpio_read, 1);
219  
220 /* enable latch */
221 gpio_set_value_cansleep(rbni->gpio_nle, 0);
222  
223 /* save registers */
224 oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
225 out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
226  
227 /* set data lines to input mode */
228 __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
229 base + AR71XX_GPIO_REG_OE);
230  
231 for (i = 0; i < len; i++) {
232 u32 in;
233 u8 data;
234  
235 /* activate RE line */
236 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
237 /* flush write */
238 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
239  
240 /* read input lines */
241 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
242  
243 /* deactivate RE line */
244 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
245  
246 data = (in & RB91X_NAND_LOW_DATA_MASK);
247 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
248 RB91X_NAND_HIGH_DATA_MASK;
249  
250 read_buf[i] = data;
251 }
252  
253 /* restore registers */
254 __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
255 __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
256 /* flush write */
257 __raw_readl(base + AR71XX_GPIO_REG_OUT);
258  
259 /* disable latch */
260 gpio_set_value_cansleep(rbni->gpio_nle, 1);
261  
262 /* disable read mode */
263 gpio_set_value_cansleep(rbni->gpio_read, 0);
264 }
265  
266 static int rb91x_nand_dev_ready(struct mtd_info *mtd)
267 {
268 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
269  
270 return gpio_get_value_cansleep(rbni->gpio_rdy);
271 }
272  
273 static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
274 unsigned int ctrl)
275 {
276 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
277  
278 if (ctrl & NAND_CTRL_CHANGE) {
279 gpio_set_value_cansleep(rbni->gpio_cle,
280 (ctrl & NAND_CLE) ? 1 : 0);
281 gpio_set_value_cansleep(rbni->gpio_ale,
282 (ctrl & NAND_ALE) ? 1 : 0);
283 gpio_set_value_cansleep(rbni->gpio_nce,
284 (ctrl & NAND_NCE) ? 0 : 1);
285 }
286  
287 if (cmd != NAND_CMD_NONE) {
288 u8 t = cmd;
289  
290 rb91x_nand_write(rbni, &t, 1);
291 }
292 }
293  
294 static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
295 {
296 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
297 u8 data = 0xff;
298  
299 rb91x_nand_read(rbni, &data, 1);
300  
301 return data;
302 }
303  
304 static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
305 {
306 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
307  
308 rb91x_nand_read(rbni, buf, len);
309 }
310  
311 static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
312 {
313 struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
314  
315 rb91x_nand_write(rbni, buf, len);
316 }
317  
318 static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
319 {
320 int ret;
321  
322 /*
323 * Ensure that the LATCH is disabled before initializing
324 * control lines.
325 */
326 ret = devm_gpio_request_one(info->dev, info->gpio_nle,
327 GPIOF_OUT_INIT_HIGH, "LATCH enable");
328 if (ret)
329 return ret;
330  
331 ret = devm_gpio_request_one(info->dev, info->gpio_nce,
332 GPIOF_OUT_INIT_HIGH, "NAND nCE");
333 if (ret)
334 return ret;
335  
336 ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
337 GPIOF_OUT_INIT_HIGH, "NAND nRW");
338 if (ret)
339 return ret;
340  
341 ret = devm_gpio_request_one(info->dev, info->gpio_cle,
342 GPIOF_OUT_INIT_LOW, "NAND CLE");
343 if (ret)
344 return ret;
345  
346 ret = devm_gpio_request_one(info->dev, info->gpio_ale,
347 GPIOF_OUT_INIT_LOW, "NAND ALE");
348 if (ret)
349 return ret;
350  
351 ret = devm_gpio_request_one(info->dev, info->gpio_read,
352 GPIOF_OUT_INIT_LOW, "NAND READ");
353 if (ret)
354 return ret;
355  
356 ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
357 GPIOF_IN, "NAND RDY");
358 return ret;
359 }
360  
361 static int rb91x_nand_probe(struct platform_device *pdev)
362 {
363 struct rb91x_nand_info *rbni;
364 struct rb91x_nand_platform_data *pdata;
365 struct mtd_info *mtd;
366 int ret;
367  
368 pr_info(DRV_DESC "\n");
369  
370 pdata = dev_get_platdata(&pdev->dev);
371 if (!pdata)
372 return -EINVAL;
373  
374 rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
375 if (!rbni)
376 return -ENOMEM;
377  
378 rbni->dev = &pdev->dev;
379 rbni->gpio_nce = pdata->gpio_nce;
380 rbni->gpio_ale = pdata->gpio_ale;
381 rbni->gpio_cle = pdata->gpio_cle;
382 rbni->gpio_read = pdata->gpio_read;
383 rbni->gpio_nrw = pdata->gpio_nrw;
384 rbni->gpio_rdy = pdata->gpio_rdy;
385 rbni->gpio_nle = pdata->gpio_nle;
386  
387 rbni->chip.priv = &rbni;
388 mtd = rbinfo_to_mtd(rbni);
389  
390 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
391 mtd->priv = &rbni->chip;
392 #endif
393 mtd->owner = THIS_MODULE;
394  
395 rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl;
396 rbni->chip.dev_ready = rb91x_nand_dev_ready;
397 rbni->chip.read_byte = rb91x_nand_read_byte;
398 rbni->chip.write_buf = rb91x_nand_write_buf;
399 rbni->chip.read_buf = rb91x_nand_read_buf;
400  
401 rbni->chip.chip_delay = 25;
402 rbni->chip.ecc.mode = NAND_ECC_SOFT;
403 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
404 rbni->chip.ecc.algo = NAND_ECC_HAMMING;
405 #endif
406 rbni->chip.options = NAND_NO_SUBPAGE_WRITE;
407  
408 platform_set_drvdata(pdev, rbni);
409  
410 ret = rb91x_nand_gpio_init(rbni);
411 if (ret)
412 return ret;
413  
414 ret = nand_scan_ident(mtd, 1, NULL);
415 if (ret)
416 return ret;
417  
418 if (mtd->writesize == 512)
419 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
420 rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
421 #else
422 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
423 #endif
424  
425 ret = nand_scan_tail(mtd);
426 if (ret)
427 return ret;
428  
429 ret = mtd_device_register(mtd, rb91x_nand_partitions,
430 ARRAY_SIZE(rb91x_nand_partitions));
431 if (ret)
432 goto err_release_nand;
433  
434 return 0;
435  
436 err_release_nand:
437 nand_release(mtd);
438 return ret;
439 }
440  
441 static int rb91x_nand_remove(struct platform_device *pdev)
442 {
443 struct rb91x_nand_info *info = platform_get_drvdata(pdev);
444  
445 nand_release(rbinfo_to_mtd(info));
446  
447 return 0;
448 }
449  
450 static struct platform_driver rb91x_nand_driver = {
451 .probe = rb91x_nand_probe,
452 .remove = rb91x_nand_remove,
453 .driver = {
454 .name = RB91X_NAND_DRIVER_NAME,
455 .owner = THIS_MODULE,
456 },
457 };
458  
459 module_platform_driver(rb91x_nand_driver);
460  
461 MODULE_DESCRIPTION(DRV_DESC);
462 MODULE_VERSION(DRV_VERSION);
463 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
464 MODULE_LICENSE("GPL v2");