OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * MikroTik RouterBOARD 91X support |
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3 | * |
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4 | * Copyright (C) 2015 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU General Public License version 2 as published |
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8 | * by the Free Software Foundation. |
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9 | */ |
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10 | |||
11 | #include <linux/version.h> |
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12 | #include <linux/phy.h> |
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13 | #include <linux/delay.h> |
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14 | #include <linux/platform_device.h> |
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15 | #include <linux/ath9k_platform.h> |
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16 | #include <linux/mtd/mtd.h> |
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17 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) |
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18 | #include <linux/mtd/nand.h> |
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19 | #else |
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20 | #include <linux/mtd/rawnand.h> |
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21 | #endif |
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22 | #include <linux/mtd/partitions.h> |
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23 | #include <linux/spi/spi.h> |
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24 | #include <linux/spi/flash.h> |
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25 | #include <linux/routerboot.h> |
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26 | #include <linux/gpio.h> |
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27 | #include <linux/platform_data/phy-at803x.h> |
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28 | #include <linux/version.h> |
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29 | |||
30 | #include <asm/prom.h> |
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31 | #include <asm/mach-ath79/ath79.h> |
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32 | #include <asm/mach-ath79/ar71xx_regs.h> |
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33 | |||
34 | #include "common.h" |
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35 | #include "dev-gpio-buttons.h" |
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36 | #include "dev-eth.h" |
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37 | #include "dev-leds-gpio.h" |
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38 | #include "dev-m25p80.h" |
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39 | #include "dev-nfc.h" |
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40 | #include "dev-usb.h" |
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41 | #include "dev-spi.h" |
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42 | #include "machtypes.h" |
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43 | #include "pci.h" |
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44 | #include "routerboot.h" |
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45 | |||
46 | #define RB922_GPIO_LED_USR 12 |
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47 | #define RB922_GPIO_USB_POWER 13 |
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48 | #define RB922_GPIO_FAN_CTRL 14 |
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49 | #define RB922_GPIO_BTN_RESET 20 |
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50 | #define RB922_GPIO_NAND_NCE 23 |
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51 | |||
52 | #define RB922_PHY_ADDR 4 |
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53 | |||
54 | #define RB922_KEYS_POLL_INTERVAL 20 /* msecs */ |
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55 | #define RB922_KEYS_DEBOUNCE_INTERVAL (3 * RB922_KEYS_POLL_INTERVAL) |
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56 | |||
57 | #define RB_ROUTERBOOT_OFFSET 0x0000 |
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58 | #define RB_ROUTERBOOT_MIN_SIZE 0xb000 |
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59 | #define RB_HARD_CFG_SIZE 0x1000 |
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60 | #define RB_BIOS_OFFSET 0xd000 |
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61 | #define RB_BIOS_SIZE 0x1000 |
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62 | #define RB_SOFT_CFG_OFFSET 0xf000 |
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63 | #define RB_SOFT_CFG_SIZE 0x1000 |
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64 | |||
65 | static struct mtd_partition rb922gs_spi_partitions[] = { |
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66 | { |
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67 | .name = "routerboot", |
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68 | .offset = RB_ROUTERBOOT_OFFSET, |
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69 | .mask_flags = MTD_WRITEABLE, |
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70 | }, { |
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71 | .name = "hard_config", |
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72 | .size = RB_HARD_CFG_SIZE, |
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73 | .mask_flags = MTD_WRITEABLE, |
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74 | }, { |
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75 | .name = "bios", |
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76 | .offset = RB_BIOS_OFFSET, |
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77 | .size = RB_BIOS_SIZE, |
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78 | .mask_flags = MTD_WRITEABLE, |
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79 | }, { |
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80 | .name = "soft_config", |
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81 | .size = RB_SOFT_CFG_SIZE, |
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82 | } |
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83 | }; |
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84 | |||
85 | static struct flash_platform_data rb922gs_spi_flash_data = { |
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86 | .parts = rb922gs_spi_partitions, |
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87 | .nr_parts = ARRAY_SIZE(rb922gs_spi_partitions), |
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88 | }; |
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89 | |||
90 | static struct gpio_led rb922gs_leds[] __initdata = { |
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91 | { |
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92 | .name = "rb:green:user", |
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93 | .gpio = RB922_GPIO_LED_USR, |
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94 | .active_low = 1, |
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95 | }, |
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96 | }; |
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97 | |||
98 | static struct gpio_keys_button rb922gs_gpio_keys[] __initdata = { |
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99 | { |
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100 | .desc = "Reset button", |
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101 | .type = EV_KEY, |
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102 | .code = KEY_RESTART, |
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103 | .debounce_interval = RB922_KEYS_DEBOUNCE_INTERVAL, |
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104 | .gpio = RB922_GPIO_BTN_RESET, |
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105 | .active_low = 1, |
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106 | }, |
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107 | }; |
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108 | |||
109 | static struct at803x_platform_data rb922gs_at803x_data = { |
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110 | .disable_smarteee = 1, |
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111 | }; |
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112 | |||
113 | static struct mdio_board_info rb922gs_mdio0_info[] = { |
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114 | { |
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115 | .bus_id = "ag71xx-mdio.0", |
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116 | .mdio_addr = RB922_PHY_ADDR, |
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117 | .platform_data = &rb922gs_at803x_data, |
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118 | }, |
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119 | }; |
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120 | |||
121 | static void __init rb922gs_init_partitions(const struct rb_info *info) |
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122 | { |
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123 | rb922gs_spi_partitions[0].size = info->hard_cfg_offs; |
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124 | rb922gs_spi_partitions[1].offset = info->hard_cfg_offs; |
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125 | rb922gs_spi_partitions[3].offset = info->soft_cfg_offs; |
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126 | } |
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127 | |||
128 | static void rb922gs_nand_select_chip(int chip_no) |
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129 | { |
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130 | switch (chip_no) { |
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131 | case 0: |
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132 | gpio_set_value(RB922_GPIO_NAND_NCE, 0); |
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133 | break; |
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134 | default: |
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135 | gpio_set_value(RB922_GPIO_NAND_NCE, 1); |
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136 | break; |
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137 | } |
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138 | ndelay(500); |
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139 | } |
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140 | |||
141 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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142 | static struct nand_ecclayout rb922gs_nand_ecclayout = { |
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143 | .eccbytes = 6, |
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144 | .eccpos = { 8, 9, 10, 13, 14, 15 }, |
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145 | .oobavail = 9, |
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146 | .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } |
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147 | }; |
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148 | |||
149 | #else |
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150 | |||
151 | static int rb922gs_ooblayout_ecc(struct mtd_info *mtd, int section, |
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152 | struct mtd_oob_region *oobregion) |
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153 | { |
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154 | switch (section) { |
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155 | case 0: |
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156 | oobregion->offset = 8; |
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157 | oobregion->length = 3; |
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158 | return 0; |
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159 | case 1: |
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160 | oobregion->offset = 13; |
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161 | oobregion->length = 3; |
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162 | return 0; |
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163 | default: |
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164 | return -ERANGE; |
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165 | } |
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166 | } |
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167 | |||
168 | static int rb922gs_ooblayout_free(struct mtd_info *mtd, int section, |
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169 | struct mtd_oob_region *oobregion) |
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170 | { |
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171 | switch (section) { |
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172 | case 0: |
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173 | oobregion->offset = 0; |
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174 | oobregion->length = 4; |
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175 | return 0; |
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176 | case 1: |
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177 | oobregion->offset = 4; |
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178 | oobregion->length = 1; |
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179 | return 0; |
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180 | case 2: |
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181 | oobregion->offset = 6; |
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182 | oobregion->length = 2; |
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183 | return 0; |
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184 | case 3: |
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185 | oobregion->offset = 11; |
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186 | oobregion->length = 2; |
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187 | return 0; |
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188 | default: |
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189 | return -ERANGE; |
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190 | } |
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191 | } |
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192 | |||
193 | static const struct mtd_ooblayout_ops rb922gs_nand_ecclayout_ops = { |
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194 | .ecc = rb922gs_ooblayout_ecc, |
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195 | .free = rb922gs_ooblayout_free, |
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196 | }; |
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197 | #endif /* < 4.6 */ |
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198 | |||
199 | static int rb922gs_nand_scan_fixup(struct mtd_info *mtd) |
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200 | { |
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201 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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202 | struct nand_chip *chip = mtd->priv; |
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203 | #else |
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204 | struct nand_chip *chip = mtd_to_nand(mtd); |
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205 | #endif /* < 4.6.0 */ |
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206 | |||
207 | if (mtd->writesize == 512) { |
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208 | /* |
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209 | * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot |
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210 | * will not be able to find the kernel that we load. |
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211 | */ |
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212 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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213 | chip->ecc.layout = &rb922gs_nand_ecclayout; |
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214 | #else |
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215 | mtd_set_ooblayout(mtd, &rb922gs_nand_ecclayout_ops); |
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216 | #endif |
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217 | } |
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218 | |||
219 | chip->options = NAND_NO_SUBPAGE_WRITE; |
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220 | |||
221 | return 0; |
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222 | } |
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223 | |||
224 | static struct mtd_partition rb922gs_nand_partitions[] = { |
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225 | { |
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226 | .name = "booter", |
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227 | .offset = 0, |
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228 | .size = (256 * 1024), |
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229 | .mask_flags = MTD_WRITEABLE, |
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230 | }, |
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231 | { |
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232 | .name = "kernel", |
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233 | .offset = (256 * 1024), |
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234 | .size = (4 * 1024 * 1024) - (256 * 1024), |
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235 | }, |
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236 | { |
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237 | .name = "ubi", |
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238 | .offset = MTDPART_OFS_NXTBLK, |
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239 | .size = MTDPART_SIZ_FULL, |
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240 | }, |
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241 | }; |
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242 | |||
243 | static void __init rb922gs_nand_init(void) |
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244 | { |
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245 | gpio_request_one(RB922_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); |
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246 | |||
247 | ath79_nfc_set_scan_fixup(rb922gs_nand_scan_fixup); |
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248 | ath79_nfc_set_parts(rb922gs_nand_partitions, |
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249 | ARRAY_SIZE(rb922gs_nand_partitions)); |
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250 | ath79_nfc_set_select_chip(rb922gs_nand_select_chip); |
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251 | ath79_nfc_set_swap_dma(true); |
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252 | ath79_register_nfc(); |
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253 | } |
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254 | |||
255 | static void __init rb922gs_setup(void) |
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256 | { |
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257 | const struct rb_info *info; |
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258 | char buf[64]; |
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259 | |||
260 | info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); |
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261 | if (!info) |
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262 | return; |
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263 | |||
264 | scnprintf(buf, sizeof(buf), "MikroTik RouterBOARD %s", |
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265 | (info->board_name) ? info->board_name : ""); |
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266 | mips_set_machine_name(buf); |
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267 | |||
268 | rb922gs_init_partitions(info); |
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269 | ath79_register_m25p80(&rb922gs_spi_flash_data); |
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270 | |||
271 | rb922gs_nand_init(); |
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272 | |||
273 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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274 | |||
275 | ath79_register_mdio(0, 0x0); |
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276 | |||
277 | mdiobus_register_board_info(rb922gs_mdio0_info, |
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278 | ARRAY_SIZE(rb922gs_mdio0_info)); |
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279 | |||
280 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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281 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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282 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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283 | ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR); |
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284 | if (strcmp(info->board_name, "921GS-5HPacD r2") == 0) { |
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285 | ath79_eth0_pll_data.pll_10 = 0xa0001313; |
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286 | ath79_eth0_pll_data.pll_100 = 0xa0000101; |
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287 | ath79_eth0_pll_data.pll_1000 = 0x8f000000; |
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288 | } |
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289 | else { |
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290 | ath79_eth0_pll_data.pll_10 = 0x81001313; |
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291 | ath79_eth0_pll_data.pll_100 = 0x81000101; |
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292 | ath79_eth0_pll_data.pll_1000 = 0x8f000000; |
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293 | } |
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294 | |||
295 | ath79_register_eth(0); |
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296 | |||
297 | ath79_register_pci(); |
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298 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds); |
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299 | ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL, |
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300 | ARRAY_SIZE(rb922gs_gpio_keys), |
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301 | rb922gs_gpio_keys); |
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302 | |||
303 | /* NOTE: |
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304 | * This only supports the RB911G-5HPacD board for now. For other boards |
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305 | * more devices must be registered based on the hardware options which |
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306 | * can be found in the hardware configuration of RouterBOOT. |
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307 | */ |
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308 | } |
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309 | |||
310 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_922GS, "922gs", rb922gs_setup); |