OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * MikroTik RouterBOARD 4xx series support |
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3 | * |
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4 | * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #include <linux/platform_device.h> |
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13 | #include <linux/irq.h> |
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14 | #include <linux/platform_data/mdio-gpio.h> |
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15 | #include <linux/mmc/host.h> |
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16 | #include <linux/spi/spi.h> |
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17 | #include <linux/spi/flash.h> |
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18 | #include <linux/spi/mmc_spi.h> |
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19 | #include <linux/mtd/mtd.h> |
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20 | #include <linux/mtd/partitions.h> |
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21 | |||
22 | #include <asm/mach-ath79/ar71xx_regs.h> |
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23 | #include <asm/mach-ath79/ath79.h> |
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24 | #include <asm/mach-ath79/rb4xx_cpld.h> |
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25 | |||
26 | #include "common.h" |
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27 | #include "dev-eth.h" |
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28 | #include "dev-gpio-buttons.h" |
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29 | #include "dev-leds-gpio.h" |
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30 | #include "dev-usb.h" |
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31 | #include "machtypes.h" |
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32 | #include "pci.h" |
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33 | |||
34 | #define RB4XX_GPIO_USER_LED 4 |
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35 | #define RB4XX_GPIO_RESET_SWITCH 7 |
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36 | |||
37 | #define RB4XX_GPIO_CPLD_BASE 32 |
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38 | #define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) |
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39 | #define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) |
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40 | #define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) |
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41 | #define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) |
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42 | #define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) |
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43 | |||
44 | #define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ |
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45 | #define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) |
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46 | |||
47 | static struct gpio_led rb4xx_leds_gpio[] __initdata = { |
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48 | { |
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49 | .name = "rb4xx:yellow:user", |
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50 | .gpio = RB4XX_GPIO_USER_LED, |
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51 | .active_low = 0, |
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52 | }, { |
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53 | .name = "rb4xx:green:led1", |
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54 | .gpio = RB4XX_GPIO_CPLD_LED1, |
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55 | .active_low = 1, |
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56 | }, { |
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57 | .name = "rb4xx:green:led2", |
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58 | .gpio = RB4XX_GPIO_CPLD_LED2, |
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59 | .active_low = 1, |
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60 | }, { |
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61 | .name = "rb4xx:green:led3", |
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62 | .gpio = RB4XX_GPIO_CPLD_LED3, |
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63 | .active_low = 1, |
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64 | }, { |
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65 | .name = "rb4xx:green:led4", |
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66 | .gpio = RB4XX_GPIO_CPLD_LED4, |
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67 | .active_low = 1, |
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68 | }, { |
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69 | .name = "rb4xx:green:led5", |
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70 | .gpio = RB4XX_GPIO_CPLD_LED5, |
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71 | .active_low = 0, |
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72 | }, |
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73 | }; |
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74 | |||
75 | static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { |
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76 | { |
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77 | .desc = "reset_switch", |
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78 | .type = EV_KEY, |
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79 | .code = KEY_RESTART, |
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80 | .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, |
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81 | .gpio = RB4XX_GPIO_RESET_SWITCH, |
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82 | .active_low = 1, |
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83 | } |
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84 | }; |
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85 | |||
86 | static struct platform_device rb4xx_nand_device = { |
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87 | .name = "rb4xx-nand", |
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88 | .id = -1, |
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89 | }; |
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90 | |||
91 | static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = { |
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92 | { |
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93 | .slot = 17, |
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94 | .pin = 1, |
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95 | .irq = ATH79_PCI_IRQ(2), |
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96 | }, { |
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97 | .slot = 18, |
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98 | .pin = 1, |
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99 | .irq = ATH79_PCI_IRQ(0), |
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100 | }, { |
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101 | .slot = 18, |
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102 | .pin = 2, |
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103 | .irq = ATH79_PCI_IRQ(1), |
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104 | }, { |
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105 | .slot = 19, |
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106 | .pin = 1, |
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107 | .irq = ATH79_PCI_IRQ(1), |
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108 | }, { |
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109 | .slot = 19, |
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110 | .pin = 2, |
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111 | .irq = ATH79_PCI_IRQ(2), |
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112 | }, { |
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113 | .slot = 20, |
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114 | .pin = 1, |
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115 | .irq = ATH79_PCI_IRQ(2), |
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116 | }, { |
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117 | .slot = 20, |
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118 | .pin = 2, |
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119 | .irq = ATH79_PCI_IRQ(0), |
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120 | }, { |
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121 | .slot = 21, |
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122 | .pin = 1, |
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123 | .irq = ATH79_PCI_IRQ(0), |
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124 | }, { |
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125 | .slot = 22, |
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126 | .pin = 1, |
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127 | .irq = ATH79_PCI_IRQ(1), |
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128 | }, { |
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129 | .slot = 22, |
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130 | .pin = 2, |
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131 | .irq = ATH79_PCI_IRQ(2), |
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132 | }, { |
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133 | .slot = 23, |
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134 | .pin = 1, |
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135 | .irq = ATH79_PCI_IRQ(2), |
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136 | }, { |
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137 | .slot = 23, |
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138 | .pin = 2, |
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139 | .irq = ATH79_PCI_IRQ(0), |
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140 | } |
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141 | }; |
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142 | |||
143 | static struct mtd_partition rb4xx_partitions[] = { |
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144 | { |
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145 | .name = "routerboot", |
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146 | .offset = 0, |
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147 | .size = 0x0b000, |
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148 | .mask_flags = MTD_WRITEABLE, |
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149 | }, { |
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150 | .name = "hard_config", |
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151 | .offset = 0x0b000, |
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152 | .size = 0x01000, |
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153 | .mask_flags = MTD_WRITEABLE, |
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154 | }, { |
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155 | .name = "bios", |
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156 | .offset = 0x0d000, |
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157 | .size = 0x02000, |
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158 | .mask_flags = MTD_WRITEABLE, |
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159 | }, { |
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160 | .name = "soft_config", |
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161 | .offset = 0x0f000, |
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162 | .size = 0x01000, |
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163 | } |
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164 | }; |
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165 | |||
166 | static struct flash_platform_data rb4xx_flash_data = { |
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167 | .type = "pm25lv512", |
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168 | .parts = rb4xx_partitions, |
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169 | .nr_parts = ARRAY_SIZE(rb4xx_partitions), |
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170 | }; |
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171 | |||
172 | static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { |
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173 | .gpio_base = RB4XX_GPIO_CPLD_BASE, |
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174 | }; |
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175 | |||
176 | static struct mmc_spi_platform_data rb4xx_mmc_data = { |
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177 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
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178 | }; |
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179 | |||
180 | static struct spi_board_info rb4xx_spi_info[] = { |
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181 | { |
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182 | .bus_num = 0, |
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183 | .chip_select = 0, |
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184 | .max_speed_hz = 25000000, |
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185 | .modalias = "m25p80", |
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186 | .platform_data = &rb4xx_flash_data, |
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187 | }, { |
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188 | .bus_num = 0, |
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189 | .chip_select = 1, |
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190 | .max_speed_hz = 25000000, |
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191 | .modalias = "spi-rb4xx-cpld", |
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192 | .platform_data = &rb4xx_cpld_data, |
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193 | } |
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194 | }; |
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195 | |||
196 | static struct spi_board_info rb4xx_microsd_info[] = { |
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197 | { |
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198 | .bus_num = 0, |
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199 | .chip_select = 2, |
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200 | .max_speed_hz = 25000000, |
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201 | .modalias = "mmc_spi", |
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202 | .platform_data = &rb4xx_mmc_data, |
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203 | } |
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204 | }; |
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205 | |||
206 | |||
207 | static struct resource rb4xx_spi_resources[] = { |
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208 | { |
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209 | .start = AR71XX_SPI_BASE, |
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210 | .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, |
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211 | .flags = IORESOURCE_MEM, |
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212 | }, |
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213 | }; |
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214 | |||
215 | static struct platform_device rb4xx_spi_device = { |
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216 | .name = "rb4xx-spi", |
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217 | .id = -1, |
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218 | .resource = rb4xx_spi_resources, |
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219 | .num_resources = ARRAY_SIZE(rb4xx_spi_resources), |
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220 | }; |
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221 | |||
222 | static void __init rb4xx_generic_setup(void) |
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223 | { |
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224 | ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | |
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225 | AR71XX_GPIO_FUNC_SPI_CS2_EN); |
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226 | |||
227 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), |
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228 | rb4xx_leds_gpio); |
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229 | |||
230 | ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, |
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231 | ARRAY_SIZE(rb4xx_gpio_keys), |
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232 | rb4xx_gpio_keys); |
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233 | |||
234 | spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); |
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235 | platform_device_register(&rb4xx_spi_device); |
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236 | platform_device_register(&rb4xx_nand_device); |
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237 | } |
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238 | |||
239 | static void __init rb411_setup(void) |
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240 | { |
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241 | rb4xx_generic_setup(); |
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242 | spi_register_board_info(rb4xx_microsd_info, |
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243 | ARRAY_SIZE(rb4xx_microsd_info)); |
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244 | |||
245 | ath79_register_mdio(0, 0xfffffffc); |
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246 | |||
247 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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248 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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249 | ath79_eth0_data.phy_mask = 0x00000003; |
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250 | |||
251 | ath79_register_eth(0); |
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252 | |||
253 | ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); |
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254 | ath79_register_pci(); |
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255 | } |
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256 | |||
257 | MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", |
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258 | rb411_setup); |
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259 | |||
260 | static void __init rb411u_setup(void) |
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261 | { |
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262 | rb411_setup(); |
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263 | ath79_register_usb(); |
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264 | } |
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265 | |||
266 | MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", |
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267 | rb411u_setup); |
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268 | |||
269 | #define RB433_LAN_PHYMASK BIT(0) |
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270 | #define RB433_WAN_PHYMASK BIT(4) |
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271 | #define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) |
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272 | |||
273 | static void __init rb433_setup(void) |
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274 | { |
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275 | rb4xx_generic_setup(); |
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276 | spi_register_board_info(rb4xx_microsd_info, |
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277 | ARRAY_SIZE(rb4xx_microsd_info)); |
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278 | |||
279 | ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); |
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280 | |||
281 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); |
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282 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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283 | ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; |
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284 | |||
285 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); |
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286 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
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287 | ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; |
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288 | |||
289 | ath79_register_eth(1); |
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290 | ath79_register_eth(0); |
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291 | |||
292 | ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); |
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293 | ath79_register_pci(); |
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294 | } |
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295 | |||
296 | MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", |
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297 | rb433_setup); |
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298 | |||
299 | static void __init rb433u_setup(void) |
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300 | { |
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301 | rb433_setup(); |
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302 | ath79_register_usb(); |
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303 | } |
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304 | |||
305 | MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", |
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306 | rb433u_setup); |
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307 | |||
308 | static void __init rb435g_setup(void) |
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309 | { |
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310 | rb4xx_generic_setup(); |
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311 | |||
312 | spi_register_board_info(rb4xx_microsd_info, |
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313 | ARRAY_SIZE(rb4xx_microsd_info)); |
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314 | |||
315 | ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); |
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316 | |||
317 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); |
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318 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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319 | ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; |
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320 | |||
321 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); |
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322 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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323 | ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; |
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324 | |||
325 | ath79_register_eth(1); |
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326 | ath79_register_eth(0); |
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327 | |||
328 | ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); |
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329 | ath79_register_pci(); |
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330 | |||
331 | ath79_register_usb(); |
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332 | } |
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333 | |||
334 | MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G", |
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335 | rb435g_setup); |
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336 | |||
337 | #define RB450_LAN_PHYMASK BIT(0) |
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338 | #define RB450_WAN_PHYMASK BIT(4) |
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339 | #define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) |
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340 | |||
341 | static void __init rb450_generic_setup(int gige) |
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342 | { |
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343 | rb4xx_generic_setup(); |
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344 | ath79_register_mdio(0, ~RB450_MDIO_PHYMASK); |
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345 | |||
346 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); |
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347 | ath79_eth0_data.phy_if_mode = (gige) ? |
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348 | PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; |
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349 | ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK; |
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350 | |||
351 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); |
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352 | ath79_eth1_data.phy_if_mode = (gige) ? |
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353 | PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; |
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354 | ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK; |
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355 | |||
356 | ath79_register_eth(1); |
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357 | ath79_register_eth(0); |
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358 | } |
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359 | |||
360 | static void __init rb450_setup(void) |
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361 | { |
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362 | rb450_generic_setup(0); |
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363 | } |
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364 | |||
365 | MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450", |
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366 | rb450_setup); |
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367 | |||
368 | static void __init rb450g_setup(void) |
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369 | { |
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370 | rb450_generic_setup(1); |
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371 | spi_register_board_info(rb4xx_microsd_info, |
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372 | ARRAY_SIZE(rb4xx_microsd_info)); |
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373 | } |
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374 | |||
375 | MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", |
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376 | rb450g_setup); |
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377 | |||
378 | static void __init rb493_setup(void) |
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379 | { |
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380 | rb4xx_generic_setup(); |
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381 | |||
382 | ath79_register_mdio(0, 0x3fffff00); |
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383 | |||
384 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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385 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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386 | ath79_eth0_data.speed = SPEED_100; |
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387 | ath79_eth0_data.duplex = DUPLEX_FULL; |
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388 | |||
389 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); |
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390 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
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391 | ath79_eth1_data.phy_mask = 0x00000001; |
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392 | |||
393 | ath79_register_eth(0); |
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394 | ath79_register_eth(1); |
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395 | |||
396 | ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); |
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397 | ath79_register_pci(); |
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398 | } |
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399 | |||
400 | MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", |
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401 | rb493_setup); |
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402 | |||
403 | #define RB493G_GPIO_MDIO_MDC 7 |
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404 | #define RB493G_GPIO_MDIO_DATA 8 |
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405 | |||
406 | #define RB493G_MDIO_PHYMASK BIT(0) |
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407 | |||
408 | static struct mdio_gpio_platform_data rb493g_mdio_data = { |
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409 | .mdc = RB493G_GPIO_MDIO_MDC, |
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410 | .mdio = RB493G_GPIO_MDIO_DATA, |
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411 | |||
412 | .phy_mask = ~RB493G_MDIO_PHYMASK, |
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413 | }; |
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414 | |||
415 | static struct platform_device rb493g_mdio_device = { |
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416 | .name = "mdio-gpio", |
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417 | .id = -1, |
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418 | .dev = { |
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419 | .platform_data = &rb493g_mdio_data, |
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420 | }, |
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421 | }; |
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422 | |||
423 | static void __init rb493g_setup(void) |
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424 | { |
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425 | ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | |
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426 | AR71XX_GPIO_FUNC_SPI_CS2_EN); |
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427 | |||
428 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), |
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429 | rb4xx_leds_gpio); |
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430 | |||
431 | spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); |
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432 | spi_register_board_info(rb4xx_microsd_info, |
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433 | ARRAY_SIZE(rb4xx_microsd_info)); |
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434 | |||
435 | platform_device_register(&rb4xx_spi_device); |
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436 | platform_device_register(&rb4xx_nand_device); |
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437 | |||
438 | ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK); |
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439 | |||
440 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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441 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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442 | ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK; |
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443 | ath79_eth0_data.speed = SPEED_1000; |
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444 | ath79_eth0_data.duplex = DUPLEX_FULL; |
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445 | |||
446 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); |
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447 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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448 | ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev; |
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449 | ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK; |
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450 | ath79_eth1_data.speed = SPEED_1000; |
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451 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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452 | |||
453 | platform_device_register(&rb493g_mdio_device); |
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454 | |||
455 | ath79_register_eth(1); |
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456 | ath79_register_eth(0); |
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457 | |||
458 | ath79_register_usb(); |
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459 | |||
460 | ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); |
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461 | ath79_register_pci(); |
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462 | } |
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463 | |||
464 | MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G", |
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465 | rb493g_setup); |