OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * D-Link DAP-2695 rev. A1 support |
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3 | * |
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4 | * Copyright (c) 2012 Qualcomm Atheros |
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5 | * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org> |
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6 | * Copyright (c) 2016 Stijn Tintel <stijn@linux-ipv6.be> |
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7 | * |
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8 | * Permission to use, copy, modify, and/or distribute this software for any |
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9 | * purpose with or without fee is hereby granted, provided that the above |
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10 | * copyright notice and this permission notice appear in all copies. |
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11 | * |
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12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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19 | * |
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20 | */ |
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21 | |||
22 | #include <linux/mtd/mtd.h> |
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23 | #include <linux/mtd/partitions.h> |
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24 | #include <linux/platform_device.h> |
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25 | #include <linux/ar8216_platform.h> |
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26 | |||
27 | #include <asm/mach-ath79/ar71xx_regs.h> |
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28 | |||
29 | #include "common.h" |
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30 | #include "pci.h" |
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31 | #include "dev-ap9x-pci.h" |
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32 | #include "dev-gpio-buttons.h" |
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33 | #include "dev-eth.h" |
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34 | #include "dev-leds-gpio.h" |
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35 | #include "dev-m25p80.h" |
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36 | #include "dev-spi.h" |
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37 | #include "dev-wmac.h" |
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38 | #include "machtypes.h" |
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39 | #include "nvram.h" |
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40 | |||
41 | #define DAP2695_GPIO_LED_GREEN_POWER 23 |
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42 | #define DAP2695_GPIO_LED_RED_POWER 14 |
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43 | #define DAP2695_GPIO_LED_WLAN_2G 13 |
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44 | |||
45 | #define DAP2695_GPIO_BTN_RESET 17 |
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46 | |||
47 | #define DAP2695_KEYS_POLL_INTERVAL 20 /* msecs */ |
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48 | #define DAP2695_KEYS_DEBOUNCE_INTERVAL (3 * DAP2695_KEYS_POLL_INTERVAL) |
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49 | |||
50 | #define DAP2695_NVRAM_ADDR 0x1f040000 |
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51 | #define DAP2695_NVRAM_SIZE 0x10000 |
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52 | |||
53 | #define DAP2695_MAC0_OFFSET 1 |
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54 | #define DAP2695_MAC1_OFFSET 2 |
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55 | #define DAP2695_WMAC_CALDATA_OFFSET 0x1000 |
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56 | |||
57 | static struct gpio_led dap2695_leds_gpio[] __initdata = { |
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58 | { |
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59 | .name = "d-link:green:power", |
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60 | .gpio = DAP2695_GPIO_LED_GREEN_POWER, |
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61 | .active_low = 1, |
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62 | }, |
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63 | { |
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64 | .name = "d-link:red:power", |
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65 | .gpio = DAP2695_GPIO_LED_RED_POWER, |
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66 | .active_low = 1, |
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67 | }, |
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68 | { |
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69 | .name = "d-link:green:wlan2g", |
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70 | .gpio = DAP2695_GPIO_LED_WLAN_2G, |
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71 | .active_low = 1, |
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72 | }, |
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73 | }; |
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74 | |||
75 | static struct gpio_keys_button dap2695_gpio_keys[] __initdata = { |
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76 | { |
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77 | .desc = "Soft reset", |
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78 | .type = EV_KEY, |
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79 | .code = KEY_RESTART, |
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80 | .debounce_interval = DAP2695_KEYS_DEBOUNCE_INTERVAL, |
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81 | .gpio = DAP2695_GPIO_BTN_RESET, |
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82 | .active_low = 1, |
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83 | }, |
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84 | }; |
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85 | |||
86 | static struct ar8327_pad_cfg dap2695_ar8327_pad0_cfg = { |
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87 | .mode = AR8327_PAD_MAC_RGMII, |
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88 | .txclk_delay_en = true, |
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89 | .rxclk_delay_en = true, |
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90 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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91 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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92 | .mac06_exchange_dis = true, |
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93 | }; |
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94 | |||
95 | static struct ar8327_pad_cfg dap2695_ar8327_pad6_cfg = { |
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96 | .mode = AR8327_PAD_MAC_SGMII, |
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97 | .sgmii_delay_en = true, |
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98 | }; |
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99 | |||
100 | static struct ar8327_platform_data dap2695_ar8327_data = { |
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101 | .pad0_cfg = &dap2695_ar8327_pad0_cfg, |
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102 | .pad6_cfg = &dap2695_ar8327_pad6_cfg, |
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103 | .port0_cfg = { |
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104 | .force_link = 1, |
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105 | .speed = AR8327_PORT_SPEED_1000, |
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106 | .duplex = 1, |
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107 | .txpause = 1, |
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108 | .rxpause = 1, |
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109 | }, |
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110 | .port6_cfg = { |
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111 | .force_link = 1, |
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112 | .speed = AR8327_PORT_SPEED_1000, |
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113 | .duplex = 1, |
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114 | .txpause = 1, |
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115 | .rxpause = 1, |
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116 | }, |
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117 | }; |
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118 | |||
119 | static struct mdio_board_info dap2695_mdio0_info[] = { |
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120 | { |
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121 | .bus_id = "ag71xx-mdio.0", |
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122 | .mdio_addr = 0, |
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123 | .platform_data = &dap2695_ar8327_data, |
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124 | }, |
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125 | }; |
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126 | |||
127 | static struct flash_platform_data dap2695_flash_data = { |
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128 | .type = "mx25l12805d", |
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129 | }; |
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130 | |||
131 | static void dap2695_get_mac(const char *name, char *mac) |
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132 | { |
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133 | u8 *nvram = (u8 *) KSEG1ADDR(DAP2695_NVRAM_ADDR); |
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134 | int err; |
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135 | |||
136 | err = ath79_nvram_parse_mac_addr(nvram, DAP2695_NVRAM_SIZE, |
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137 | name, mac); |
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138 | if (err) |
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139 | pr_err("no MAC address found for %s\n", name); |
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140 | } |
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141 | |||
142 | static void __init dap2695_setup(void) |
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143 | { |
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144 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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145 | u8 mac0[ETH_ALEN], mac1[ETH_ALEN], wmac0[ETH_ALEN]; |
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146 | |||
147 | dap2695_get_mac("lanmac=", mac0); |
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148 | dap2695_get_mac("wanmac=", mac1); |
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149 | dap2695_get_mac("wlanmac=", wmac0); |
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150 | |||
151 | ath79_register_m25p80(&dap2695_flash_data); |
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152 | |||
153 | ath79_register_leds_gpio(-1, ARRAY_SIZE(dap2695_leds_gpio), |
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154 | dap2695_leds_gpio); |
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155 | ath79_register_gpio_keys_polled(-1, DAP2695_KEYS_POLL_INTERVAL, |
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156 | ARRAY_SIZE(dap2695_gpio_keys), |
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157 | dap2695_gpio_keys); |
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158 | |||
159 | ath79_register_wmac(art + DAP2695_WMAC_CALDATA_OFFSET, wmac0); |
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160 | |||
161 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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162 | |||
163 | ath79_register_mdio(0, 0x0); |
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164 | |||
165 | mdiobus_register_board_info(dap2695_mdio0_info, |
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166 | ARRAY_SIZE(dap2695_mdio0_info)); |
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167 | |||
168 | /* GMAC0 is connected to the RGMII interface */ |
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169 | ath79_init_mac(ath79_eth0_data.mac_addr, mac0, DAP2695_MAC0_OFFSET); |
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170 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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171 | ath79_eth0_data.phy_mask = BIT(0); |
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172 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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173 | ath79_eth0_pll_data.pll_1000 = 0x56000000; |
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174 | |||
175 | ath79_register_eth(0); |
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176 | |||
177 | /* GMAC1 is connected to the SGMII interface */ |
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178 | ath79_init_mac(ath79_eth1_data.mac_addr, mac1, DAP2695_MAC1_OFFSET); |
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179 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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180 | ath79_eth1_data.speed = SPEED_1000; |
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181 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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182 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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183 | |||
184 | ath79_register_eth(1); |
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185 | |||
186 | ath79_register_pci(); |
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187 | } |
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188 | |||
189 | MIPS_MACHINE(ATH79_MACH_DAP_2695_A1, "DAP-2695-A1", |
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190 | "D-Link DAP-2695 rev. A1", |
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191 | dap2695_setup); |