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1 office 1 /*
2 * ADM5120 HCD (Host Controller Driver) for USB
3 *
4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was derived from: drivers/usb/host/ohci.h
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15  
16 /*
17 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
18 * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
19 * host controller implementation.
20 */
21 typedef __u32 __bitwise __hc32;
22 typedef __u16 __bitwise __hc16;
23  
24 /*
25 * OHCI Endpoint Descriptor (ED) ... holds TD queue
26 * See OHCI spec, section 4.2
27 *
28 * This is a "Queue Head" for those transfers, which is why
29 * both EHCI and UHCI call similar structures a "QH".
30 */
31  
32 #define TD_DATALEN_MAX 4096
33  
34 #define ED_ALIGN 16
35 #define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */
36  
37 struct ed {
38 /* first fields are hardware-specified */
39 __hc32 hwINFO; /* endpoint config bitmap */
40 /* info bits defined by hcd */
41 #define ED_DEQUEUE (1 << 27)
42 /* info bits defined by the hardware */
43 #define ED_MPS_SHIFT 16
44 #define ED_MPS_MASK ((1 << 11)-1)
45 #define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
46 #define ED_ISO (1 << 15) /* isochronous endpoint */
47 #define ED_SKIP (1 << 14)
48 #define ED_SPEED_FULL (1 << 13) /* fullspeed device */
49 #define ED_INT (1 << 11) /* interrupt endpoint */
50 #define ED_EN_SHIFT 7 /* endpoint shift */
51 #define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */
52 #define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
53 #define ED_FA_MASK ((1 << 7)-1) /* function address mask */
54 #define ED_FA_GET(x) ((x) & ED_FA_MASK)
55 __hc32 hwTailP; /* tail of TD list */
56 __hc32 hwHeadP; /* head of TD list (hc r/w) */
57 #define ED_C (0x02) /* toggle carry */
58 #define ED_H (0x01) /* halted */
59 __hc32 hwNextED; /* next ED in list */
60  
61 /* rest are purely for the driver's use */
62 dma_addr_t dma; /* addr of ED */
63 struct td *dummy; /* next TD to activate */
64  
65 struct list_head urb_list; /* list of our URBs */
66  
67 /* host's view of schedule */
68 struct ed *ed_next; /* on schedule list */
69 struct ed *ed_prev; /* for non-interrupt EDs */
70 struct ed *ed_rm_next; /* on rm list */
71 struct list_head td_list; /* "shadow list" of our TDs */
72  
73 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
74 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
75 */
76 u8 state; /* ED_{IDLE,UNLINK,OPER} */
77 #define ED_IDLE 0x00 /* NOT linked to HC */
78 #define ED_UNLINK 0x01 /* being unlinked from hc */
79 #define ED_OPER 0x02 /* IS linked to hc */
80  
81 u8 type; /* PIPE_{BULK,...} */
82  
83 /* periodic scheduling params (for intr and iso) */
84 u8 branch;
85 u16 interval;
86 u16 load;
87 u16 last_iso; /* iso only */
88  
89 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
90 u16 tick;
91 } __attribute__ ((aligned(ED_ALIGN)));
92  
93 /*
94 * OHCI Transfer Descriptor (TD) ... one per transfer segment
95 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
96 * and 4.3.2 (iso)
97 */
98  
99 #define TD_ALIGN 32
100 #define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */
101  
102 struct td {
103 /* first fields are hardware-specified */
104 __hc32 hwINFO; /* transfer info bitmask */
105  
106 /* hwINFO bits */
107 #define TD_OWN (1 << 31) /* owner of the descriptor */
108 #define TD_CC_SHIFT 27 /* condition code */
109 #define TD_CC_MASK 0xf
110 #define TD_CC (TD_CC_MASK << TD_CC_SHIFT)
111 #define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
112  
113 #define TD_EC_SHIFT 25 /* error count */
114 #define TD_EC_MASK 0x3
115 #define TD_EC (TD_EC_MASK << TD_EC_SHIFT)
116 #define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK)
117 #define TD_T_SHIFT 23 /* data toggle state */
118 #define TD_T_MASK 0x3
119 #define TD_T (TD_T_MASK << TD_T_SHIFT)
120 #define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */
121 #define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */
122 #define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */
123 #define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK)
124 #define TD_DP_SHIFT 21 /* direction/pid */
125 #define TD_DP_MASK 0x3
126 #define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
127 #define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
128 #define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
129 #define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
130 #define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
131 #define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
132 #define TD_ISI_MASK 0x3f
133 #define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
134 #define TD_FN_MASK 0x3f /* frame number */
135 #define TD_FN_GET(x) ((x) & TD_FN_MASK)
136  
137 __hc32 hwDBP; /* Data Buffer Pointer (or 0) */
138 __hc32 hwCBL; /* Controller/Buffer Length */
139  
140 /* hwCBL bits */
141 #define TD_BL_MASK 0xffff /* buffer length */
142 #define TD_BL_GET(x) ((x) & TD_BL_MASK)
143 #define TD_IE (1 << 16) /* interrupt enable */
144 __hc32 hwNextTD; /* Next TD Pointer */
145  
146 /* rest are purely for the driver's use */
147 __u8 index;
148 struct ed *ed;
149 struct td *td_hash; /* dma-->td hashtable */
150 struct td *next_dl_td;
151 struct urb *urb;
152  
153 dma_addr_t td_dma; /* addr of this TD */
154 dma_addr_t data_dma; /* addr of data it points to */
155  
156 struct list_head td_list; /* "shadow list", TDs on same ED */
157  
158 u32 flags;
159 #define TD_FLAG_DONE (1 << 17) /* retired to done list */
160 #define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
161 } __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */
162  
163 /*
164 * Hardware transfer status codes -- CC from td->hwINFO
165 */
166 #define TD_CC_NOERROR 0x00
167 #define TD_CC_CRC 0x01
168 #define TD_CC_BITSTUFFING 0x02
169 #define TD_CC_DATATOGGLEM 0x03
170 #define TD_CC_STALL 0x04
171 #define TD_CC_DEVNOTRESP 0x05
172 #define TD_CC_PIDCHECKFAIL 0x06
173 #define TD_CC_UNEXPECTEDPID 0x07
174 #define TD_CC_DATAOVERRUN 0x08
175 #define TD_CC_DATAUNDERRUN 0x09
176 /* 0x0A, 0x0B reserved for hardware */
177 #define TD_CC_BUFFEROVERRUN 0x0C
178 #define TD_CC_BUFFERUNDERRUN 0x0D
179 /* 0x0E, 0x0F reserved for HCD */
180 #define TD_CC_HCD0 0x0E
181 #define TD_CC_NOTACCESSED 0x0F
182  
183 /*
184 * preshifted status codes
185 */
186 #define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT)
187  
188  
189 /* map OHCI TD status codes (CC) to errno values */
190 static const int cc_to_error[16] = {
191 /* No Error */ 0,
192 /* CRC Error */ -EILSEQ,
193 /* Bit Stuff */ -EPROTO,
194 /* Data Togg */ -EILSEQ,
195 /* Stall */ -EPIPE,
196 /* DevNotResp */ -ETIME,
197 /* PIDCheck */ -EPROTO,
198 /* UnExpPID */ -EPROTO,
199 /* DataOver */ -EOVERFLOW,
200 /* DataUnder */ -EREMOTEIO,
201 /* (for hw) */ -EIO,
202 /* (for hw) */ -EIO,
203 /* BufferOver */ -ECOMM,
204 /* BuffUnder */ -ENOSR,
205 /* (for HCD) */ -EALREADY,
206 /* (for HCD) */ -EALREADY
207 };
208  
209 #define NUM_INTS 32
210  
211 /*
212 * This is the structure of the OHCI controller's memory mapped I/O region.
213 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
214 * Layout is in section 7 (and appendix B) of the spec.
215 */
216 struct admhcd_regs {
217 __hc32 gencontrol; /* General Control */
218 __hc32 int_status; /* Interrupt Status */
219 __hc32 int_enable; /* Interrupt Enable */
220 __hc32 reserved00;
221 __hc32 host_control; /* Host General Control */
222 __hc32 reserved01;
223 __hc32 fminterval; /* Frame Interval */
224 __hc32 fmnumber; /* Frame Number */
225 __hc32 reserved02;
226 __hc32 reserved03;
227 __hc32 reserved04;
228 __hc32 reserved05;
229 __hc32 reserved06;
230 __hc32 reserved07;
231 __hc32 reserved08;
232 __hc32 reserved09;
233 __hc32 reserved10;
234 __hc32 reserved11;
235 __hc32 reserved12;
236 __hc32 reserved13;
237 __hc32 reserved14;
238 __hc32 reserved15;
239 __hc32 reserved16;
240 __hc32 reserved17;
241 __hc32 reserved18;
242 __hc32 reserved19;
243 __hc32 reserved20;
244 __hc32 reserved21;
245 __hc32 lsthresh; /* Low Speed Threshold */
246 __hc32 rhdesc; /* Root Hub Descriptor */
247 #define MAX_ROOT_PORTS 2
248 __hc32 portstatus[MAX_ROOT_PORTS]; /* Port Status */
249 __hc32 hosthead; /* Host Descriptor Head */
250 } __attribute__ ((aligned(32)));
251  
252 /*
253 * General Control register bits
254 */
255 #define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */
256 #define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */
257 #define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */
258 #define ADMHC_CTRL_SR (1 << 3) /* Software Reset */
259  
260 /*
261 * Host General Control register bits
262 */
263 #define ADMHC_HC_BUSS 0x3 /* USB bus state */
264 #define ADMHC_BUSS_RESET 0x0
265 #define ADMHC_BUSS_RESUME 0x1
266 #define ADMHC_BUSS_OPER 0x2
267 #define ADMHC_BUSS_SUSPEND 0x3
268 #define ADMHC_HC_DMAE (1 << 2) /* DMA enable */
269  
270 /*
271 * Interrupt Status/Enable register bits
272 */
273 #define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
274 #define ADMHC_INTR_RESI (1 << 5) /* resume detected */
275 #define ADMHC_INTR_6 (1 << 6) /* unknown */
276 #define ADMHC_INTR_7 (1 << 7) /* unknown */
277 #define ADMHC_INTR_BABI (1 << 8) /* babble detected */
278 #define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
279 #define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
280 #define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */
281 #define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */
282 #define ADMHC_INTR_SWI (1 << 29) /* software interrupt */
283 #define ADMHC_INTR_FATI (1 << 30) /* fatal error */
284 #define ADMHC_INTR_INTA (1 << 31) /* interrupt active */
285  
286 #define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */
287  
288 /*
289 * SOF Frame Interval register bits
290 */
291 #define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */
292 #define ADMHC_SFI_FSLDP_SHIFT 16
293 #define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1)
294 #define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */
295  
296 /*
297 * SOF Frame Number register bits
298 */
299 #define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */
300 #define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */
301 #define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */
302 #define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */
303  
304 /*
305 * Root Hub Descriptor register bits
306 */
307 #define ADMHC_RH_NUMP 0xff /* number of ports */
308 #define ADMHC_RH_PSM (1 << 8) /* power switching mode */
309 #define ADMHC_RH_NPS (1 << 9) /* no power switching */
310 #define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */
311 #define ADMHC_RH_NOCP (1 << 11) /* no over current protection */
312 #define ADMHC_RH_PPCM (0xff << 16) /* port power control */
313  
314 #define ADMHC_RH_LPS (1 << 24) /* local power switch */
315 #define ADMHC_RH_OCI (1 << 25) /* over current indicator */
316  
317 /* status change bits */
318 #define ADMHC_RH_LPSC (1 << 26) /* local power switch change */
319 #define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */
320  
321 #define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */
322 #define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */
323  
324 #define ADMHC_RH_CGP (1 << 24) /* clear global power */
325 #define ADMHC_RH_SGP (1 << 26) /* set global power */
326  
327 /*
328 * Port Status register bits
329 */
330 #define ADMHC_PS_CCS (1 << 0) /* current connect status */
331 #define ADMHC_PS_PES (1 << 1) /* port enable status */
332 #define ADMHC_PS_PSS (1 << 2) /* port suspend status */
333 #define ADMHC_PS_POCI (1 << 3) /* port over current indicator */
334 #define ADMHC_PS_PRS (1 << 4) /* port reset status */
335 #define ADMHC_PS_PPS (1 << 8) /* port power status */
336 #define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */
337  
338 /* status change bits */
339 #define ADMHC_PS_CSC (1 << 16) /* connect status change */
340 #define ADMHC_PS_PESC (1 << 17) /* port enable status change */
341 #define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */
342 #define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */
343 #define ADMHC_PS_PRSC (1 << 20) /* port reset status change */
344  
345 /* port feature bits */
346 #define ADMHC_PS_CPE (1 << 0) /* clear port enable */
347 #define ADMHC_PS_SPE (1 << 1) /* set port enable */
348 #define ADMHC_PS_SPS (1 << 2) /* set port suspend */
349 #define ADMHC_PS_CPS (1 << 3) /* clear suspend status */
350 #define ADMHC_PS_SPR (1 << 4) /* set port reset */
351 #define ADMHC_PS_SPP (1 << 8) /* set port power */
352 #define ADMHC_PS_CPP (1 << 9) /* clear port power */
353  
354 /*
355 * the POTPGT value is not defined in the ADMHC, so define a dummy value
356 */
357 #define ADMHC_POTPGT 2 /* in ms */
358  
359 /* hcd-private per-urb state */
360 struct urb_priv {
361 struct ed *ed;
362 struct list_head pending; /* URBs on the same ED */
363  
364 u32 td_cnt; /* # tds in this request */
365 u32 td_idx; /* index of the current td */
366 struct td *td[0]; /* all TDs in this request */
367 };
368  
369 #define TD_HASH_SIZE 64 /* power'o'two */
370 /* sizeof (struct td) ~= 64 == 2^6 ... */
371 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
372  
373 /*
374 * This is the full ADMHCD controller description
375 *
376 * Note how the "proper" USB information is just
377 * a subset of what the full implementation needs. (Linus)
378 */
379  
380 struct admhcd {
381 spinlock_t lock;
382  
383 /*
384 * I/O memory used to communicate with the HC (dma-consistent)
385 */
386 struct admhcd_regs __iomem *regs;
387  
388 /*
389 * hcd adds to schedule for a live hc any time, but removals finish
390 * only at the start of the next frame.
391 */
392  
393 struct ed *ed_head;
394 struct ed *ed_tails[4];
395  
396 struct ed *ed_rm_list; /* to be removed */
397  
398 struct ed *periodic[NUM_INTS]; /* shadow int_table */
399  
400 #if 0 /* TODO: remove? */
401 /*
402 * OTG controllers and transceivers need software interaction;
403 * other external transceivers should be software-transparent
404 */
405 struct otg_transceiver *transceiver;
406 void (*start_hnp)(struct admhcd *ahcd);
407 #endif
408  
409 /*
410 * memory management for queue data structures
411 */
412 struct dma_pool *td_cache;
413 struct dma_pool *ed_cache;
414 struct td *td_hash[TD_HASH_SIZE];
415 struct list_head pending;
416  
417 /*
418 * driver state
419 */
420 int num_ports;
421 int load[NUM_INTS];
422 u32 host_control; /* copy of the host_control reg */
423 unsigned long next_statechange; /* suspend/resume */
424 u32 fminterval; /* saved register */
425 unsigned autostop:1; /* rh auto stopping/stopped */
426  
427 unsigned long flags; /* for HC bugs */
428 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
429 #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
430 #define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
431 #define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
432 #define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
433 #define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
434 /* there are also chip quirks/bugs in init logic */
435  
436 #ifdef DEBUG
437 struct dentry *debug_dir;
438 struct dentry *debug_async;
439 struct dentry *debug_periodic;
440 struct dentry *debug_registers;
441 #endif
442 };
443  
444 /* convert between an hcd pointer and the corresponding ahcd_hcd */
445 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
446 {
447 return (struct admhcd *)(hcd->hcd_priv);
448 }
449 static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
450 {
451 return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
452 }
453  
454 /*-------------------------------------------------------------------------*/
455  
456 #ifndef DEBUG
457 #define STUB_DEBUG_FILES
458 #endif /* DEBUG */
459  
460 #ifdef DEBUG
461 # define admhc_dbg(ahcd, fmt, args...) \
462 printk(KERN_DEBUG "adm5120-hcd: " fmt, ## args)
463 #else
464 # define admhc_dbg(ahcd, fmt, args...) do { } while (0)
465 #endif
466  
467 #define admhc_err(ahcd, fmt, args...) \
468 printk(KERN_ERR "adm5120-hcd: " fmt, ## args)
469 #define admhc_info(ahcd, fmt, args...) \
470 printk(KERN_INFO "adm5120-hcd: " fmt, ## args)
471 #define admhc_warn(ahcd, fmt, args...) \
472 printk(KERN_WARNING "adm5120-hcd: " fmt, ## args)
473  
474 #ifdef ADMHC_VERBOSE_DEBUG
475 # define admhc_vdbg admhc_dbg
476 #else
477 # define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
478 #endif
479  
480 /*-------------------------------------------------------------------------*/
481  
482 /*
483 * While most USB host controllers implement their registers and
484 * in-memory communication descriptors in little-endian format,
485 * a minority (notably the IBM STB04XXX and the Motorola MPC5200
486 * processors) implement them in big endian format.
487 *
488 * In addition some more exotic implementations like the Toshiba
489 * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
490 * they have a different endianness for registers vs. in-memory
491 * descriptors.
492 *
493 * This attempts to support either format at compile time without a
494 * runtime penalty, or both formats with the additional overhead
495 * of checking a flag bit.
496 *
497 * That leads to some tricky Kconfig rules howevber. There are
498 * different defaults based on some arch/ppc platforms, though
499 * the basic rules are:
500 *
501 * Controller type Kconfig options needed
502 * --------------- ----------------------
503 * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN
504 *
505 * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
506 * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
507 *
508 * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
509 * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
510 *
511 * (If you have a mixed endian controller, you -must- also define
512 * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
513 * both your mixed endian and a fully big endian controller support in
514 * the same kernel image).
515 */
516  
517 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
518 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
519 #define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC)
520 #else
521 #define big_endian_desc(ahcd) 1 /* only big endian */
522 #endif
523 #else
524 #define big_endian_desc(ahcd) 0 /* only little endian */
525 #endif
526  
527 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
528 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
529 #define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO)
530 #else
531 #define big_endian_mmio(ahcd) 1 /* only big endian */
532 #endif
533 #else
534 #define big_endian_mmio(ahcd) 0 /* only little endian */
535 #endif
536  
537 /*
538 * Big-endian read/write functions are arch-specific.
539 * Other arches can be added if/when they're needed.
540 *
541 */
542 static inline unsigned int admhc_readl(const struct admhcd *ahcd,
543 __hc32 __iomem *regs)
544 {
545 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
546 return big_endian_mmio(ahcd) ?
547 readl_be(regs) :
548 readl(regs);
549 #else
550 return readl(regs);
551 #endif
552 }
553  
554 static inline void admhc_writel(const struct admhcd *ahcd,
555 const unsigned int val, __hc32 __iomem *regs)
556 {
557 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
558 big_endian_mmio(ahcd) ?
559 writel_be(val, regs) :
560 writel(val, regs);
561 #else
562 writel(val, regs);
563 #endif
564 }
565  
566 static inline void admhc_writel_flush(const struct admhcd *ahcd)
567 {
568 #if 0
569 /* TODO: remove? */
570 (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
571 #endif
572 }
573  
574  
575 /*-------------------------------------------------------------------------*/
576  
577 /* cpu to ahcd */
578 static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
579 {
580 return big_endian_desc(ahcd) ?
581 (__force __hc16)cpu_to_be16(x) :
582 (__force __hc16)cpu_to_le16(x);
583 }
584  
585 static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
586 {
587 return big_endian_desc(ahcd) ?
588 cpu_to_be16p(x) :
589 cpu_to_le16p(x);
590 }
591  
592 static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
593 {
594 return big_endian_desc(ahcd) ?
595 (__force __hc32)cpu_to_be32(x) :
596 (__force __hc32)cpu_to_le32(x);
597 }
598  
599 static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
600 {
601 return big_endian_desc(ahcd) ?
602 cpu_to_be32p(x) :
603 cpu_to_le32p(x);
604 }
605  
606 /* ahcd to cpu */
607 static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
608 {
609 return big_endian_desc(ahcd) ?
610 be16_to_cpu((__force __be16)x) :
611 le16_to_cpu((__force __le16)x);
612 }
613  
614 static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
615 {
616 return big_endian_desc(ahcd) ?
617 be16_to_cpup((__force __be16 *)x) :
618 le16_to_cpup((__force __le16 *)x);
619 }
620  
621 static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
622 {
623 return big_endian_desc(ahcd) ?
624 be32_to_cpu((__force __be32)x) :
625 le32_to_cpu((__force __le32)x);
626 }
627  
628 static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
629 {
630 return big_endian_desc(ahcd) ?
631 be32_to_cpup((__force __be32 *)x) :
632 le32_to_cpup((__force __le32 *)x);
633 }
634  
635 /*-------------------------------------------------------------------------*/
636  
637 static inline u16 admhc_frame_no(const struct admhcd *ahcd)
638 {
639 u32 t;
640  
641 t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
642 return (u16)t;
643 }
644  
645 static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
646 {
647 u32 t;
648  
649 t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
650 t &= ADMHC_SFN_FR_MASK;
651 return (u16)t;
652 }
653  
654 /*-------------------------------------------------------------------------*/
655  
656 static inline void admhc_disable(struct admhcd *ahcd)
657 {
658 admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
659 }
660  
661 #define FI 0x2edf /* 12000 bits per frame (-1) */
662 #define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
663 #define FIT ADMHC_SFI_FIT
664 #define LSTHRESH 0x628 /* lowspeed bit threshold */
665  
666 static inline void periodic_reinit(struct admhcd *ahcd)
667 {
668 #if 0
669 u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
670 u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
671  
672 /* TODO: adjust FSLargestDataPacket value too? */
673 admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
674 &ahcd->regs->fminterval);
675 #else
676 u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
677  
678 /* TODO: adjust FSLargestDataPacket value too? */
679 admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
680 &ahcd->regs->fminterval);
681 #endif
682 }
683  
684 static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
685 {
686 return admhc_readl(ahcd, &ahcd->regs->rhdesc);
687 }
688  
689 static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
690 {
691 return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
692 }
693  
694 static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
695 u32 value)
696 {
697 admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
698 }
699  
700 static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
701 {
702 /* FIXME: read-only bits must be masked out */
703 admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
704 }
705  
706 static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
707 {
708 u32 t;
709  
710 t = admhc_readl(ahcd, &ahcd->regs->int_enable);
711 t &= ~(ints);
712 admhc_writel(ahcd, t, &ahcd->regs->int_enable);
713 /* TODO: flush writes ?*/
714 }
715  
716 static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
717 {
718 u32 t;
719  
720 t = admhc_readl(ahcd, &ahcd->regs->int_enable);
721 t |= ints;
722 admhc_writel(ahcd, t, &ahcd->regs->int_enable);
723 /* TODO: flush writes ?*/
724 }
725  
726 static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
727 {
728 admhc_writel(ahcd, ints, &ahcd->regs->int_status);
729 }
730  
731 static inline void admhc_dma_enable(struct admhcd *ahcd)
732 {
733 u32 t;
734  
735 t = admhc_readl(ahcd, &ahcd->regs->host_control);
736 if (t & ADMHC_HC_DMAE)
737 return;
738  
739 t |= ADMHC_HC_DMAE;
740 admhc_writel(ahcd, t, &ahcd->regs->host_control);
741 admhc_vdbg(ahcd, "DMA enabled\n");
742 }
743  
744 static inline void admhc_dma_disable(struct admhcd *ahcd)
745 {
746 u32 t;
747  
748 t = admhc_readl(ahcd, &ahcd->regs->host_control);
749 if (!(t & ADMHC_HC_DMAE))
750 return;
751  
752 t &= ~ADMHC_HC_DMAE;
753 admhc_writel(ahcd, t, &ahcd->regs->host_control);
754 admhc_vdbg(ahcd, "DMA disabled\n");
755 }