OpenWrt – Blame information for rev 1
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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | office | 1 | /* |
| 2 | * ADM5120 UART definitions |
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| 3 | * |
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| 4 | * This header file defines the hardware registers of the ADM5120 SoC |
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| 5 | * built-in UARTs. |
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| 6 | * |
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| 7 | * Copyright (C) 2007 Gabor Juhos <juhosg@openwrt.org> |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or modify it |
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| 10 | * under the terms of the GNU General Public License version 2 as published |
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| 11 | * by the Free Software Foundation. |
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| 12 | * |
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| 13 | */ |
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| 14 | |||
| 15 | #ifndef _MACH_ADM5120_UART_H |
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| 16 | #define _MACH_ADM5120_UART_H |
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| 17 | |||
| 18 | #define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1) |
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| 19 | |||
| 20 | #define UART_REG_DATA 0x00 |
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| 21 | #define UART_REG_RSR 0x04 |
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| 22 | #define UART_REG_ECR UART_REG_RSR |
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| 23 | #define UART_REG_LCRH 0x08 |
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| 24 | #define UART_REG_LCRM 0x0C |
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| 25 | #define UART_REG_LCRL 0x10 |
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| 26 | #define UART_REG_CTRL 0x14 |
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| 27 | #define UART_REG_FLAG 0x18 |
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| 28 | |||
| 29 | /* Receive Status Register bits */ |
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| 30 | #define UART_RSR_FE (1 << 0) |
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| 31 | #define UART_RSR_PE (1 << 1) |
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| 32 | #define UART_RSR_BE (1 << 2) |
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| 33 | #define UART_RSR_OE (1 << 3) |
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| 34 | #define UART_RSR_ERR (UART_RSR_FE | UART_RSR_PE | UART_RSR_BE) |
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| 35 | |||
| 36 | #define UART_ECR_ALL 0xFF |
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| 37 | |||
| 38 | /* Line Control High register bits */ |
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| 39 | #define UART_LCRH_BRK (1 << 0) /* send break */ |
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| 40 | #define UART_LCRH_PEN (1 << 1) /* parity enable */ |
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| 41 | #define UART_LCRH_EPS (1 << 2) /* even parity select */ |
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| 42 | #define UART_LCRH_STP1 (0 << 3) /* one stop bits select */ |
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| 43 | #define UART_LCRH_STP2 (1 << 3) /* two stop bits select */ |
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| 44 | #define UART_LCRH_FEN (1 << 4) /* FIFO enable */ |
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| 45 | |||
| 46 | #define UART_LCRH_WLEN5 (0 << 5) |
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| 47 | #define UART_LCRH_WLEN6 (1 << 5) |
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| 48 | #define UART_LCRH_WLEN7 (2 << 5) |
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| 49 | #define UART_LCRH_WLEN8 (3 << 5) |
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| 50 | |||
| 51 | /* Control register bits */ |
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| 52 | #define UART_CTRL_EN (1 << 0) |
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| 53 | |||
| 54 | /* Flag register bits */ |
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| 55 | #define UART_FLAG_CTS (1 << 0) |
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| 56 | #define UART_FLAG_DSR (1 << 1) |
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| 57 | #define UART_FLAG_DCD (1 << 2) |
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| 58 | #define UART_FLAG_BUSY (1 << 3) |
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| 59 | #define UART_FLAG_RXFE (1 << 4) |
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| 60 | #define UART_FLAG_TXFF (1 << 5) |
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| 61 | #define UART_FLAG_RXFF (1 << 6) |
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| 62 | #define UART_FLAG_TXFE (1 << 7) |
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| 63 | |||
| 64 | #endif /* _MACH_ADM5120_UART_H */ |