OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c |
2 | +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c |
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3 | @@ -8401,6 +8401,160 @@ void rt2800_rf_self_txdc_cal(struct rt2x |
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4 | } |
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5 | EXPORT_SYMBOL_GPL(rt2800_rf_self_txdc_cal); |
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6 | |||
7 | +int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2) |
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8 | +{ |
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9 | + int calcode; |
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10 | + calcode = ((d2 - d1) * 1000) / 43; |
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11 | + if ((calcode%10) >= 5) |
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12 | + calcode += 10; |
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13 | + calcode = (calcode / 10); |
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14 | + |
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15 | + return calcode; |
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16 | +} |
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17 | +EXPORT_SYMBOL_GPL(rt2800_calcrcalibrationcode); |
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18 | + |
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19 | +void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) |
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20 | +{ |
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21 | + u32 savemacsysctrl; |
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22 | + u8 saverfb0r1, saverfb0r34, saverfb0r35; |
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23 | + u8 saverfb5r4, saverfb5r17, saverfb5r18; |
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24 | + u8 saverfb5r19, saverfb5r20; |
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25 | + u8 savebbpr22, savebbpr47, savebbpr49; |
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26 | + u8 bytevalue = 0; |
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27 | + int rcalcode; |
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28 | + u8 r_cal_code = 0; |
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29 | + char d1 = 0, d2 = 0; |
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30 | + u8 rfvalue; |
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31 | + u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG; |
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32 | + |
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33 | + saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); |
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34 | + saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34); |
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35 | + saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); |
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36 | + saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); |
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37 | + saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); |
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38 | + saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); |
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39 | + saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); |
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40 | + saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); |
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41 | + |
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42 | + savebbpr22 = rt2800_bbp_read(rt2x00dev, 22); |
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43 | + savebbpr47 = rt2800_bbp_read(rt2x00dev, 47); |
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44 | + savebbpr49 = rt2800_bbp_read(rt2x00dev, 49); |
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45 | + |
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46 | + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); |
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47 | + MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); |
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48 | + MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); |
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49 | + MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG); |
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50 | + |
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51 | + { |
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52 | + u32 maccfg, macstatus; |
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53 | + int i; |
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54 | + |
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55 | + maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); |
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56 | + maccfg &= (~0x04); |
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57 | + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); |
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58 | + |
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59 | + for (i = 0; i < 10000; i++) { |
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60 | + macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); |
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61 | + if (macstatus & 0x1) |
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62 | + udelay(50); |
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63 | + else |
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64 | + break; |
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65 | + } |
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66 | + |
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67 | + if (i == 10000) |
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68 | + rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); |
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69 | + |
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70 | + maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); |
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71 | + maccfg &= (~0x04); |
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72 | + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); |
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73 | + |
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74 | + for (i = 0; i < 10000; i++) { |
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75 | + macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); |
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76 | + if (macstatus & 0x2) |
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77 | + udelay(50); |
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78 | + else |
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79 | + break; |
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80 | + } |
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81 | + |
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82 | + if (i == 10000) |
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83 | + rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n"); |
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84 | + } |
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85 | + |
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86 | + rfvalue = (MAC_RF_BYPASS0 | 0x3004); |
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87 | + rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue); |
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88 | + rfvalue = (MAC_RF_CONTROL0 | (~0x3002)); |
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89 | + rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue); |
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90 | + |
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91 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27); |
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92 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); |
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93 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83); |
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94 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00); |
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95 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); |
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96 | + |
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97 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00); |
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98 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13); |
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99 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); |
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100 | + |
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101 | + rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1); |
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102 | + |
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103 | + rt2800_bbp_write(rt2x00dev, 47, 0x04); |
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104 | + rt2800_bbp_write(rt2x00dev, 22, 0x80); |
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105 | + udelay(100); |
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106 | + bytevalue = rt2800_bbp_read(rt2x00dev, 49); |
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107 | + if (bytevalue > 128) |
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108 | + d1 = bytevalue - 256; |
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109 | + else |
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110 | + d1 = (char)bytevalue; |
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111 | + rt2800_bbp_write(rt2x00dev, 22, 0x0); |
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112 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01); |
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113 | + |
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114 | + rt2800_bbp_write(rt2x00dev, 22, 0x80); |
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115 | + udelay(100); |
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116 | + bytevalue = rt2800_bbp_read(rt2x00dev, 49); |
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117 | + if (bytevalue > 128) |
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118 | + d2 = bytevalue - 256; |
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119 | + else |
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120 | + d2 = (char)bytevalue; |
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121 | + rt2800_bbp_write(rt2x00dev, 22, 0x0); |
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122 | + |
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123 | + rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2); |
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124 | + if (rcalcode < 0) |
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125 | + r_cal_code = 256 + rcalcode; |
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126 | + else |
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127 | + r_cal_code = (u8)rcalcode; |
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128 | + |
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129 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code); |
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130 | + |
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131 | + rt2800_bbp_write(rt2x00dev, 22, 0x0); |
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132 | + |
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133 | + bytevalue = rt2800_bbp_read(rt2x00dev, 21); |
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134 | + bytevalue |= 0x1; |
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135 | + rt2800_bbp_write(rt2x00dev, 21, bytevalue); |
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136 | + bytevalue = rt2800_bbp_read(rt2x00dev, 21); |
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137 | + bytevalue &= (~0x1); |
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138 | + rt2800_bbp_write(rt2x00dev, 21, bytevalue); |
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139 | + |
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140 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1); |
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141 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34); |
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142 | + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35); |
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143 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); |
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144 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); |
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145 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); |
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146 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); |
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147 | + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); |
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148 | + |
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149 | + rt2800_bbp_write(rt2x00dev, 22, savebbpr22); |
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150 | + rt2800_bbp_write(rt2x00dev, 47, savebbpr47); |
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151 | + rt2800_bbp_write(rt2x00dev, 49, savebbpr49); |
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152 | + |
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153 | + rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); |
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154 | + rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); |
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155 | + |
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156 | + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); |
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157 | + rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG); |
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158 | +} |
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159 | +EXPORT_SYMBOL_GPL(rt2800_r_calibration); |
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160 | + |
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161 | static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, |
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162 | bool set_bw, bool is_ht40) |
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163 | { |
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164 | @@ -9008,6 +9162,7 @@ static void rt2800_init_rfcsr_6352(struc |
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165 | rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); |
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166 | rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); |
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167 | |||
168 | + rt2800_r_calibration(rt2x00dev); |
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169 | rt2800_rf_self_txdc_cal(rt2x00dev); |
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170 | rt2800_bw_filter_calibration(rt2x00dev, true); |
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171 | rt2800_bw_filter_calibration(rt2x00dev, false); |
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172 | --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h |
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173 | +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h |
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174 | @@ -244,6 +244,8 @@ void rt2800_link_tuner(struct rt2x00_dev |
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175 | void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev); |
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176 | void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev); |
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177 | void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev); |
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178 | +int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2); |
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179 | +void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev); |
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180 | |||
181 | int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev); |
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182 | void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev); |
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183 | --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h |
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184 | +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h |
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185 | @@ -573,6 +573,8 @@ struct rt2x00lib_ops { |
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186 | void (*gain_calibration) (struct rt2x00_dev *rt2x00dev); |
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187 | void (*vco_calibration) (struct rt2x00_dev *rt2x00dev); |
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188 | void (*rf_self_txdc_cal) (struct rt2x00_dev *rt2x00dev); |
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189 | + int (*calcrcalibrationcode) (struct rt2x00_dev *rt2x00dev, int d1, int d2); |
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190 | + void (*r_calibration) (struct rt2x00_dev *rt2x00dev); |
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191 | |||
192 | /* |
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193 | * Data queue handlers. |