OpenWrt – Blame information for rev 1

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Rev Author Line No. Line
1 office 1 --- a/src/mps/drv_mps_vmmc_ar9.c
2 +++ b/src/mps/drv_mps_vmmc_ar9.c
3 @@ -30,15 +30,24 @@
4 #include "ifxos_interrupt.h"
5  
6 /* board specific headers */
7 +#if !defined CONFIG_LANTIQ
8 #include <asm/ifx/ifx_regs.h>
9 #include <asm/ifx_vpe.h>
10 #include <asm/ifx/ifx_gpio.h>
11 +#endif
12 +
13 +#include <lantiq_soc.h>
14 +#include <asm/vpe.h>
15  
16 /* device specific headers */
17 #include "drv_mps_vmmc.h"
18 #include "drv_mps_vmmc_dbg.h"
19 #include "drv_mps_vmmc_device.h"
20  
21 +const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;
22 +
23 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
24 +
25 /* ============================= */
26 /* Local Macros & Definitions */
27 /* ============================= */
28 @@ -65,12 +74,7 @@ extern mps_comm_dev *pMPSDev;
29 IFX_void_t ifx_mps_release (IFX_void_t);
30 extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);
31 extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);
32 -IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count);
33 extern IFXOS_event_t fw_ready_evt;
34 -/* ============================= */
35 -/* Local function declaration */
36 -/* ============================= */
37 -static IFX_int32_t ifx_mps_fw_wdog_start_ar9(IFX_void_t);
38  
39 /* ============================= */
40 /* Local variable definition */
41 @@ -88,61 +92,6 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui
42 ******************************************************************************/
43  
44 /**
45 - * Start AR9 EDSP firmware watchdog mechanism.
46 - * Called after download and startup of VPE1.
47 - *
48 - * \param none
49 - * \return 0 IFX_SUCCESS
50 - * \return -1 IFX_ERROR
51 - * \ingroup Internal
52 - */
53 -IFX_int32_t ifx_mps_fw_wdog_start_ar9()
54 -{
55 - /* vpe1_wdog_ctr should be set up in u-boot as
56 - "vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing
57 - setting */
58 - if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)
59 - {
60 - vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;
61 - }
62 -
63 - /* vpe1_wdog_timeout should be set up in u-boot as "vpe1_wdog_timeout =
64 - <value in ms>"; protection from insane setting */
65 - if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)
66 - {
67 - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;
68 - }
69 - if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)
70 - {
71 - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;
72 - }
73 -
74 - /* recalculate in jiffies */
75 - vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;
76 -
77 - /* register BSP callback function */
78 - if (IFX_SUCCESS !=
79 - vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))
80 - {
81 - TRACE (MPS, DBG_LEVEL_HIGH,
82 - (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n",
83 - __FILE__, __func__, __LINE__));
84 - return IFX_ERROR;;
85 - }
86 -
87 - /* start software watchdog timer */
88 - if (IFX_SUCCESS != vpe1_sw_wdog_start (0))
89 - {
90 - TRACE (MPS, DBG_LEVEL_HIGH,
91 - (KERN_ERR
92 - "[%s %s %d]: Error starting software watchdog timer.\r\n",
93 - __FILE__, __func__, __LINE__));
94 - return IFX_ERROR;
95 - }
96 - return IFX_SUCCESS;
97 -}
98 -
99 -/**
100 * Firmware download to Voice CPU
101 * This function performs a firmware download to the coprocessor.
102 *
103 @@ -292,6 +241,18 @@ IFX_int32_t ifx_mps_download_firmware (m
104 decryption. Subtract sizeof(u32) from length to avoid decryption
105 of data beyond the FW image code */
106 pFWDwnld->length -= sizeof(IFX_uint32_t);
107 + switch(ltq_soc_type()) {
108 + case SOC_TYPE_AR9:
109 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;
110 + break;
111 + case SOC_TYPE_VR9:
112 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;
113 + break;
114 + case SOC_TYPE_VR9_2:
115 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;
116 + break;
117 + }
118 + if (ifx_bsp_basic_mps_decrypt)
119 ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);
120 }
121  
122 @@ -318,9 +279,6 @@ IFX_int32_t ifx_mps_download_firmware (m
123 /* start VPE1 */
124 ifx_mps_release ();
125  
126 - /* start FW watchdog mechanism */
127 - ifx_mps_fw_wdog_start_ar9();
128 -
129 /* get FW version */
130 return ifx_mps_get_fw_version (0);
131 }
132 @@ -345,8 +303,6 @@ IFX_int32_t ifx_mps_restart (IFX_void_t)
133 ifx_mps_init_gpt ();
134 /* let CPU1 run */
135 ifx_mps_release ();
136 - /* start FW watchdog mechanism */
137 - ifx_mps_fw_wdog_start_ar9();
138 TRACE (MPS, DBG_LEVEL_HIGH, ("IFX_MPS: Restarting firmware..."));
139 return ifx_mps_get_fw_version (0);
140 }
141 @@ -361,10 +317,6 @@ IFX_void_t ifx_mps_shutdown (IFX_void_t)
142 {
143 if (vpe1_started)
144 {
145 - /* stop software watchdog timer */
146 - vpe1_sw_wdog_stop (0);
147 - /* clean up the BSP callback function */
148 - vpe1_sw_wdog_register_reset_handler (IFX_NULL);
149 /* stop VPE1 */
150 vpe1_sw_stop (0);
151 vpe1_started = 0;
152 @@ -387,8 +339,6 @@ IFX_void_t ifx_mps_reset (IFX_void_t)
153 /* if VPE1 is already started, stop it */
154 if (vpe1_started)
155 {
156 - /* stop software watchdog timer first */
157 - vpe1_sw_wdog_stop (0);
158 vpe1_sw_stop (0);
159 vpe1_started = 0;
160 }
161 @@ -436,101 +386,6 @@ IFX_void_t ifx_mps_release (IFX_void_t)
162 }
163  
164 /**
165 - * WDT callback.
166 - * This function is called by BSP (module softdog_vpe) in case if software
167 - * watchdog timer expiration is detected by BSP.
168 - * This function needs to be registered at BSP as WDT callback using
169 - * vpe1_sw_wdog_register_reset_handler() API.
170 - *
171 - * \return 0 IFX_SUCCESS, cannot fail
172 - * \ingroup Internal
173 - */
174 -IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count)
175 -{
176 - IFX_uint32_t flags;
177 -#ifdef DEBUG
178 - TRACE (MPS, DBG_LEVEL_HIGH,
179 - ("MPS: watchdog callback! arg=0x%08x\r\n", wdog_cleared_ok_count));
180 -#endif /* DEBUG */
181 -
182 - /* reset SmartSLIC */
183 - IFXOS_LOCKINT (flags);
184 - if (ifx_gpio_pin_reserve
185 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
186 - {
187 - TRACE (MPS, DBG_LEVEL_HIGH,
188 - (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
189 - __FILE__, __func__, __LINE__));
190 - }
191 - /* P1_ALTSEL0.15 = 0 */
192 - if (ifx_gpio_altsel0_clear
193 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
194 - {
195 - TRACE (MPS, DBG_LEVEL_HIGH,
196 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
197 - __func__, __LINE__));
198 - }
199 - /* P1_ALTSEL1.15 = 0 */
200 - if (ifx_gpio_altsel1_clear
201 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
202 - {
203 - TRACE (MPS, DBG_LEVEL_HIGH,
204 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
205 - __func__, __LINE__));
206 - }
207 - /* P1_DIR.15 = 1 */
208 - if (ifx_gpio_dir_out_set
209 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
210 - {
211 - TRACE (MPS, DBG_LEVEL_HIGH,
212 - (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
213 - __func__, __LINE__));
214 - }
215 - /* P1_OD.15 = 1 */
216 - if (ifx_gpio_open_drain_set
217 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
218 - {
219 - TRACE (MPS, DBG_LEVEL_HIGH,
220 - (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
221 - __func__, __LINE__));
222 - }
223 - /* P1_OUT.15 = 0 */
224 - if (ifx_gpio_output_clear
225 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
226 - {
227 - TRACE (MPS, DBG_LEVEL_HIGH,
228 - (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
229 - __func__, __LINE__));
230 - }
231 - if (ifx_gpio_pin_free
232 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
233 - {
234 - TRACE (MPS, DBG_LEVEL_HIGH,
235 - (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
236 - __func__, __LINE__));
237 - }
238 - IFXOS_UNLOCKINT (flags);
239 -
240 - /* recalculate and compare the firmware checksum */
241 - ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
242 -
243 - /* dump exception area on a console */
244 - ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
245 -
246 - if (IFX_NULL != ifx_wdog_callback)
247 - {
248 - /* call VMMC driver */
249 - ifx_wdog_callback (wdog_cleared_ok_count);
250 - }
251 - else
252 - {
253 - TRACE (MPS, DBG_LEVEL_HIGH,
254 - (KERN_WARNING "MPS: VMMC watchdog timer callback is NULL.\r\n"));
255 - }
256 - return 0;
257 -}
258 -
259 -/**
260 * Register WDT callback.
261 * This function is called by VMMC driver to register its callback in
262 * the MPS driver.
263 --- a/src/drv_vmmc_amazon_s.h
264 +++ b/src/drv_vmmc_amazon_s.h
265 @@ -15,9 +15,7 @@
266 */
267  
268  
269 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
270 -#include <asm/ifx/ifx_gpio.h>
271 -#else
272 +#if !defined(SYSTEM_AR9) && !defined(SYSTEM_VR9)
273 #error no system selected
274 #endif
275  
276 @@ -27,45 +25,6 @@
277 */
278 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
279 do { \
280 - ret = VMMC_statusOk; \
281 - /* Reserve P0.0 as TDM/FSC */ \
282 - if (!GPIOreserved) \
283 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
284 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
285 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
286 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
287 - \
288 - /* Reserve P1.9 as TDM/DO */ \
289 - if (!GPIOreserved) \
290 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
291 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
292 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
293 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
294 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
295 - \
296 - /* Reserve P2.9 as TDM/DI */ \
297 - if (!GPIOreserved) \
298 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
299 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
300 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\
301 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
302 - \
303 - /* Reserve P2.8 as TDM/DCL */ \
304 - if (!GPIOreserved) \
305 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
306 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
307 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
308 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
309 - \
310 - if (mode == 2) { \
311 - /* TDM/FSC+DCL Master */ \
312 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
313 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
314 - } else { \
315 - /* TDM/FSC+DCL Slave */ \
316 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
317 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
318 - } \
319 } while(0);
320  
321 /**
322 @@ -73,11 +32,6 @@ do { \
323 */
324 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
325 do { \
326 - ret = VMMC_statusOk; \
327 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
328 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
329 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
330 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
331 } while (0)
332  
333 #endif /* _DRV_VMMC_AMAZON_S_H */