WebSVN – OpenWrt – Blame – Rev 1 – /trunk/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe

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/******************************************************************************

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**

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** FILE NAME : ifxmips_ptm_ppe_common.h

** PROJECT : UEIP

** MODULES : PTM

**

** DATE : 7 Jul 2009

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** AUTHOR : Xu Liang

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** DESCRIPTION : PTM driver header file (PPE register for all platform)

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** Infineon Technologies AG

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** Am Campeon 1-12, 85579 Neubiberg, Germany

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**

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** This program is free software; you can redistribute it and/or modify

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** it under the terms of the GNU General Public License as published by

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** the Free Software Foundation; either version 2 of the License, or

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** (at your option) any later version.

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**

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** HISTORY

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** $Date $Author $Comment

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** 07 JUL 2009 Xu Liang Init Version

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*******************************************************************************/

#ifndef IFXMIPS_PTM_PPE_COMMON_H

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#define IFXMIPS_PTM_PPE_COMMON_H

#if defined(CONFIG_DANUBE)

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#include "ifxmips_ptm_ppe_danube.h"

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#elif defined(CONFIG_AMAZON_SE)

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#include "ifxmips_ptm_ppe_amazon_se.h"

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#elif defined(CONFIG_AR9)

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#include "ifxmips_ptm_ppe_ar9.h"

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#elif defined(CONFIG_VR9)

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#include "ifxmips_ptm_ppe_vr9.h"

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#else

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#error Platform is not specified!

#endif

/*

* Code/Data Memory (CDM) Interface Configuration Register

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*/

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#define CDM_CFG PPE_REG_ADDR(0x0100)

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#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2)

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#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1))

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#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value)

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#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0)

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/*

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* QSB Internal Cell Delay Variation Register

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*/

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#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007)

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#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0)

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#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value)

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/*

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* QSB Scheduler Burst Limit Register

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*/

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#define QSB_SBL QSB_CONF_REG_ADDR(0x0009)

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#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0)

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#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value)

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/*

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* QSB Configuration Register

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*/

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#define QSB_CFG QSB_CONF_REG_ADDR(0x000A)

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#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0)

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#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value)

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/*

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* QSB RAM Transfer Table Register

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*/

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#define QSB_RTM QSB_CONF_REG_ADDR(0x000B)

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#define QSB_RTM_DM (*QSB_RTM)

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#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF)

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/*

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* QSB RAM Transfer Data Register

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*/

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#define QSB_RTD QSB_CONF_REG_ADDR(0x000C)

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#define QSB_RTD_TTV (*QSB_RTD)

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#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF)

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/*

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* QSB RAM Access Register

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*/

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#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D)

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#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31))

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#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24)

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#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16))

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#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0)

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#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0)

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#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value)

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#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0)

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#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value)

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/*

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* QSB Queue Scheduling and Shaping Definitions

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*/

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#define QSB_WFQ_NONUBR_MAX 0x3f00

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#define QSB_WFQ_UBR_BYPASS 0x3fff

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#define QSB_TP_TS_MAX 65472

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#define QSB_TAUS_MAX 64512

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#define QSB_GCR_MIN 18

/*

* QSB Constant

*/

#define QSB_RAMAC_RW_READ 0

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#define QSB_RAMAC_RW_WRITE 1

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#define QSB_RAMAC_TSEL_QPT 0x01

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#define QSB_RAMAC_TSEL_SCT 0x02

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#define QSB_RAMAC_TSEL_SPT 0x03

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#define QSB_RAMAC_TSEL_VBR 0x08

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#define QSB_RAMAC_LH_LOW 0

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#define QSB_RAMAC_LH_HIGH 1

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#define QSB_QPT_SET_MASK 0x0

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#define QSB_QVPT_SET_MASK 0x0

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#define QSB_SET_SCT_MASK 0x0

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#define QSB_SET_SPT_MASK 0x0

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#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF

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#define QSB_SPT_SBV_VALID (1 << 31)

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#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0)

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#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value)

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/*

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* QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry

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*/

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#if defined(__BIG_ENDIAN)

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union qsb_queue_parameter_table {

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struct {

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unsigned int res1 :1;

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unsigned int vbr :1;

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unsigned int wfqf :14;

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unsigned int tp :16;

} bit;

u32 dword;

};

union qsb_queue_vbr_parameter_table {

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struct {

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unsigned int taus :16;

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unsigned int ts :16;

} bit;

u32 dword;

};

#else

union qsb_queue_parameter_table {

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struct {

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unsigned int tp :16;

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unsigned int wfqf :14;

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unsigned int vbr :1;

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unsigned int res1 :1;

} bit;

u32 dword;

};

union qsb_queue_vbr_parameter_table {

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struct {

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unsigned int ts :16;

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unsigned int taus :16;

} bit;

u32 dword;

};

#endif // defined(__BIG_ENDIAN)

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/*

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* Mailbox IGU0 Registers

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*/

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#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200)

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#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201)

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#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202)

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#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203)

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#define MBOX_IGU0_ISRS_SET(n) (1 << (n))

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#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n))

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#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n)))

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#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n)))

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#define MBOX_IGU0_IER_EN_SET(n) (1 << (n))

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/*

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* Mailbox IGU1 Registers

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*/

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#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204)

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#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205)

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#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206)

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#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207)

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#define MBOX_IGU1_ISRS_SET(n) (1 << (n))

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#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n))

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#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n)))

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#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n)))

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#define MBOX_IGU1_IER_EN_SET(n) (1 << (n))

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/*

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* Mailbox IGU3 Registers

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*/

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#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214)

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#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215)

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#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216)

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#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217)

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#define MBOX_IGU3_ISRS_SET(n) (1 << (n))

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#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n))

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#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n)))

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#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n)))

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#define MBOX_IGU3_IER_EN_SET(n) (1 << (n))

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/*

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* RTHA/TTHA Registers

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*/

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#define RFBI_CFG PPE_REG_ADDR(0x0400)

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#define RBA_CFG0 PPE_REG_ADDR(0x0404)

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#define RBA_CFG1 PPE_REG_ADDR(0x0405)

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#define RCA_CFG0 PPE_REG_ADDR(0x0408)

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#define RCA_CFG1 PPE_REG_ADDR(0x0409)

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#define RDES_CFG0 PPE_REG_ADDR(0x040C)

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#define RDES_CFG1 PPE_REG_ADDR(0x040D)

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#define SFSM_STATE0 PPE_REG_ADDR(0x0410)

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#define SFSM_STATE1 PPE_REG_ADDR(0x0411)

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#define SFSM_DBA0 PPE_REG_ADDR(0x0412)

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#define SFSM_DBA1 PPE_REG_ADDR(0x0413)

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#define SFSM_CBA0 PPE_REG_ADDR(0x0414)

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#define SFSM_CBA1 PPE_REG_ADDR(0x0415)

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#define SFSM_CFG0 PPE_REG_ADDR(0x0416)

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#define SFSM_CFG1 PPE_REG_ADDR(0x0417)

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#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)

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#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)

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#define FFSM_DBA0 PPE_REG_ADDR(0x0508)

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#define FFSM_DBA1 PPE_REG_ADDR(0x0509)

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#define FFSM_CFG0 PPE_REG_ADDR(0x050A)

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#define FFSM_CFG1 PPE_REG_ADDR(0x050B)

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#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)

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#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)

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#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)

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#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)

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/*

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* PPE TC Logic Registers (partial)

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*/

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#define DREG_A_VERSION PPE_REG_ADDR(0x0D00)

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#define DREG_A_CFG PPE_REG_ADDR(0x0D01)

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#define DREG_AT_CTRL PPE_REG_ADDR(0x0D02)

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#define DREG_AT_CB_CFG0 PPE_REG_ADDR(0x0D03)

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#define DREG_AT_CB_CFG1 PPE_REG_ADDR(0x0D04)

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#define DREG_AR_CTRL PPE_REG_ADDR(0x0D08)

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#define DREG_AR_CB_CFG0 PPE_REG_ADDR(0x0D09)

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#define DREG_AR_CB_CFG1 PPE_REG_ADDR(0x0D0A)

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#define DREG_A_UTPCFG PPE_REG_ADDR(0x0D0E)

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#define DREG_A_STATUS PPE_REG_ADDR(0x0D0F)

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#define DREG_AT_CFG0 PPE_REG_ADDR(0x0D20)

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#define DREG_AT_CFG1 PPE_REG_ADDR(0x0D21)

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#define DREG_AT_FB_SIZE0 PPE_REG_ADDR(0x0D22)

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#define DREG_AT_FB_SIZE1 PPE_REG_ADDR(0x0D23)

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#define DREG_AT_CELL0 PPE_REG_ADDR(0x0D24)

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#define DREG_AT_CELL1 PPE_REG_ADDR(0x0D25)

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#define DREG_AT_IDLE_CNT0 PPE_REG_ADDR(0x0D26)

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#define DREG_AT_IDLE_CNT1 PPE_REG_ADDR(0x0D27)

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#define DREG_AT_IDLE0 PPE_REG_ADDR(0x0D28)

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#define DREG_AT_IDLE1 PPE_REG_ADDR(0x0D29)

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#define DREG_AR_CFG0 PPE_REG_ADDR(0x0D60)

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#define DREG_AR_CFG1 PPE_REG_ADDR(0x0D61)

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#define DREG_AR_CELL0 PPE_REG_ADDR(0x0D68)

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#define DREG_AR_CELL1 PPE_REG_ADDR(0x0D69)

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#define DREG_AR_IDLE_CNT0 PPE_REG_ADDR(0x0D6A)

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#define DREG_AR_IDLE_CNT1 PPE_REG_ADDR(0x0D6B)

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#define DREG_AR_AIIDLE_CNT0 PPE_REG_ADDR(0x0D6C)

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#define DREG_AR_AIIDLE_CNT1 PPE_REG_ADDR(0x0D6D)

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#define DREG_AR_BE_CNT0 PPE_REG_ADDR(0x0D6E)

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#define DREG_AR_BE_CNT1 PPE_REG_ADDR(0x0D6F)

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#define DREG_AR_HEC_CNT0 PPE_REG_ADDR(0x0D70)

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#define DREG_AR_HEC_CNT1 PPE_REG_ADDR(0x0D71)

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#define DREG_AR_IDLE0 PPE_REG_ADDR(0x0D74)

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#define DREG_AR_IDLE1 PPE_REG_ADDR(0x0D75)

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#define DREG_AR_CERRN_CNT0 PPE_REG_ADDR(0x0DA0)

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#define DREG_AR_CERRN_CNT1 PPE_REG_ADDR(0x0DA1)

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#define DREG_AR_CERRNP_CNT0 PPE_REG_ADDR(0x0DA2)

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#define DREG_AR_CERRNP_CNT1 PPE_REG_ADDR(0x0DA3)

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#define DREG_AR_CVN_CNT0 PPE_REG_ADDR(0x0DA4)

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#define DREG_AR_CVN_CNT1 PPE_REG_ADDR(0x0DA5)

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#define DREG_AR_CVNP_CNT0 PPE_REG_ADDR(0x0DA6)

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#define DREG_AR_CVNP_CNT1 PPE_REG_ADDR(0x0DA7)

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#define DREG_B0_LADR PPE_REG_ADDR(0x0DA8)

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#define DREG_B1_LADR PPE_REG_ADDR(0x0DA9)

#endif // IFXMIPS_PTM_PPE_COMMON_H

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