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1 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_ppe_amazon_se.h
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver header file (PPE register for Amazon-SE)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23  
24  
25  
26 #ifndef IFXMIPS_PTM_PPE_AMAZON_SE_H
27 #define IFXMIPS_PTM_PPE_AMAZON_SE_H
28  
29  
30  
31 /*
32 * FPI Configuration Bus Register and Memory Address Mapping
33 */
34 #define IFX_PPE (KSEG1 | 0x1E180000)
35 #define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
36 #define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
37 #define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
38 #define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
39 #define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
40 #define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
41 #define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
42 #define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
43 #define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
44 #define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
45 #define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
46 #define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2)))
47 #define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
48 #define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
49  
50 /*
51 * DWORD-Length of Memory Blocks
52 */
53 #define PP32_DEBUG_REG_DWLEN 0x0030
54 #define PPM_INT_REG_DWLEN 0x0010
55 #define PP32_INTERNAL_RES_DWLEN 0x00C0
56 #define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)
57 #define PPE_REG_DWLEN 0x1000
58 #define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)
59 #define PPM_INT_UNIT_DWLEN 0x0100
60 #define PPM_TIMER0_DWLEN 0x0100
61 #define PPM_TASK_IND_REG_DWLEN 0x0100
62 #define PPS_BRK_DWLEN 0x0100
63 #define PPM_TIMER1_DWLEN 0x0100
64 #define SB_RAM0_DWLEN 0x0A00
65 #define SB_RAM1_DWLEN 0x0A00
66 #define QSB_CONF_REG_DWLEN 0x0100
67  
68 /*
69 * PP32 to FPI Address Mapping
70 */
71 #define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x0000) : \
72 (((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) : \
73 (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) : \
74 0))
75  
76 /*
77 * PP32 Debug Control Register
78 */
79 #define NUM_OF_PP32 1
80  
81 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000)
82  
83 #define DBG_CTRL_RESTART 0
84 #define DBG_CTRL_STOP 1
85  
86 #define PP32_CTRL_CMD(n) PP32_DEBUG_REG_ADDR(n, 0x0B00)
87 #define PP32_CTRL_CMD_RESTART (1 << 0)
88 #define PP32_CTRL_CMD_STOP (1 << 1)
89 #define PP32_CTRL_CMD_STEP (1 << 2)
90 #define PP32_CTRL_CMD_BREAKOUT (1 << 3)
91  
92 #define PP32_CTRL_OPT(n) PP32_DEBUG_REG_ADDR(n, 0x0C00)
93 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON (3 << 0)
94 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF (2 << 0)
95 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON (3 << 2)
96 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)
97 #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON (3 << 4)
98 #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF (2 << 4)
99 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON (3 << 6)
100 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF (2 << 6)
101 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n) (*PP32_CTRL_OPT(n) & (1 << 0))
102 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 2))
103 #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 4))
104 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n) (*PP32_CTRL_OPT(n) & (1 << 6))
105  
106 #define PP32_BRK_PC(n, i) PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)
107 #define PP32_BRK_PC_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)
108 #define PP32_BRK_DATA_ADDR(n, i) PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)
109 #define PP32_BRK_DATA_ADDR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)
110 #define PP32_BRK_DATA_VALUE_RD(n, i) PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)
111 #define PP32_BRK_DATA_VALUE_RD_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)
112 #define PP32_BRK_DATA_VALUE_WR(n, i) PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)
113 #define PP32_BRK_DATA_VALUE_WR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)
114 #define PP32_BRK_CONTEXT_MASK(i) (1 << (i))
115 #define PP32_BRK_CONTEXT_MASK_EN (1 << 4)
116 #define PP32_BRK_COMPARE_GREATER_EQUAL (1 << 5) // valid for break data value rd/wr only
117 #define PP32_BRK_COMPARE_LOWER_EQUAL (1 << 6)
118 #define PP32_BRK_COMPARE_EN (1 << 7)
119  
120 #define PP32_BRK_SRC(n) PP32_DEBUG_REG_ADDR(n, 0x0F00)
121 #define PP32_BRK_TRIG(n) PP32_BRK_SRC(n)
122 #define PP32_BRK_GRPi_PCn_ON(i, n) ((3 << ((n) * 2)) << ((i) * 16))
123 #define PP32_BRK_GRPi_PCn_OFF(i, n) ((2 << ((n) * 2)) << ((i) * 16))
124 #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n) ((3 << ((n) * 2 + 4)) << ((i) * 16))
125 #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n) ((2 << ((n) * 2 + 4)) << ((i) * 16))
126 #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))
127 #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))
128 #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))
129 #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))
130 #define PP32_BRK_GRPi_PCn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))
131 #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))
132 #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))
133 #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))
134  
135 #define PP32_CPU_STATUS(n) PP32_DEBUG_REG_ADDR(n, 0x0D00)
136 #define PP32_HALT_STAT(n) PP32_CPU_STATUS(n)
137 #define PP32_DBG_CUR_PC(n) PP32_DEBUG_REG_ADDR(n, 0x0F80)
138 #define PP32_CPU_USER_STOPPED(n) (*PP32_CPU_STATUS(n) & (1 << 0))
139 #define PP32_CPU_USER_BREAKIN_RCV(n) (*PP32_CPU_STATUS(n) & (1 << 1))
140 #define PP32_CPU_USER_BREAKPOINT_MET(n) (*PP32_CPU_STATUS(n) & (1 << 2))
141 #define PP32_CPU_CUR_PC(n) (*PP32_DBG_CUR_PC(n) & 0xFFFF)
142  
143 #define PP32_BREAKPOINT_REASONS(n) PP32_DEBUG_REG_ADDR(n, 0x0A00)
144 #define PP32_BRK_PC_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))
145 #define PP32_BRK_DATA_ADDR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))
146 #define PP32_BRK_DATA_VALUE_RD_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))
147 #define PP32_BRK_DATA_VALUE_WR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))
148 #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))
149 #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))
150 #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))
151 #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))
152 // #define PP32_BRK_CUR_CONTEXT(n) ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)
153 #define PP32_DBG_TASK_NO(n) PP32_DEBUG_REG_ADDR(n, 0x0F81)
154 #define PP32_BRK_CUR_CONTEXT(n) (*PP32_DBG_TASK_NO(n) & 0x03)
155  
156 #define PP32_GP_REG_BASE(n) PP32_DEBUG_REG_ADDR(n, 0x0E00)
157 #define PP32_GP_CONTEXTi_REGn(n, i, j) PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))
158  
159 /*
160 * Share Buffer
161 */
162 #define SB_MST_PRI0 PPE_REG_ADDR(0x0300)
163 #define SB_MST_PRI1 PPE_REG_ADDR(0x0301)
164  
165 /*
166 * EMA Registers
167 */
168 #define EMA_CMDCFG PPE_REG_ADDR(0x0A00)
169 #define EMA_DATACFG PPE_REG_ADDR(0x0A01)
170 #define EMA_CMDCNT PPE_REG_ADDR(0x0A02)
171 #define EMA_DATACNT PPE_REG_ADDR(0x0A03)
172 #define EMA_ISR PPE_REG_ADDR(0x0A04)
173 #define EMA_IER PPE_REG_ADDR(0x0A05)
174 #define EMA_CFG PPE_REG_ADDR(0x0A06)
175 #define EMA_SUBID PPE_REG_ADDR(0x0A07)
176  
177 #define EMA_ALIGNMENT 4
178  
179 /*
180 * Mailbox IGU1 Interrupt
181 */
182 #define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
183  
184  
185  
186 #endif // IFXMIPS_PTM_PPE_AMAZON_SE_H