OpenWrt – Blame information for rev 1

Subversion Repositories:
Rev:
Rev Author Line No. Line
1 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_danube.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23  
24  
25  
26 /*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31  
32 /*
33 * Common Head File
34 */
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <linux/delay.h>
44  
45 /*
46 * Chip Specific Head File
47 */
48 #include "ifxmips_ptm_adsl.h"
49 #include "ifxmips_ptm_fw_danube.h"
50  
51 #include <lantiq_soc.h>
52  
53 /*
54 * ####################################
55 * Definition
56 * ####################################
57 */
58  
59 /*
60 * EMA Settings
61 */
62 #define EMA_CMD_BUF_LEN 0x0040
63 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
64 #define EMA_DATA_BUF_LEN 0x0100
65 #define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
66 #define EMA_WRITE_BURST 0x2
67 #define EMA_READ_BURST 0x2
68  
69  
70  
71 /*
72 * ####################################
73 * Declaration
74 * ####################################
75 */
76  
77 /*
78 * Hardware Init/Uninit Functions
79 */
80 static inline void init_pmu(void);
81 static inline void uninit_pmu(void);
82 static inline void reset_ppe(void);
83 static inline void init_ema(void);
84 static inline void init_mailbox(void);
85 static inline void init_atm_tc(void);
86 static inline void clear_share_buffer(void);
87  
88  
89  
90 /*
91 * ####################################
92 * Local Variable
93 * ####################################
94 */
95  
96  
97 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
98 #define IFX_PMU_MODULE_PPE_TC BIT(21)
99 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
100 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
101 #define IFX_PMU_MODULE_TPE BIT(13)
102 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
103  
104 /*
105 * ####################################
106 * Local Function
107 * ####################################
108 */
109  
110 static inline void init_pmu(void)
111 {
112 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
113 IFX_PMU_MODULE_PPE_TC |
114 IFX_PMU_MODULE_PPE_EMA |
115 IFX_PMU_MODULE_TPE |
116 IFX_PMU_MODULE_DSL_DFE);
117 }
118  
119 static inline void uninit_pmu(void)
120 {
121 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
122 IFX_PMU_MODULE_PPE_TC |
123 IFX_PMU_MODULE_PPE_EMA |
124 IFX_PMU_MODULE_TPE |
125 IFX_PMU_MODULE_DSL_DFE);
126 }
127  
128 static inline void reset_ppe(void)
129 {
130 #ifdef MODULE
131 /*unsigned int etop_cfg;
132 unsigned int etop_mdio_cfg;
133 unsigned int etop_ig_plen_ctrl;
134 unsigned int enet_mac_cfg;
135  
136 etop_cfg = *IFX_PP32_ETOP_CFG;
137 etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
138 etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
139 enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
140  
141 *IFX_PP32_ETOP_CFG &= ~0x03C0;
142  
143 // reset PPE
144 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
145  
146 *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
147 *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
148 *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
149 *IFX_PP32_ETOP_CFG = etop_cfg;*/
150 #endif
151 }
152  
153 static inline void init_ema(void)
154 {
155 // Configure share buffer master selection
156 *SB_MST_SEL |= 0x03;
157  
158 // EMA Settings
159 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
160 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
161 IFX_REG_W32(0x000000FF, EMA_IER);
162 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
163 }
164  
165 static inline void init_mailbox(void)
166 {
167 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
168 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
169 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
170 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
171 }
172  
173 static inline void init_atm_tc(void)
174 {
175 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
176 IFX_REG_W32(0x3C00, DREG_AR_CTRL);
177 IFX_REG_W32(0x0, DREG_AT_IDLE0);
178 IFX_REG_W32(0x0, DREG_AT_IDLE1);
179 IFX_REG_W32(0x0, DREG_AR_IDLE0);
180 IFX_REG_W32(0x0, DREG_AR_IDLE1);
181 IFX_REG_W32(0x0, RFBI_CFG);
182 IFX_REG_W32(0x1600, SFSM_DBA0);
183 IFX_REG_W32(0x1721, SFSM_DBA1);
184 IFX_REG_W32(0x1842, SFSM_CBA0);
185 IFX_REG_W32(0x1853, SFSM_CBA1);
186 IFX_REG_W32(0x14011, SFSM_CFG0);
187 IFX_REG_W32(0x14011, SFSM_CFG1);
188 IFX_REG_W32(0x1864, FFSM_DBA0);
189 IFX_REG_W32(0x1930, FFSM_DBA1);
190 IFX_REG_W32(0x3000C, FFSM_CFG0);
191 IFX_REG_W32(0x3000C, FFSM_CFG1);
192 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
193 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
194 }
195  
196 static inline void clear_share_buffer(void)
197 {
198 volatile u32 *p = SB_RAM0_ADDR(0);
199 unsigned int i;
200  
201 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
202 IFX_REG_W32(0, p++);
203 }
204  
205 /*
206 * Description:
207 * Download PPE firmware binary code.
208 * Input:
209 * src --- u32 *, binary code buffer
210 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
211 * Output:
212 * int --- 0: Success
213 * else: Error Code
214 */
215 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
216 {
217 volatile u32 *dest;
218  
219 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
220 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
221 return -1;
222  
223 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
224 IFX_REG_W32(0x00, CDM_CFG);
225 else
226 IFX_REG_W32(0x04, CDM_CFG);
227  
228 /* copy code */
229 dest = CDM_CODE_MEMORY(0, 0);
230 while ( code_dword_len-- > 0 )
231 IFX_REG_W32(*code_src++, dest++);
232  
233 /* copy data */
234 dest = CDM_DATA_MEMORY(0, 0);
235 while ( data_dword_len-- > 0 )
236 IFX_REG_W32(*data_src++, dest++);
237  
238 return 0;
239 }
240  
241  
242  
243 /*
244 * ####################################
245 * Global Function
246 * ####################################
247 */
248  
249 extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
250 {
251 ASSERT(major != NULL, "pointer is NULL");
252 ASSERT(minor != NULL, "pointer is NULL");
253  
254 *major = FW_VER_ID->major;
255 *minor = FW_VER_ID->minor;
256 }
257  
258 void ifx_ptm_init_chip(void)
259 {
260 init_pmu();
261  
262 reset_ppe();
263  
264 init_ema();
265  
266 init_mailbox();
267  
268 init_atm_tc();
269  
270 clear_share_buffer();
271 }
272  
273 void ifx_ptm_uninit_chip(void)
274 {
275 uninit_pmu();
276 }
277  
278 /*
279 * Description:
280 * Initialize and start up PP32.
281 * Input:
282 * none
283 * Output:
284 * int --- 0: Success
285 * else: Error Code
286 */
287 int ifx_pp32_start(int pp32)
288 {
289 int ret;
290  
291 /* download firmware */
292 ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
293 if ( ret != 0 )
294 return ret;
295  
296 /* run PP32 */
297 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
298  
299 /* idle for a while to let PP32 init itself */
300 udelay(10);
301  
302 return 0;
303 }
304  
305 /*
306 * Description:
307 * Halt PP32.
308 * Input:
309 * none
310 * Output:
311 * none
312 */
313 void ifx_pp32_stop(int pp32)
314 {
315 /* halt PP32 */
316 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
317 }