OpenWrt – Blame information for rev 1
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1 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_ptm_ar9.c |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : PTM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : PTM driver common source file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 07 JUL 2009 Xu Liang Init Version |
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22 | *******************************************************************************/ |
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23 | |||
24 | |||
25 | |||
26 | /* |
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27 | * #################################### |
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28 | * Head File |
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29 | * #################################### |
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30 | */ |
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31 | |||
32 | /* |
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33 | * Common Head File |
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34 | */ |
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35 | #include <linux/kernel.h> |
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36 | #include <linux/module.h> |
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37 | #include <linux/version.h> |
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38 | #include <linux/types.h> |
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39 | #include <linux/errno.h> |
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40 | #include <linux/proc_fs.h> |
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41 | #include <linux/init.h> |
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42 | #include <linux/ioctl.h> |
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43 | #include <asm/delay.h> |
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44 | |||
45 | /* |
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46 | * Chip Specific Head File |
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47 | */ |
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48 | #include "ifxmips_ptm_adsl.h" |
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49 | #include "ifxmips_ptm_fw_ar9.h" |
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50 | |||
51 | #include <lantiq_soc.h> |
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52 | |||
53 | |||
54 | /* |
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55 | * #################################### |
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56 | * Definition |
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57 | * #################################### |
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58 | */ |
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59 | |||
60 | /* |
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61 | * EMA Settings |
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62 | */ |
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63 | #define EMA_CMD_BUF_LEN 0x0040 |
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64 | #define EMA_CMD_BASE_ADDR (0x00001B80 << 2) |
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65 | #define EMA_DATA_BUF_LEN 0x0100 |
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66 | #define EMA_DATA_BASE_ADDR (0x00001C00 << 2) |
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67 | #define EMA_WRITE_BURST 0x2 |
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68 | #define EMA_READ_BURST 0x2 |
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69 | |||
70 | |||
71 | |||
72 | /* |
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73 | * #################################### |
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74 | * Declaration |
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75 | * #################################### |
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76 | */ |
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77 | |||
78 | /* |
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79 | * Hardware Init/Uninit Functions |
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80 | */ |
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81 | static inline void init_pmu(void); |
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82 | static inline void uninit_pmu(void); |
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83 | static inline void reset_ppe(void); |
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84 | static inline void init_ema(void); |
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85 | static inline void init_mailbox(void); |
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86 | static inline void init_atm_tc(void); |
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87 | static inline void clear_share_buffer(void); |
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88 | |||
89 | |||
90 | |||
91 | /* |
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92 | * #################################### |
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93 | * Local Variable |
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94 | * #################################### |
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95 | */ |
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96 | |||
97 | |||
98 | |||
99 | /* |
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100 | * #################################### |
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101 | * Local Function |
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102 | * #################################### |
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103 | */ |
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104 | |||
105 | #define IFX_PMU_MODULE_PPE_SLL01 BIT(19) |
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106 | #define IFX_PMU_MODULE_PPE_TC BIT(21) |
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107 | #define IFX_PMU_MODULE_PPE_EMA BIT(22) |
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108 | #define IFX_PMU_MODULE_PPE_QSB BIT(18) |
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109 | #define IFX_PMU_MODULE_TPE BIT(13) |
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110 | #define IFX_PMU_MODULE_DSL_DFE BIT(9) |
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111 | |||
112 | |||
113 | static inline void init_pmu(void) |
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114 | { |
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115 | ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 | |
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116 | IFX_PMU_MODULE_PPE_TC | |
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117 | IFX_PMU_MODULE_PPE_EMA | |
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118 | IFX_PMU_MODULE_TPE | |
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119 | IFX_PMU_MODULE_DSL_DFE); |
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120 | |||
121 | } |
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122 | |||
123 | static inline void uninit_pmu(void) |
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124 | { |
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125 | ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 | |
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126 | IFX_PMU_MODULE_PPE_TC | |
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127 | IFX_PMU_MODULE_PPE_EMA | |
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128 | IFX_PMU_MODULE_TPE | |
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129 | IFX_PMU_MODULE_DSL_DFE); |
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130 | |||
131 | } |
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132 | |||
133 | static inline void reset_ppe(void) |
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134 | { |
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135 | #ifdef MODULE |
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136 | // reset PPE |
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137 | // ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM); |
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138 | #endif |
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139 | } |
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140 | |||
141 | static inline void init_ema(void) |
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142 | { |
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143 | // Configure share buffer master selection |
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144 | IFX_REG_W32(1, SB_MST_PRI0); |
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145 | IFX_REG_W32(1, SB_MST_PRI1); |
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146 | |||
147 | // EMA Settings |
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148 | IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); |
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149 | IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); |
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150 | IFX_REG_W32(0x000000FF, EMA_IER); |
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151 | IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); |
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152 | } |
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153 | |||
154 | static inline void init_mailbox(void) |
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155 | { |
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156 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); |
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157 | IFX_REG_W32(0x00000000, MBOX_IGU1_IER); |
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158 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); |
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159 | IFX_REG_W32(0x00000000, MBOX_IGU3_IER); |
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160 | } |
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161 | |||
162 | static inline void init_atm_tc(void) |
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163 | { |
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164 | IFX_REG_W32(0x0, RFBI_CFG); |
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165 | IFX_REG_W32(0x1800, SFSM_DBA0); |
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166 | IFX_REG_W32(0x1921, SFSM_DBA1); |
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167 | IFX_REG_W32(0x1A42, SFSM_CBA0); |
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168 | IFX_REG_W32(0x1A53, SFSM_CBA1); |
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169 | IFX_REG_W32(0x14011, SFSM_CFG0); |
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170 | IFX_REG_W32(0x14011, SFSM_CFG1); |
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171 | IFX_REG_W32(0x1000, FFSM_DBA0); |
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172 | IFX_REG_W32(0x1700, FFSM_DBA1); |
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173 | IFX_REG_W32(0x3000C, FFSM_CFG0); |
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174 | IFX_REG_W32(0x3000C, FFSM_CFG1); |
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175 | IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0); |
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176 | IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1); |
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177 | |||
178 | /* |
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179 | * 0. Backup port2 value to temp |
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180 | * 1. Disable CPU port2 in switch (link and learning) |
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181 | * 2. wait for a while |
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182 | * 3. Configure DM register and counter |
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183 | * 4. restore temp to CPU port2 in switch |
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184 | * This code will cause network to stop working if there are heavy |
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185 | * traffic during bootup. This part should be moved to switch and use |
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186 | * the same code as ATM |
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187 | */ |
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188 | { |
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189 | int i; |
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190 | u32 temp; |
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191 | |||
192 | temp = IFX_REG_R32(SW_P2_CTL); |
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193 | |||
194 | IFX_REG_W32(0x40020000, SW_P2_CTL); |
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195 | for (i = 0; i < 200; i++) |
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196 | udelay(2000); |
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197 | |||
198 | IFX_REG_W32(0x00007028, DM_RXCFG); |
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199 | IFX_REG_W32(0x00007028, DS_RXCFG); |
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200 | |||
201 | IFX_REG_W32(0x00001100, DM_RXDB); |
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202 | IFX_REG_W32(0x00001100, DS_RXDB); |
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203 | |||
204 | IFX_REG_W32(0x00001600, DM_RXCB); |
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205 | IFX_REG_W32(0x00001600, DS_RXCB); |
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206 | |||
207 | /* |
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208 | * For dynamic, must reset these counters, |
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209 | * For once initialization, don't need to reset these counters |
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210 | */ |
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211 | IFX_REG_W32(0x0, DM_RXPGCNT); |
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212 | IFX_REG_W32(0x0, DS_RXPGCNT); |
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213 | IFX_REG_W32(0x0, DM_RXPKTCNT); |
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214 | |||
215 | IFX_REG_W32_MASK(0, 0x80000000, DM_RXCFG); |
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216 | IFX_REG_W32_MASK(0, 0x8000, DS_RXCFG); |
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217 | |||
218 | udelay(2000); |
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219 | IFX_REG_W32(temp, SW_P2_CTL); |
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220 | udelay(2000); |
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221 | } |
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222 | } |
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223 | |||
224 | static inline void clear_share_buffer(void) |
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225 | { |
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226 | volatile u32 *p = SB_RAM0_ADDR(0); |
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227 | unsigned int i; |
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228 | |||
229 | for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ ) |
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230 | IFX_REG_W32(0, p++); |
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231 | } |
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232 | |||
233 | /* |
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234 | * Description: |
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235 | * Download PPE firmware binary code. |
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236 | * Input: |
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237 | * src --- u32 *, binary code buffer |
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238 | * dword_len --- unsigned int, binary code length in DWORD (32-bit) |
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239 | * Output: |
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240 | * int --- 0: Success |
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241 | * else: Error Code |
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242 | */ |
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243 | static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) |
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244 | { |
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245 | volatile u32 *dest; |
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246 | |||
247 | if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 |
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248 | || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) |
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249 | return -1; |
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250 | |||
251 | if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) |
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252 | IFX_REG_W32(0x00, CDM_CFG); |
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253 | else |
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254 | IFX_REG_W32(0x04, CDM_CFG); |
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255 | |||
256 | /* copy code */ |
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257 | dest = CDM_CODE_MEMORY(0, 0); |
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258 | while ( code_dword_len-- > 0 ) |
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259 | IFX_REG_W32(*code_src++, dest++); |
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260 | |||
261 | /* copy data */ |
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262 | dest = CDM_DATA_MEMORY(0, 0); |
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263 | while ( data_dword_len-- > 0 ) |
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264 | IFX_REG_W32(*data_src++, dest++); |
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265 | |||
266 | return 0; |
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267 | } |
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268 | |||
269 | |||
270 | |||
271 | /* |
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272 | * #################################### |
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273 | * Global Function |
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274 | * #################################### |
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275 | */ |
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276 | |||
277 | void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor) |
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278 | { |
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279 | ASSERT(major != NULL, "pointer is NULL"); |
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280 | ASSERT(minor != NULL, "pointer is NULL"); |
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281 | |||
282 | *major = FW_VER_ID->major; |
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283 | *minor = FW_VER_ID->minor; |
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284 | } |
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285 | |||
286 | void ifx_ptm_init_chip(void) |
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287 | { |
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288 | init_pmu(); |
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289 | |||
290 | reset_ppe(); |
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291 | |||
292 | init_ema(); |
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293 | |||
294 | init_mailbox(); |
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295 | |||
296 | init_atm_tc(); |
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297 | |||
298 | clear_share_buffer(); |
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299 | } |
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300 | |||
301 | void ifx_ptm_uninit_chip(void) |
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302 | { |
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303 | uninit_pmu(); |
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304 | } |
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305 | |||
306 | /* |
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307 | * Description: |
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308 | * Initialize and start up PP32. |
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309 | * Input: |
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310 | * none |
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311 | * Output: |
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312 | * int --- 0: Success |
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313 | * else: Error Code |
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314 | */ |
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315 | int ifx_pp32_start(int pp32) |
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316 | { |
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317 | int ret; |
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318 | |||
319 | /* download firmware */ |
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320 | ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); |
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321 | if ( ret != 0 ) |
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322 | return ret; |
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323 | |||
324 | /* run PP32 */ |
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325 | IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0)); |
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326 | |||
327 | /* idle for a while to let PP32 init itself */ |
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328 | udelay(10); |
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329 | |||
330 | return 0; |
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331 | } |
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332 | |||
333 | /* |
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334 | * Description: |
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335 | * Halt PP32. |
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336 | * Input: |
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337 | * none |
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338 | * Output: |
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339 | * none |
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340 | */ |
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341 | void ifx_pp32_stop(int pp32) |
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342 | { |
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343 | /* halt PP32 */ |
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344 | IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0)); |
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345 | } |
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346 | |||
347 | int ifx_ptm_proc_read_regs(char *page, char **start, off_t off, int count, int *eof, void *data) |
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348 | { |
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349 | int len = 0; |
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350 | |||
351 | len += sprintf(page + off + len, "EMA:\n"); |
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352 | len += sprintf(page + off + len, " SB_MST_PRI0 - 0x%08X, SB_MST_PRI1 - 0x%08X\n", IFX_REG_R32(SB_MST_PRI0), IFX_REG_R32(SB_MST_PRI1)); |
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353 | len += sprintf(page + off + len, " EMA_CMDCFG - 0x%08X, EMA_DATACFG - 0x%08X\n", IFX_REG_R32(EMA_CMDCFG), IFX_REG_R32(EMA_DATACFG)); |
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354 | len += sprintf(page + off + len, " EMA_IER - 0x%08X, EMA_CFG - 0x%08X\n", IFX_REG_R32(EMA_IER), IFX_REG_R32(EMA_CFG)); |
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355 | |||
356 | len += sprintf(page + off + len, "Mailbox:\n"); |
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357 | len += sprintf(page + off + len, " MBOX_IGU1_IER - 0x%08X, MBOX_IGU1_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU1_IER), IFX_REG_R32(MBOX_IGU1_ISR)); |
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358 | len += sprintf(page + off + len, " MBOX_IGU3_IER - 0x%08X, MBOX_IGU3_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU3_IER), IFX_REG_R32(MBOX_IGU3_ISR)); |
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359 | |||
360 | len += sprintf(page + off + len, "TC:\n"); |
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361 | len += sprintf(page + off + len, " RFBI_CFG - 0x%08X\n", IFX_REG_R32(RFBI_CFG)); |
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362 | len += sprintf(page + off + len, " SFSM_DBA0 - 0x%08X, SFSM_CBA0 - 0x%08X, SFSM_CFG0 - 0x%08X\n", IFX_REG_R32(SFSM_DBA0), IFX_REG_R32(SFSM_CBA0), IFX_REG_R32(SFSM_CFG0)); |
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363 | len += sprintf(page + off + len, " SFSM_DBA1 - 0x%08X, SFSM_CBA1 - 0x%08X, SFSM_CFG1 - 0x%08X\n", IFX_REG_R32(SFSM_DBA1), IFX_REG_R32(SFSM_CBA1), IFX_REG_R32(SFSM_CFG1)); |
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364 | len += sprintf(page + off + len, " FFSM_DBA0 - 0x%08X, FFSM_CFG0 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA0), IFX_REG_R32(FFSM_CFG0), IFX_REG_R32(FFSM_IDLE_HEAD_BC0)); |
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365 | len += sprintf(page + off + len, " FFSM_DBA1 - 0x%08X, FFSM_CFG1 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA1), IFX_REG_R32(FFSM_CFG1), IFX_REG_R32(FFSM_IDLE_HEAD_BC1)); |
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366 | |||
367 | len += sprintf(page + off + len, "DPlus:\n"); |
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368 | len += sprintf(page + off + len, " DM_RXDB - 0x%08X, DM_RXCB - 0x%08X, DM_RXCFG - 0x%08X\n", IFX_REG_R32(DM_RXDB), IFX_REG_R32(DM_RXCB), IFX_REG_R32(DM_RXCFG)); |
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369 | len += sprintf(page + off + len, " DM_RXPGCNT - 0x%08X, DM_RXPKTCNT - 0x%08X\n", IFX_REG_R32(DM_RXPGCNT), IFX_REG_R32(DM_RXPKTCNT)); |
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370 | len += sprintf(page + off + len, " DS_RXDB - 0x%08X, DS_RXCB - 0x%08X, DS_RXCFG - 0x%08X\n", IFX_REG_R32(DS_RXDB), IFX_REG_R32(DS_RXCB), IFX_REG_R32(DS_RXCFG)); |
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371 | len += sprintf(page + off + len, " DS_RXPGCNT - 0x%08X\n", IFX_REG_R32(DS_RXPGCNT)); |
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372 | |||
373 | *eof = 1; |
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374 | |||
375 | return len; |
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376 | } |