OpenWrt – Blame information for rev 1
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1 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_atm_vr9.c |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : ATM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : ATM driver common source file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 07 JUL 2009 Xu Liang Init Version |
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22 | *******************************************************************************/ |
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23 | |||
24 | |||
25 | |||
26 | /* |
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27 | * #################################### |
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28 | * Head File |
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29 | * #################################### |
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30 | */ |
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31 | |||
32 | /* |
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33 | * Common Head File |
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34 | */ |
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35 | #include <linux/kernel.h> |
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36 | #include <linux/module.h> |
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37 | #include <linux/version.h> |
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38 | #include <linux/types.h> |
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39 | #include <linux/errno.h> |
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40 | #include <linux/proc_fs.h> |
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41 | #include <linux/init.h> |
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42 | #include <linux/ioctl.h> |
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43 | #include <asm/delay.h> |
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44 | |||
45 | #include "ifxmips_atm_core.h" |
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46 | #include "ifxmips_atm_fw_vr9.h" |
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47 | |||
48 | #ifdef CONFIG_VR9 |
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49 | |||
50 | #include <lantiq_soc.h> |
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51 | |||
52 | #define IFX_PMU_MODULE_PPE_SLL01 BIT(19) |
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53 | #define IFX_PMU_MODULE_PPE_TC BIT(21) |
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54 | #define IFX_PMU_MODULE_PPE_EMA BIT(22) |
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55 | #define IFX_PMU_MODULE_PPE_QSB BIT(18) |
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56 | #define IFX_PMU_MODULE_AHBS BIT(13) |
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57 | #define IFX_PMU_MODULE_DSL_DFE BIT(9) |
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58 | |||
59 | static inline void vr9_reset_ppe(void) |
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60 | { |
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61 | /*#ifdef MODULE |
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62 | // reset PPE |
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63 | ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM); |
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64 | udelay(1000); |
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65 | ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM); |
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66 | udelay(1000); |
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67 | ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); |
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68 | udelay(1000); |
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69 | *PP32_SRST &= ~0x000303CF; |
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70 | udelay(1000); |
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71 | *PP32_SRST |= 0x000303CF; |
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72 | udelay(1000); |
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73 | #endif*/ |
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74 | } |
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75 | |||
76 | static inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) |
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77 | { |
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78 | unsigned int clr, set; |
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79 | volatile u32 *dest; |
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80 | |||
81 | if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 |
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82 | || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) |
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83 | return -1; |
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84 | |||
85 | clr = pp32 ? 0xF0 : 0x0F; |
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86 | if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) |
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87 | set = pp32 ? (3 << 6): (2 << 2); |
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88 | else |
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89 | set = 0x00; |
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90 | IFX_REG_W32_MASK(clr, set, CDM_CFG); |
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91 | |||
92 | dest = CDM_CODE_MEMORY(pp32, 0); |
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93 | while ( code_dword_len-- > 0 ) |
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94 | IFX_REG_W32(*code_src++, dest++); |
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95 | |||
96 | dest = CDM_DATA_MEMORY(pp32, 0); |
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97 | while ( data_dword_len-- > 0 ) |
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98 | IFX_REG_W32(*data_src++, dest++); |
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99 | |||
100 | return 0; |
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101 | } |
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102 | |||
103 | static void vr9_fw_ver(unsigned int *major, unsigned int *minor) |
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104 | { |
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105 | |||
106 | *major = FW_VER_ID->major; |
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107 | *minor = FW_VER_ID->minor; |
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108 | } |
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109 | |||
110 | static void vr9_init(void) |
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111 | { |
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112 | volatile u32 *p; |
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113 | unsigned int i; |
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114 | |||
115 | /* setup pmu */ |
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116 | ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 | |
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117 | IFX_PMU_MODULE_PPE_TC | |
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118 | IFX_PMU_MODULE_PPE_EMA | |
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119 | IFX_PMU_MODULE_PPE_QSB | |
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120 | IFX_PMU_MODULE_AHBS | |
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121 | IFX_PMU_MODULE_DSL_DFE); |
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122 | |||
123 | vr9_reset_ppe(); |
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124 | |||
125 | /* pdma init */ |
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126 | IFX_REG_W32(0x08, PDMA_CFG); |
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127 | IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG); |
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128 | IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG); |
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129 | |||
130 | /* mailbox init */ |
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131 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); |
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132 | IFX_REG_W32(0x00000000, MBOX_IGU1_IER); |
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133 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); |
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134 | IFX_REG_W32(0x00000000, MBOX_IGU3_IER); |
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135 | |||
136 | /* tc init - clear sync state */ |
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137 | *SFSM_STATE0 = 0; |
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138 | *SFSM_STATE1 = 0; |
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139 | |||
140 | /* init shared buffer */ |
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141 | p = SB_RAM0_ADDR(0); |
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142 | for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ ) |
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143 | IFX_REG_W32(0, p++); |
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144 | |||
145 | p = SB_RAM6_ADDR(0); |
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146 | for ( i = 0; i < SB_RAM6_DWLEN; i++ ) |
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147 | IFX_REG_W32(0, p++); |
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148 | } |
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149 | |||
150 | static void vr9_shutdown(void) |
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151 | { |
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152 | } |
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153 | |||
154 | static int vr9_start(int pp32) |
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155 | { |
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156 | unsigned int mask = 1 << (pp32 << 4); |
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157 | int ret; |
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158 | |||
159 | /* download firmware */ |
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160 | ret = vr9_pp32_download_code(pp32, |
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161 | vr9_fw_bin, sizeof(vr9_fw_bin) / sizeof(*vr9_fw_bin), |
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162 | vr9_fw_data, sizeof(vr9_fw_data) / sizeof(*vr9_fw_data)); |
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163 | if ( ret != 0 ) |
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164 | return ret; |
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165 | |||
166 | /* run PP32 */ |
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167 | IFX_REG_W32_MASK(mask, 0, PP32_FREEZE); |
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168 | |||
169 | /* idle for a while to let PP32 init itself */ |
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170 | udelay(10); |
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171 | |||
172 | return 0; |
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173 | } |
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174 | |||
175 | static void vr9_stop(int pp32) |
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176 | { |
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177 | unsigned int mask = 1 << (pp32 << 4); |
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178 | |||
179 | IFX_REG_W32_MASK(0, mask, PP32_FREEZE); |
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180 | } |
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181 | |||
182 | struct ltq_atm_ops vr9_ops = { |
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183 | .init = vr9_init, |
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184 | .shutdown = vr9_shutdown, |
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185 | .start = vr9_start, |
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186 | .stop = vr9_stop, |
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187 | .fw_ver = vr9_fw_ver, |
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188 | }; |
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189 | |||
190 | #endif |