OpenWrt – Blame information for rev 1
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1 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_atm_ppe_amazon_se.h |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : ATM (ADSL) |
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6 | ** |
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7 | ** DATE : 1 AUG 2005 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : ATM Driver (PPE Registers) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 4 AUG 2005 Xu Liang Initiate Version |
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22 | ** 23 OCT 2006 Xu Liang Add GPL header. |
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23 | ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) |
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24 | *******************************************************************************/ |
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25 | |||
26 | |||
27 | |||
28 | #ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H |
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29 | #define IFXMIPS_ATM_PPE_AMAZON_SE_H |
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30 | |||
31 | |||
32 | |||
33 | /* |
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34 | * FPI Configuration Bus Register and Memory Address Mapping |
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35 | */ |
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36 | #define IFX_PPE (KSEG1 | 0x1E180000) |
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37 | #define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) |
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38 | #define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) |
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39 | #define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) |
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40 | #define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) |
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41 | #define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) |
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42 | #define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) |
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43 | #define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) |
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44 | #define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) |
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45 | #define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) |
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46 | #define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) |
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47 | #define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) |
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48 | #define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2))) |
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49 | #define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2))) |
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50 | #define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) |
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51 | |||
52 | /* |
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53 | * DWORD-Length of Memory Blocks |
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54 | */ |
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55 | #define PP32_DEBUG_REG_DWLEN 0x0030 |
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56 | #define PPM_INT_REG_DWLEN 0x0010 |
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57 | #define PP32_INTERNAL_RES_DWLEN 0x00C0 |
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58 | #define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) |
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59 | #define PPE_REG_DWLEN 0x1000 |
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60 | #define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) |
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61 | #define PPM_INT_UNIT_DWLEN 0x0100 |
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62 | #define PPM_TIMER0_DWLEN 0x0100 |
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63 | #define PPM_TASK_IND_REG_DWLEN 0x0100 |
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64 | #define PPS_BRK_DWLEN 0x0100 |
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65 | #define PPM_TIMER1_DWLEN 0x0100 |
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66 | #define SB_RAM0_DWLEN 0x0A00 |
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67 | #define SB_RAM1_DWLEN 0x0A00 |
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68 | #define QSB_CONF_REG_DWLEN 0x0100 |
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69 | |||
70 | /* |
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71 | * PP32 to FPI Address Mapping |
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72 | */ |
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73 | #define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) : \ |
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74 | (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) : \ |
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75 | 0)) |
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76 | |||
77 | /* |
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78 | * PP32 Debug Control Register |
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79 | */ |
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80 | #define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) |
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81 | |||
82 | #define DBG_CTRL_RESTART 0 |
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83 | #define DBG_CTRL_STOP 1 |
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84 | |||
85 | #define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0D00) |
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86 | #define PP32_BREAKPOINT_REASONS PP32_DEBUG_REG_ADDR(0, 0x0A00) |
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87 | |||
88 | #define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0F00) |
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89 | |||
90 | #define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0F80) |
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91 | |||
92 | #define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0F81) |
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93 | |||
94 | /* |
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95 | * Share Buffer |
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96 | */ |
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97 | #define SB_MST_PRI0 PPE_REG_ADDR(0x0300) |
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98 | #define SB_MST_PRI1 PPE_REG_ADDR(0x0301) |
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99 | |||
100 | /* |
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101 | * EMA Registers |
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102 | */ |
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103 | #define EMA_CMDCFG PPE_REG_ADDR(0x0A00) |
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104 | #define EMA_DATACFG PPE_REG_ADDR(0x0A01) |
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105 | #define EMA_CMDCNT PPE_REG_ADDR(0x0A02) |
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106 | #define EMA_DATACNT PPE_REG_ADDR(0x0A03) |
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107 | #define EMA_ISR PPE_REG_ADDR(0x0A04) |
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108 | #define EMA_IER PPE_REG_ADDR(0x0A05) |
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109 | #define EMA_CFG PPE_REG_ADDR(0x0A06) |
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110 | #define EMA_SUBID PPE_REG_ADDR(0x0A07) |
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111 | |||
112 | #define EMA_ALIGNMENT 4 |
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113 | |||
114 | /* |
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115 | * Mailbox IGU1 Interrupt |
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116 | */ |
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117 | #define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13 |
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118 | |||
119 | |||
120 | |||
121 | #endif // IFXMIPS_ATM_PPE_AMAZON_SE_H |