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1 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_fw_regs_danube.h
4 ** PROJECT : UEIP
5 ** MODULES : ATM (ADSL)
6 **
7 ** DATE : 1 AUG 2005
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM Driver (Firmware Registers)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
25  
26  
27  
28 #ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
29 #define IFXMIPS_ATM_FW_REGS_DANUBE_H
30  
31 #define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
32 #define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
33 #define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
34 #define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
35 #define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
36 #define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
37 #define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
38 #define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
39 #define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
40  
41 #define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
42 #define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
43 #define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
44 #define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
45 #define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
46 #define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
47 #define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
48 #define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
49 #define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
50  
51 #endif