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1 office 1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_fw_regs_common.h
4 ** PROJECT : UEIP
5 ** MODULES : ATM (ADSL)
6 **
7 ** DATE : 1 AUG 2005
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM Driver (Firmware Register Structures)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
25  
26  
27  
28 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
29 #define IFXMIPS_ATM_FW_REGS_COMMON_H
30  
31  
32 #if defined(CONFIG_DANUBE)
33 #include "ifxmips_atm_fw_regs_danube.h"
34 #elif defined(CONFIG_AMAZON_SE)
35 #include "ifxmips_atm_fw_regs_amazon_se.h"
36 #elif defined(CONFIG_AR9)
37 #include "ifxmips_atm_fw_regs_ar9.h"
38 #elif defined(CONFIG_VR9)
39 #include "ifxmips_atm_fw_regs_vr9.h"
40 #else
41 #error Platform is not specified!
42 #endif
43  
44  
45  
46 /*
47 * PPE ATM Cell Header
48 */
49 #if defined(__BIG_ENDIAN)
50 struct uni_cell_header {
51 unsigned int gfc :4;
52 unsigned int vpi :8;
53 unsigned int vci :16;
54 unsigned int pti :3;
55 unsigned int clp :1;
56 };
57 #else
58 struct uni_cell_header {
59 unsigned int clp :1;
60 unsigned int pti :3;
61 unsigned int vci :16;
62 unsigned int vpi :8;
63 unsigned int gfc :4;
64 };
65 #endif // defined(__BIG_ENDIAN)
66  
67 /*
68 * Inband Header and Trailer
69 */
70 #if defined(__BIG_ENDIAN)
71 struct rx_inband_trailer {
72 /* 0 - 3h */
73 unsigned int uu :8;
74 unsigned int cpi :8;
75 unsigned int stw_res1:4;
76 unsigned int stw_clp :1;
77 unsigned int stw_ec :1;
78 unsigned int stw_uu :1;
79 unsigned int stw_cpi :1;
80 unsigned int stw_ovz :1;
81 unsigned int stw_mfl :1;
82 unsigned int stw_usz :1;
83 unsigned int stw_crc :1;
84 unsigned int stw_il :1;
85 unsigned int stw_ra :1;
86 unsigned int stw_res2:2;
87 /* 4 - 7h */
88 unsigned int gfc :4;
89 unsigned int vpi :8;
90 unsigned int vci :16;
91 unsigned int pti :3;
92 unsigned int clp :1;
93 };
94  
95 struct tx_inband_header {
96 /* 0 - 3h */
97 unsigned int gfc :4;
98 unsigned int vpi :8;
99 unsigned int vci :16;
100 unsigned int pti :3;
101 unsigned int clp :1;
102 /* 4 - 7h */
103 unsigned int uu :8;
104 unsigned int cpi :8;
105 unsigned int pad :8;
106 unsigned int res1 :8;
107 };
108 #else
109 struct rx_inband_trailer {
110 /* 0 - 3h */
111 unsigned int stw_res2:2;
112 unsigned int stw_ra :1;
113 unsigned int stw_il :1;
114 unsigned int stw_crc :1;
115 unsigned int stw_usz :1;
116 unsigned int stw_mfl :1;
117 unsigned int stw_ovz :1;
118 unsigned int stw_cpi :1;
119 unsigned int stw_uu :1;
120 unsigned int stw_ec :1;
121 unsigned int stw_clp :1;
122 unsigned int stw_res1:4;
123 unsigned int cpi :8;
124 unsigned int uu :8;
125 /* 4 - 7h */
126 unsigned int clp :1;
127 unsigned int pti :3;
128 unsigned int vci :16;
129 unsigned int vpi :8;
130 unsigned int gfc :4;
131 };
132  
133 struct tx_inband_header {
134 /* 0 - 3h */
135 unsigned int clp :1;
136 unsigned int pti :3;
137 unsigned int vci :16;
138 unsigned int vpi :8;
139 unsigned int gfc :4;
140 /* 4 - 7h */
141 unsigned int res1 :8;
142 unsigned int pad :8;
143 unsigned int cpi :8;
144 unsigned int uu :8;
145 };
146 #endif // defined(__BIG_ENDIAN)
147  
148 /*
149 * MIB Table Maintained by Firmware
150 */
151 struct wan_mib_table {
152 u32 res1;
153 u32 wrx_drophtu_cell;
154 u32 wrx_dropdes_pdu;
155 u32 wrx_correct_pdu;
156 u32 wrx_err_pdu;
157 u32 wrx_dropdes_cell;
158 u32 wrx_correct_cell;
159 u32 wrx_err_cell;
160 u32 wrx_total_byte;
161 u32 res2;
162 u32 wtx_total_pdu;
163 u32 wtx_total_cell;
164 u32 wtx_total_byte;
165 };
166  
167 /*
168 * Host-PPE Communication Data Structure
169 */
170  
171 #if defined(__BIG_ENDIAN)
172 struct fw_ver_id {
173 unsigned int family :4;
174 unsigned int fwtype :4;
175 unsigned int interface :4;
176 unsigned int fwmode :4;
177 unsigned int major :8;
178 unsigned int minor :8;
179 };
180  
181 struct wrx_queue_config {
182 /* 0h */
183 unsigned int res2 :27;
184 unsigned int dmach :4;
185 unsigned int errdp :1;
186 /* 1h */
187 unsigned int oversize :16;
188 unsigned int undersize :16;
189 /* 2h */
190 unsigned int res1 :16;
191 unsigned int mfs :16;
192 /* 3h */
193 unsigned int uumask :8;
194 unsigned int cpimask :8;
195 unsigned int uuexp :8;
196 unsigned int cpiexp :8;
197 };
198  
199 struct wrx_queue_context {
200 /* 0h */
201 unsigned int curr_len :16;
202 unsigned int res0 :12;
203 unsigned int mfs :1;
204 unsigned int ec :1;
205 unsigned int clp1 :1;
206 unsigned int aal5dp :1;
207  
208 /* 1h */
209 unsigned int intcrc;
210  
211 /* 2h, 3h */
212 unsigned int curr_des0;
213 unsigned int curr_des1;
214  
215 /* 4h - 0xE */
216 unsigned int res1[11];
217  
218 unsigned int last_dword;
219 };
220  
221 struct wtx_port_config {
222 unsigned int res1 :27;
223 unsigned int qid :4;
224 unsigned int qsben :1;
225 };
226  
227 struct wtx_queue_config {
228 unsigned int res1 :16;
229 unsigned int same_vc_qmap:8;
230 unsigned int res2 :1;
231 unsigned int sbid :1;
232 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
233 unsigned int res3 :1;
234 unsigned int qsben :1;
235 };
236  
237 struct wrx_desc_context {
238 unsigned int dmach_wrptr : 16;
239 unsigned int dmach_rdptr : 16;
240  
241 unsigned int res0 : 16;
242 unsigned int dmach_fcnt : 16;
243  
244 unsigned int res1 : 11;
245 unsigned int desbuf_wrptr : 5;
246 unsigned int res2 : 11;
247 unsigned int desbuf_rdptr : 5;
248  
249 unsigned int res3 : 27;
250 unsigned int desbuf_vcnt : 5;
251 };
252  
253 struct wrx_dma_channel_config {
254 /* 0h */
255 unsigned int res1 :1;
256 unsigned int mode :2;
257 unsigned int rlcfg :1;
258 unsigned int desba :28;
259 /* 1h */
260 unsigned int chrl :16;
261 unsigned int clp1th :16;
262 /* 2h */
263 unsigned int deslen :16;
264 unsigned int vlddes :16;
265 };
266  
267 struct wtx_dma_channel_config {
268 /* 0h */
269 unsigned int res2 :1;
270 unsigned int mode :2;
271 unsigned int res3 :1;
272 unsigned int desba :28;
273 /* 1h */
274 unsigned int res1 :32;
275 /* 2h */
276 unsigned int deslen :16;
277 unsigned int vlddes :16;
278 };
279  
280 struct htu_entry {
281 unsigned int res1 :1;
282 unsigned int clp :1;
283 unsigned int pid :2;
284 unsigned int vpi :8;
285 unsigned int vci :16;
286 unsigned int pti :3;
287 unsigned int vld :1;
288 };
289  
290 struct htu_mask {
291 unsigned int set :1;
292 unsigned int clp :1;
293 unsigned int pid_mask :2;
294 unsigned int vpi_mask :8;
295 unsigned int vci_mask :16;
296 unsigned int pti_mask :3;
297 unsigned int clear :1;
298 };
299  
300 struct htu_result {
301 unsigned int res1 :12;
302 unsigned int cellid :4;
303 unsigned int res2 :5;
304 unsigned int type :1;
305 unsigned int ven :1;
306 unsigned int res3 :5;
307 unsigned int qid :4;
308 };
309  
310 struct rx_descriptor {
311 /* 0 - 3h */
312 unsigned int own :1;
313 unsigned int c :1;
314 unsigned int sop :1;
315 unsigned int eop :1;
316 unsigned int res1 :3;
317 unsigned int byteoff :2;
318 unsigned int res2 :2;
319 unsigned int id :4;
320 unsigned int err :1;
321 unsigned int datalen :16;
322 /* 4 - 7h */
323 unsigned int res3 :4;
324 unsigned int dataptr :28;
325 };
326  
327 struct tx_descriptor {
328 /* 0 - 3h */
329 unsigned int own :1;
330 unsigned int c :1;
331 unsigned int sop :1;
332 unsigned int eop :1;
333 unsigned int byteoff :5;
334 unsigned int res1 :5;
335 unsigned int iscell :1;
336 unsigned int clp :1;
337 unsigned int datalen :16;
338 /* 4 - 7h */
339 unsigned int res2 :4;
340 unsigned int dataptr :28;
341 };
342 #else
343 struct wrx_queue_config {
344 /* 0h */
345 unsigned int errdp :1;
346 unsigned int dmach :4;
347 unsigned int res2 :27;
348 /* 1h */
349 unsigned int undersize :16;
350 unsigned int oversize :16;
351 /* 2h */
352 unsigned int mfs :16;
353 unsigned int res1 :16;
354 /* 3h */
355 unsigned int cpiexp :8;
356 unsigned int uuexp :8;
357 unsigned int cpimask :8;
358 unsigned int uumask :8;
359 };
360  
361 struct wtx_port_config {
362 unsigned int qsben :1;
363 unsigned int qid :4;
364 unsigned int res1 :27;
365 };
366  
367 struct wtx_queue_config {
368 unsigned int qsben :1;
369 unsigned int res3 :1;
370 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
371 unsigned int sbid :1;
372 unsigned int res2 :1;
373 unsigned int same_vc_qmap:8;
374 unsigned int res1 :16;
375 };
376  
377 struct wrx_dma_channel_config
378 {
379 /* 0h */
380 unsigned int desba :28;
381 unsigned int rlcfg :1;
382 unsigned int mode :2;
383 unsigned int res1 :1;
384 /* 1h */
385 unsigned int clp1th :16;
386 unsigned int chrl :16;
387 /* 2h */
388 unsigned int vlddes :16;
389 unsigned int deslen :16;
390 };
391  
392 struct wtx_dma_channel_config {
393 /* 0h */
394 unsigned int desba :28;
395 unsigned int res3 :1;
396 unsigned int mode :2;
397 unsigned int res2 :1;
398 /* 1h */
399 unsigned int res1 :32;
400 /* 2h */
401 unsigned int vlddes :16;
402 unsigned int deslen :16;
403 };
404  
405 struct rx_descriptor {
406 /* 4 - 7h */
407 unsigned int dataptr :28;
408 unsigned int res3 :4;
409 /* 0 - 3h */
410 unsigned int datalen :16;
411 unsigned int err :1;
412 unsigned int id :4;
413 unsigned int res2 :2;
414 unsigned int byteoff :2;
415 unsigned int res1 :3;
416 unsigned int eop :1;
417 unsigned int sop :1;
418 unsigned int c :1;
419 unsigned int own :1;
420 };
421  
422 struct tx_descriptor {
423 /* 4 - 7h */
424 unsigned int dataptr :28;
425 unsigned int res2 :4;
426 /* 0 - 3h */
427 unsigned int datalen :16;
428 unsigned int clp :1;
429 unsigned int iscell :1;
430 unsigned int res1 :5;
431 unsigned int byteoff :5;
432 unsigned int eop :1;
433 unsigned int sop :1;
434 unsigned int c :1;
435 unsigned int own :1;
436 };
437 #endif // defined(__BIG_ENDIAN)
438  
439 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
440 #if defined(__BIG_ENDIAN)
441  
442 struct Retx_adsl_ppe_intf {
443 unsigned int res0_0 : 16;
444 unsigned int dtu_sid : 8;
445 unsigned int dtu_timestamp : 8;
446  
447 unsigned int res1_0 : 16;
448 unsigned int local_time : 8;
449 unsigned int res1_1 : 5;
450 unsigned int is_last_cw : 1;
451 unsigned int reinit_flag : 1;
452 unsigned int is_bad_cw : 1;
453 };
454  
455 struct Retx_adsl_ppe_intf_rec {
456  
457 unsigned int local_time : 8;
458 unsigned int res1_1 : 5;
459 unsigned int is_last_cw : 1;
460 unsigned int reinit_flag : 1;
461 unsigned int is_bad_cw : 1;
462  
463 unsigned int dtu_sid : 8;
464 unsigned int dtu_timestamp : 8;
465  
466 };
467  
468 struct Retx_mode_cfg {
469 unsigned int res0 :8;
470 unsigned int invld_range :8; // used for rejecting the too late arrival of the retransmitted DTU
471 unsigned int buff_size :8; // the total number of cells in playout buffer is 32 * buff_size
472 unsigned int res1 :7;
473 unsigned int retx_en :1;
474 };
475  
476 struct Retx_Tsync_cfg {
477 unsigned int fw_alpha :16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)
478 unsigned int sync_inp :16; // reserved
479 };
480  
481 struct Retx_Td_cfg {
482 unsigned int res0 :8;
483 unsigned int td_max :8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
484 unsigned int res1 :8;
485 unsigned int td_min :8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
486 };
487  
488 struct Retx_MIB_Timer_cfg {
489 unsigned int ticks_per_sec : 16;
490 unsigned int tick_cycle : 16;
491 };
492  
493 struct DTU_stat_info {
494 unsigned int complete : 1;
495 unsigned int bad : 1;
496 unsigned int res0_0 : 14;
497 unsigned int time_stamp : 8;
498 unsigned int cell_cnt : 8;
499  
500 unsigned int dtu_rd_ptr : 16;
501 unsigned int dtu_wr_ptr : 16;
502 };
503  
504 struct Retx_ctrl_field {
505 unsigned int res0 : 1;
506  
507 unsigned int l2_drop : 1;
508 unsigned int res1 : 13;
509 unsigned int retx : 1;
510  
511 unsigned int dtu_sid : 8;
512 unsigned int cell_sid : 8;
513 };
514  
515 #else
516 #error Little Endian is not supported yet.
517 #endif
518  
519 struct dsl_param {
520 unsigned int update_flag; // 00
521 unsigned int res0; // 04
522 unsigned int MinDelayrt; // 08
523 unsigned int MaxDelayrt; // 0C
524 unsigned int res1; // 10
525 unsigned int res2; // 14
526 unsigned int RetxEnable; // 18
527 unsigned int ServiceSpecificReTx; // 1C
528 unsigned int res3; // 20
529 unsigned int ReTxPVC; // 24
530 unsigned int res4; // 28
531 unsigned int res5; // 2C
532 unsigned int res6; // 30
533 unsigned int res7; // 34
534 unsigned int res8; // 38
535 unsigned int res9; // 3C
536 unsigned int res10; // 40
537 unsigned int res11; // 44
538 unsigned int res12; // 48
539 unsigned int res13; // 4C
540 unsigned int RxDtuCorruptedCNT; // 50
541 unsigned int RxRetxDtuUnCorrectedCNT;// 54
542 unsigned int RxLastEFB; // 58
543 unsigned int RxDtuCorrectedCNT; // 5C
544 };
545 #endif
546  
547  
548  
549 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H