OpenWrt – Blame information for rev 1
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1 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_atm_core.h |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : ATM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : ATM driver header file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 17 JUN 2009 Xu Liang Init Version |
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22 | *******************************************************************************/ |
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23 | |||
24 | #ifndef IFXMIPS_ATM_CORE_H |
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25 | #define IFXMIPS_ATM_CORE_H |
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26 | |||
27 | |||
28 | #define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) |
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29 | #define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) |
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30 | #define CONFIG_IFXMIPS_DSL_CPE_MEI |
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31 | #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) |
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32 | #define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) |
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33 | #define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) |
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34 | #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) |
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35 | |||
36 | struct ltq_atm_ops { |
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37 | void (*init)(void); |
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38 | void (*shutdown)(void); |
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39 | |||
40 | int (*start)(int pp32); |
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41 | void (*stop)(int pp32); |
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42 | |||
43 | void (*fw_ver)(unsigned int *major, unsigned int *minor); |
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44 | }; |
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45 | |||
46 | #include <linux/atomic.h> |
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47 | #include <lantiq_atm.h> |
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48 | |||
49 | /* |
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50 | * #################################### |
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51 | * Definition |
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52 | * #################################### |
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53 | */ |
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54 | |||
55 | /* |
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56 | * Compile Options |
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57 | */ |
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58 | |||
59 | #define ENABLE_DEBUG 1 |
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60 | |||
61 | #define ENABLE_ASSERT 1 |
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62 | |||
63 | #define INLINE |
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64 | |||
65 | #define DEBUG_DUMP_SKB 1 |
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66 | |||
67 | #define DEBUG_QOS 1 |
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68 | |||
69 | #define DISABLE_QOS_WORKAROUND 0 |
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70 | |||
71 | #define ENABLE_DBG_PROC 1 |
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72 | |||
73 | #define ENABLE_FW_PROC 1 |
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74 | |||
75 | #ifdef CONFIG_IFX_ATM_TASKLET |
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76 | #define ENABLE_TASKLET 1 |
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77 | #endif |
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78 | |||
79 | #ifdef CONFIG_IFX_ATM_RETX |
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80 | #define ENABLE_ATM_RETX 1 |
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81 | #endif |
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82 | |||
83 | #if defined(CONFIG_DSL_MEI_CPE_DRV) && !defined(CONFIG_IFXMIPS_DSL_CPE_MEI) |
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84 | #define CONFIG_IFXMIPS_DSL_CPE_MEI 1 |
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85 | #endif |
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86 | |||
87 | /* |
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88 | * Debug/Assert/Error Message |
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89 | */ |
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90 | |||
91 | #define ifx_atm_dbg_enable 1 |
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92 | |||
93 | #define DBG_ENABLE_MASK_ERR (1 << 0) |
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94 | #define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1) |
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95 | #define DBG_ENABLE_MASK_ASSERT (1 << 2) |
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96 | #define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8) |
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97 | #define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9) |
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98 | #define DBG_ENABLE_MASK_DUMP_QOS (1 << 10) |
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99 | #define DBG_ENABLE_MASK_DUMP_INIT (1 << 11) |
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100 | #define DBG_ENABLE_MASK_MAC_SWAP (1 << 12) |
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101 | #define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP) |
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102 | |||
103 | #if defined(ENABLE_ASSERT) && ENABLE_ASSERT |
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104 | #define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 ) |
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105 | #else |
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106 | #define ASSERT(cond, format, arg...) |
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107 | #endif |
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108 | |||
109 | |||
110 | /* |
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111 | * Constants |
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112 | */ |
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113 | #define DEFAULT_TX_LINK_RATE 3200 // in cells |
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114 | |||
115 | /* |
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116 | * ATM Port, QSB Queue, DMA RX/TX Channel Parameters |
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117 | */ |
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118 | #define ATM_PORT_NUMBER 2 |
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119 | #define MAX_QUEUE_NUMBER 16 |
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120 | #define OAM_RX_QUEUE 15 |
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121 | #define QSB_RESERVE_TX_QUEUE 0 |
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122 | #define FIRST_QSB_QID 1 |
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123 | #define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID) |
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124 | #define MAX_RX_DMA_CHANNEL_NUMBER 8 |
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125 | #define MAX_TX_DMA_CHANNEL_NUMBER 16 |
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126 | #define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT |
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127 | #define DESC_ALIGNMENT 8 |
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128 | #define DEFAULT_RX_HUNT_BITTH 4 |
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129 | |||
130 | /* |
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131 | * RX DMA Channel Allocation |
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132 | */ |
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133 | #define RX_DMA_CH_OAM 0 |
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134 | #define RX_DMA_CH_AAL 1 |
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135 | #define RX_DMA_CH_TOTAL 2 |
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136 | #define RX_DMA_CH_OAM_DESC_LEN 32 |
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137 | #define RX_DMA_CH_OAM_BUF_SIZE ((CELL_SIZE + 14) & ~15) |
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138 | #define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48) |
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139 | |||
140 | /* |
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141 | * OAM Constants |
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142 | */ |
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143 | #define OAM_HTU_ENTRY_NUMBER 3 |
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144 | #define OAM_F4_SEG_HTU_ENTRY 0 |
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145 | #define OAM_F4_TOT_HTU_ENTRY 1 |
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146 | #define OAM_F5_HTU_ENTRY 2 |
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147 | #define OAM_F4_CELL_ID 0 |
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148 | #define OAM_F5_CELL_ID 15 |
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149 | #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX |
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150 | #undef OAM_HTU_ENTRY_NUMBER |
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151 | #define OAM_HTU_ENTRY_NUMBER 4 |
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152 | #define OAM_ARQ_HTU_ENTRY 3 |
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153 | #endif |
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154 | |||
155 | /* |
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156 | * RX Frame Definitions |
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157 | */ |
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158 | #define MAX_RX_PACKET_ALIGN_BYTES 3 |
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159 | #define MAX_RX_PACKET_PADDING_BYTES 3 |
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160 | #define RX_INBAND_TRAILER_LENGTH 8 |
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161 | #define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES) |
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162 | |||
163 | /* |
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164 | * TX Frame Definitions |
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165 | */ |
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166 | #define MAX_TX_HEADER_ALIGN_BYTES 12 |
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167 | #define MAX_TX_PACKET_ALIGN_BYTES 3 |
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168 | #define MAX_TX_PACKET_PADDING_BYTES 3 |
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169 | #define TX_INBAND_HEADER_LENGTH 8 |
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170 | #define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES) |
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171 | |||
172 | #define CELL_SIZE ATM_AAL0_SDU |
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173 | |||
174 | #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX |
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175 | #define RETX_PLAYOUT_BUFFER_ORDER 6 |
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176 | #define RETX_PLAYOUT_BUFFER_SIZE (PAGE_SIZE * (1 << RETX_PLAYOUT_BUFFER_ORDER)) |
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177 | #define RETX_PLAYOUT_FW_BUFF_SIZE (RETX_PLAYOUT_BUFFER_SIZE / (32 * 56 /* cell size */)) |
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178 | #define RETX_POLLING_INTERVAL (HZ / 100 > 0 ? HZ / 100 : 1) |
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179 | #endif |
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180 | |||
181 | typedef struct { |
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182 | unsigned int h; |
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183 | unsigned int l; |
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184 | } ppe_u64_t; |
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185 | |||
186 | struct port { |
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187 | unsigned int tx_max_cell_rate; |
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188 | unsigned int tx_current_cell_rate; |
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189 | |||
190 | struct atm_dev *dev; |
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191 | }; |
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192 | |||
193 | struct connection { |
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194 | struct atm_vcc *vcc; |
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195 | |||
196 | volatile struct tx_descriptor *tx_desc; |
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197 | unsigned int tx_desc_pos; |
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198 | struct sk_buff **tx_skb; |
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199 | spinlock_t lock; |
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200 | |||
201 | unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */ |
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202 | unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */ |
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203 | |||
204 | unsigned int port; |
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205 | }; |
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206 | |||
207 | struct atm_priv_data { |
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208 | unsigned long conn_table; |
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209 | struct connection conn[MAX_PVC_NUMBER]; |
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210 | |||
211 | volatile struct rx_descriptor *aal_desc; |
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212 | unsigned int aal_desc_pos; |
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213 | |||
214 | volatile struct rx_descriptor *oam_desc; |
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215 | unsigned char *oam_buf; |
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216 | unsigned int oam_desc_pos; |
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217 | |||
218 | struct port port[ATM_PORT_NUMBER]; |
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219 | |||
220 | unsigned int wrx_pdu; /* successfully received AAL5 packet */ |
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221 | unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */ |
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222 | unsigned int wtx_pdu; /* successfully transmitted AAL5 packet */ |
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223 | unsigned int wtx_err_pdu; /* error AAL5 packet */ |
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224 | unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */ |
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225 | |||
226 | unsigned int wrx_oam; /* successfully received OAM cell */ |
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227 | unsigned int wrx_drop_oam; /* OAM cell dropped by driver on RX */ |
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228 | unsigned int wtx_oam; /* successfully transmitted OAM cell */ |
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229 | unsigned int wtx_err_oam; /* error during transmiting OAM cell */ |
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230 | unsigned int wtx_drop_oam; /* OAM cell dropped by driver on TX */ |
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231 | |||
232 | ppe_u64_t wrx_total_byte; |
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233 | ppe_u64_t wtx_total_byte; |
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234 | unsigned int prev_wrx_total_byte; |
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235 | unsigned int prev_wtx_total_byte; |
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236 | |||
237 | void *aal_desc_base; |
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238 | void *oam_desc_base; |
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239 | void *oam_buf_base; |
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240 | void *tx_desc_base; |
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241 | void *tx_skb_base; |
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242 | }; |
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243 | |||
244 | #include "ifxmips_atm_ppe_common.h" |
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245 | #include "ifxmips_atm_fw_regs_common.h" |
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246 | |||
247 | #endif |