OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | From 0329cf7965956a5a7044827e0ce88ae8d5150e54 Mon Sep 17 00:00:00 2001 |
2 | From: Xiangfu <xiangfu@openmobilefree.net> |
||
3 | Date: Fri, 12 Oct 2012 09:46:58 +0800 |
||
4 | Subject: [PATCH 1/6] qi_lb60: add nand spl support |
||
5 | |||
6 | The JZ4740 CPU can load 8KB from two different addresses: |
||
7 | 1. the normal area up to 8KB starting from NAND flash address 0x00000000 |
||
8 | 2. the backup area up to 8KB starting from NAND flash address 0x00002000 |
||
9 | |||
10 | Signed-off-by: Xiangfu <xiangfu@openmobilefree.net> |
||
11 | --- |
||
12 | Makefile | 12 +++ |
||
13 | arch/mips/cpu/xburst/Makefile | 7 +- |
||
14 | arch/mips/cpu/xburst/cpu.c | 4 + |
||
15 | arch/mips/cpu/xburst/jz4740.c | 82 +++++++---------- |
||
16 | arch/mips/cpu/xburst/spl/Makefile | 47 ++++++++++ |
||
17 | arch/mips/cpu/xburst/spl/start.S | 63 +++++++++++++ |
||
18 | board/qi/qi_lb60/Makefile | 4 + |
||
19 | board/qi/qi_lb60/qi_lb60-spl.c | 30 +++++++ |
||
20 | board/qi/qi_lb60/qi_lb60.c | 8 +- |
||
21 | board/qi/qi_lb60/u-boot-spl.lds | 61 +++++++++++++ |
||
22 | drivers/mtd/nand/jz4740_nand.c | 39 ++++++++- |
||
23 | include/configs/qi_lb60.h | 175 ++++++++++++++++++------------------- |
||
24 | 12 files changed, 386 insertions(+), 146 deletions(-) |
||
25 | create mode 100644 arch/mips/cpu/xburst/spl/Makefile |
||
26 | create mode 100644 arch/mips/cpu/xburst/spl/start.S |
||
27 | create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c |
||
28 | create mode 100644 board/qi/qi_lb60/u-boot-spl.lds |
||
29 | |||
30 | diff --git a/Makefile b/Makefile |
||
31 | index 34d9075..a22778e 100644 |
||
32 | --- a/Makefile |
||
33 | +++ b/Makefile |
||
34 | @@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin |
||
35 | endif |
||
36 | endif |
||
37 | |||
38 | +ifeq ($(CPU),xburst) |
||
39 | +ALL-y += $(obj)u-boot-xburst.bin |
||
40 | +endif |
||
41 | + |
||
42 | all: $(ALL-y) $(SUBDIR_EXAMPLES) |
||
43 | |||
44 | $(obj)u-boot.dtb: $(obj)u-boot |
||
45 | @@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin |
||
46 | endif |
||
47 | endif |
||
48 | |||
49 | +ifeq ($(CPU),xburst) |
||
50 | +$(obj)u-boot-xburst.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin |
||
51 | + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync bs=8192 count=1 |
||
52 | + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=8192 count=1 |
||
53 | + tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=16384 count=1 |
||
54 | + cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@ |
||
55 | +endif |
||
56 | + |
||
57 | ifeq ($(CONFIG_SANDBOX),y) |
||
58 | GEN_UBOOT = \ |
||
59 | cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ |
||
60 | diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile |
||
61 | index b1f2ae4..ec35e55 100644 |
||
62 | --- a/arch/mips/cpu/xburst/Makefile |
||
63 | +++ b/arch/mips/cpu/xburst/Makefile |
||
64 | @@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk |
||
65 | |||
66 | LIB = $(obj)lib$(CPU).o |
||
67 | |||
68 | +COBJS-y = cpu.o jz_serial.o |
||
69 | + |
||
70 | +ifneq ($(CONFIG_SPL_BUILD),y) |
||
71 | START = start.o |
||
72 | -SOBJS-y = |
||
73 | -COBJS-y = cpu.o timer.o jz_serial.o |
||
74 | +COBJS-y += timer.o |
||
75 | +endif |
||
76 | |||
77 | COBJS-$(CONFIG_JZ4740) += jz4740.o |
||
78 | |||
79 | diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c |
||
80 | index ddcbfaa..1432838 100644 |
||
81 | --- a/arch/mips/cpu/xburst/cpu.c |
||
82 | +++ b/arch/mips/cpu/xburst/cpu.c |
||
83 | @@ -42,6 +42,8 @@ |
||
84 | : \ |
||
85 | : "i" (op), "R" (*(unsigned char *)(addr))) |
||
86 | |||
87 | +#ifndef CONFIG_SPL_BUILD |
||
88 | + |
||
89 | void __attribute__((weak)) _machine_restart(void) |
||
90 | { |
||
91 | struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE; |
||
92 | @@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) |
||
93 | cache_op(Hit_Invalidate_D, addr); |
||
94 | } |
||
95 | |||
96 | +#endif |
||
97 | + |
||
98 | void flush_icache_all(void) |
||
99 | { |
||
100 | u32 addr, t = 0; |
||
101 | diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c |
||
102 | index c0b9817..8816aa3 100644 |
||
103 | --- a/arch/mips/cpu/xburst/jz4740.c |
||
104 | +++ b/arch/mips/cpu/xburst/jz4740.c |
||
105 | @@ -32,31 +32,19 @@ int disable_interrupts(void) |
||
106 | return 0; |
||
107 | } |
||
108 | |||
109 | -/* |
||
110 | - * PLL output clock = EXTAL * NF / (NR * NO) |
||
111 | - * NF = FD + 2, NR = RD + 2 |
||
112 | - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) |
||
113 | - */ |
||
114 | void pll_init(void) |
||
115 | { |
||
116 | struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; |
||
117 | |||
118 | - register unsigned int cfcr, plcr1; |
||
119 | - int n2FR[33] = { |
||
120 | - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, |
||
121 | - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, |
||
122 | - 9 |
||
123 | - }; |
||
124 | - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ |
||
125 | - int nf, pllout2; |
||
126 | + register unsigned int cfcr, plcr; |
||
127 | + unsigned int nf, pllout2; |
||
128 | |||
129 | cfcr = CPM_CPCCR_CLKOEN | |
||
130 | - CPM_CPCCR_PCS | |
||
131 | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | |
||
132 | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | |
||
133 | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | |
||
134 | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | |
||
135 | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); |
||
136 | + (0 << CPM_CPCCR_CDIV_BIT) | |
||
137 | + (2 << CPM_CPCCR_HDIV_BIT) | |
||
138 | + (2 << CPM_CPCCR_PDIV_BIT) | |
||
139 | + (2 << CPM_CPCCR_MDIV_BIT) | |
||
140 | + (2 << CPM_CPCCR_LDIV_BIT); |
||
141 | |||
142 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? |
||
143 | CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); |
||
144 | @@ -65,15 +53,18 @@ void pll_init(void) |
||
145 | writel(pllout2 / 48000000 - 1, &cpm->uhccdr); |
||
146 | |||
147 | nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; |
||
148 | - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
||
149 | + plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
||
150 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
||
151 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
||
152 | - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
||
153 | + (0x32 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
||
154 | CPM_CPPCR_PLLEN; /* enable PLL */ |
||
155 | |||
156 | /* init PLL */ |
||
157 | writel(cfcr, &cpm->cpccr); |
||
158 | - writel(plcr1, &cpm->cppcr); |
||
159 | + writel(plcr, &cpm->cppcr); |
||
160 | + |
||
161 | + while (!(readl(&cpm->cppcr) & CPM_CPPCR_PLLS)) |
||
162 | + ; |
||
163 | } |
||
164 | |||
165 | void sdram_init(void) |
||
166 | @@ -92,26 +83,12 @@ void sdram_init(void) |
||
167 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
||
168 | }; |
||
169 | |||
170 | - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
||
171 | - |
||
172 | cpu_clk = CONFIG_SYS_CPU_SPEED; |
||
173 | - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
||
174 | + mem_clk = 84000000; |
||
175 | |||
176 | writel(0, &emc->bcr); /* Disable bus release */ |
||
177 | writew(0, &emc->rtcsr); /* Disable clock for counting */ |
||
178 | |||
179 | - /* Fault DMCR value for mode register setting*/ |
||
180 | -#define SDRAM_ROW0 11 |
||
181 | -#define SDRAM_COL0 8 |
||
182 | -#define SDRAM_BANK40 0 |
||
183 | - |
||
184 | - dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) | |
||
185 | - ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) | |
||
186 | - (SDRAM_BANK40 << EMC_DMCR_BA_BIT) | |
||
187 | - (SDRAM_BW16 << EMC_DMCR_BW_BIT) | |
||
188 | - EMC_DMCR_EPIN | |
||
189 | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
||
190 | - |
||
191 | /* Basic DMCR value */ |
||
192 | dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) | |
||
193 | ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) | |
||
194 | @@ -128,31 +105,31 @@ void sdram_init(void) |
||
195 | if (tmp > 11) |
||
196 | tmp = 11; |
||
197 | dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT; |
||
198 | - tmp = SDRAM_RCD / ns; |
||
199 | |||
200 | + tmp = SDRAM_RCD / ns; |
||
201 | if (tmp > 3) |
||
202 | tmp = 3; |
||
203 | dmcr |= tmp << EMC_DMCR_RCD_BIT; |
||
204 | - tmp = SDRAM_TPC / ns; |
||
205 | |||
206 | + tmp = SDRAM_TPC / ns; |
||
207 | if (tmp > 7) |
||
208 | tmp = 7; |
||
209 | dmcr |= tmp << EMC_DMCR_TPC_BIT; |
||
210 | - tmp = SDRAM_TRWL / ns; |
||
211 | |||
212 | + tmp = SDRAM_TRWL / ns; |
||
213 | if (tmp > 3) |
||
214 | tmp = 3; |
||
215 | dmcr |= tmp << EMC_DMCR_TRWL_BIT; |
||
216 | - tmp = (SDRAM_TRAS + SDRAM_TPC) / ns; |
||
217 | |||
218 | + tmp = (SDRAM_TRAS + SDRAM_TPC) / ns; |
||
219 | if (tmp > 14) |
||
220 | tmp = 14; |
||
221 | dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT; |
||
222 | |||
223 | /* SDRAM mode value */ |
||
224 | - sdmode = EMC_SDMR_BT_SEQ | |
||
225 | - EMC_SDMR_OM_NORMAL | |
||
226 | - EMC_SDMR_BL_4 | |
||
227 | + sdmode = EMC_SDMR_BT_SEQ | |
||
228 | + EMC_SDMR_OM_NORMAL | |
||
229 | + EMC_SDMR_BL_4 | |
||
230 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
||
231 | |||
232 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
||
233 | @@ -172,8 +149,8 @@ void sdram_init(void) |
||
234 | if (tmp > 0xff) |
||
235 | tmp = 0xff; |
||
236 | writew(tmp, &emc->rtcor); |
||
237 | + |
||
238 | writew(0, &emc->rtcnt); |
||
239 | - /* Divisor is 64, CKO/64 */ |
||
240 | writew(EMC_RTCSR_CKS_64, &emc->rtcsr); |
||
241 | |||
242 | /* Wait for number of auto-refresh cycles */ |
||
243 | @@ -182,13 +159,17 @@ void sdram_init(void) |
||
244 | ; |
||
245 | |||
246 | /* Stage 3. Mode Register Set */ |
||
247 | + dmcr0 = (11 << EMC_DMCR_RA_BIT) | |
||
248 | + (8 << EMC_DMCR_CA_BIT) | |
||
249 | + (0 << EMC_DMCR_BA_BIT) | |
||
250 | + EMC_DMCR_EPIN | |
||
251 | + (SDRAM_BW16 << EMC_DMCR_BW_BIT) | |
||
252 | + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
||
253 | writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); |
||
254 | writeb(0, JZ4740_EMC_SDMR0 | sdmode); |
||
255 | |||
256 | /* Set back to basic DMCR value */ |
||
257 | writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); |
||
258 | - |
||
259 | - /* everything is ok now */ |
||
260 | } |
||
261 | |||
262 | DECLARE_GLOBAL_DATA_PTR; |
||
263 | @@ -232,9 +213,10 @@ void rtc_init(void) |
||
264 | phys_size_t initdram(int board_type) |
||
265 | { |
||
266 | struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE; |
||
267 | - u32 dmcr; |
||
268 | - u32 rows, cols, dw, banks; |
||
269 | - ulong size; |
||
270 | + |
||
271 | + unsigned int dmcr; |
||
272 | + unsigned int rows, cols, dw, banks; |
||
273 | + unsigned long size; |
||
274 | |||
275 | dmcr = readl(&emc->dmcr); |
||
276 | rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); |
||
277 | diff --git a/arch/mips/cpu/xburst/spl/Makefile b/arch/mips/cpu/xburst/spl/Makefile |
||
278 | new file mode 100644 |
||
279 | index 0000000..f45e8c8 |
||
280 | --- /dev/null |
||
281 | +++ b/arch/mips/cpu/xburst/spl/Makefile |
||
282 | @@ -0,0 +1,47 @@ |
||
283 | +# |
||
284 | +# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net> |
||
285 | +# |
||
286 | +# See file CREDITS for list of people who contributed to this |
||
287 | +# project. |
||
288 | +# |
||
289 | +# This program is free software; you can redistribute it and/or |
||
290 | +# modify it under the terms of the GNU General Public License as |
||
291 | +# published by the Free Software Foundation; either version 2 of |
||
292 | +# the License, or (at your option) any later version. |
||
293 | +# |
||
294 | +# This program is distributed in the hope that it will be useful, |
||
295 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
296 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
297 | +# GNU General Public License for more details. |
||
298 | +# |
||
299 | +# You should have received a copy of the GNU General Public License |
||
300 | +# along with this program; if not, write to the Free Software |
||
301 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||
302 | +# MA 02111-1307 USA |
||
303 | +# |
||
304 | + |
||
305 | +include $(TOPDIR)/config.mk |
||
306 | + |
||
307 | +LIB = $(obj)lib$(CPU).o |
||
308 | + |
||
309 | +START = start.o |
||
310 | +SOBJS-y = |
||
311 | +COBJS-y = |
||
312 | + |
||
313 | +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) |
||
314 | +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) |
||
315 | +START := $(addprefix $(obj),$(START)) |
||
316 | + |
||
317 | +all: $(obj).depend $(START) $(LIB) |
||
318 | + |
||
319 | +$(LIB): $(OBJS) |
||
320 | + $(call cmd_link_o_target, $(OBJS)) |
||
321 | + |
||
322 | +######################################################################### |
||
323 | + |
||
324 | +# defines $(obj).depend target |
||
325 | +include $(SRCTREE)/rules.mk |
||
326 | + |
||
327 | +sinclude $(obj).depend |
||
328 | + |
||
329 | +######################################################################### |
||
330 | diff --git a/arch/mips/cpu/xburst/spl/start.S b/arch/mips/cpu/xburst/spl/start.S |
||
331 | new file mode 100644 |
||
332 | index 0000000..e31c4c8 |
||
333 | --- /dev/null |
||
334 | +++ b/arch/mips/cpu/xburst/spl/start.S |
||
335 | @@ -0,0 +1,63 @@ |
||
336 | +/* |
||
337 | + * Copyright (c) 2010 Xiangfu Liu <xiangfu@openmobilefree.net> |
||
338 | + * |
||
339 | + * See file CREDITS for list of people who contributed to this |
||
340 | + * project. |
||
341 | + * |
||
342 | + * This program is free software; you can redistribute it and/or |
||
343 | + * modify it under the terms of the GNU General Public License as |
||
344 | + * published by the Free Software Foundation; either version 3 of |
||
345 | + * the License, or (at your option) any later version. |
||
346 | + * |
||
347 | + * This program is distributed in the hope that it will be useful, |
||
348 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
349 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
350 | + * GNU General Public License for more details. |
||
351 | + * |
||
352 | + * You should have received a copy of the GNU General Public License |
||
353 | + * along with this program; if not, write to the Free Software |
||
354 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||
355 | + * MA 02111-1307 USA |
||
356 | + */ |
||
357 | + |
||
358 | +#include <config.h> |
||
359 | +#include <version.h> |
||
360 | +#include <asm/regdef.h> |
||
361 | +#include <asm/mipsregs.h> |
||
362 | +#include <asm/addrspace.h> |
||
363 | +#include <asm/cacheops.h> |
||
364 | + |
||
365 | +#include <asm/jz4740.h> |
||
366 | + |
||
367 | + .set noreorder |
||
368 | + |
||
369 | + .globl _start |
||
370 | + .text |
||
371 | +_start: |
||
372 | + .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */ |
||
373 | +reset: |
||
374 | + /* |
||
375 | + * STATUS register |
||
376 | + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 |
||
377 | + */ |
||
378 | + li t0, 0x0040FC04 |
||
379 | + mtc0 t0, CP0_STATUS |
||
380 | + /* |
||
381 | + * CAUSE register |
||
382 | + * IV=1, use the specical interrupt vector (0x200) |
||
383 | + */ |
||
384 | + li t1, 0x00800000 |
||
385 | + mtc0 t1, CP0_CAUSE |
||
386 | + |
||
387 | + bal 1f |
||
388 | + nop |
||
389 | + .word _GLOBAL_OFFSET_TABLE_ |
||
390 | +1: |
||
391 | + move gp, ra |
||
392 | + lw t1, 0(ra) |
||
393 | + move gp, t1 |
||
394 | + |
||
395 | + la sp, 0x80004000 |
||
396 | + la t9, nand_spl_boot |
||
397 | + j t9 |
||
398 | + nop |
||
399 | diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile |
||
400 | index 5dae11b..e399246 100644 |
||
401 | --- a/board/qi/qi_lb60/Makefile |
||
402 | +++ b/board/qi/qi_lb60/Makefile |
||
403 | @@ -22,7 +22,11 @@ include $(TOPDIR)/config.mk |
||
404 | |||
405 | LIB = $(obj)lib$(BOARD).o |
||
406 | |||
407 | +ifeq ($(CONFIG_SPL_BUILD),y) |
||
408 | +COBJS := $(BOARD)-spl.o |
||
409 | +else |
||
410 | COBJS := $(BOARD).o |
||
411 | +endif |
||
412 | |||
413 | SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) |
||
414 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) |
||
415 | diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c |
||
416 | new file mode 100644 |
||
417 | index 0000000..3fe3fa3 |
||
418 | --- /dev/null |
||
419 | +++ b/board/qi/qi_lb60/qi_lb60-spl.c |
||
420 | @@ -0,0 +1,30 @@ |
||
421 | +/* |
||
422 | + * Authors: Xiangfu Liu <xiangfu@openmobilefree.cc> |
||
423 | + * |
||
424 | + * This program is free software; you can redistribute it and/or |
||
425 | + * modify it under the terms of the GNU General Public License |
||
426 | + * as published by the Free Software Foundation; either version |
||
427 | + * 3 of the License, or (at your option) any later version. |
||
428 | + */ |
||
429 | + |
||
430 | +#include <common.h> |
||
431 | +#include <nand.h> |
||
432 | +#include <asm/io.h> |
||
433 | +#include <asm/jz4740.h> |
||
434 | + |
||
435 | +void nand_spl_boot(void) |
||
436 | +{ |
||
437 | + __gpio_as_sdram_16bit_4720(); |
||
438 | + __gpio_as_uart0(); |
||
439 | + __gpio_jtag_to_uart0(); |
||
440 | + |
||
441 | + serial_init(); |
||
442 | + |
||
443 | + pll_init(); |
||
444 | + sdram_init(); |
||
445 | + |
||
446 | + nand_init(); |
||
447 | + |
||
448 | + puts("\nQi LB60 SPL: Starting U-Boot ...\n"); |
||
449 | + nand_boot(); |
||
450 | +} |
||
451 | diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c |
||
452 | index d975209..3bd4e2f 100644 |
||
453 | --- a/board/qi/qi_lb60/qi_lb60.c |
||
454 | +++ b/board/qi/qi_lb60/qi_lb60.c |
||
455 | @@ -1,5 +1,5 @@ |
||
456 | /* |
||
457 | - * Authors: Xiangfu Liu <xiangfu@sharism.cc> |
||
458 | + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> |
||
459 | * |
||
460 | * This program is free software; you can redistribute it and/or |
||
461 | * modify it under the terms of the GNU General Public License |
||
462 | @@ -97,8 +97,10 @@ int board_early_init_f(void) |
||
463 | /* U-Boot common routines */ |
||
464 | int checkboard(void) |
||
465 | { |
||
466 | - printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n", |
||
467 | - gd->cpu_clk / 1000000); |
||
468 | + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC)\n"); |
||
469 | + printf(" CPU: %ld\n", gd->cpu_clk); |
||
470 | + printf(" MEM: %ld\n", gd->mem_clk); |
||
471 | + printf(" DEV: %ld\n", gd->dev_clk); |
||
472 | |||
473 | return 0; |
||
474 | } |
||
475 | diff --git a/board/qi/qi_lb60/u-boot-spl.lds b/board/qi/qi_lb60/u-boot-spl.lds |
||
476 | new file mode 100644 |
||
477 | index 0000000..930537f |
||
478 | --- /dev/null |
||
479 | +++ b/board/qi/qi_lb60/u-boot-spl.lds |
||
480 | @@ -0,0 +1,61 @@ |
||
481 | +/* |
||
482 | + * (C) Copyright 2012 Xiangfu Liu <xiangfu@openmobilefree.net> |
||
483 | + * |
||
484 | + * This program is free software; you can redistribute it and/or |
||
485 | + * modify it under the terms of the GNU General Public License as |
||
486 | + * published by the Free Software Foundation; either version 2 of |
||
487 | + * the License, or (at your option) any later version. |
||
488 | + * |
||
489 | + * This program is distributed in the hope that it will be useful, |
||
490 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
491 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
492 | + * GNU General Public License for more details. |
||
493 | + * |
||
494 | + * You should have received a copy of the GNU General Public License |
||
495 | + * along with this program; if not, write to the Free Software |
||
496 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||
497 | + * MA 02111-1307 USA |
||
498 | + */ |
||
499 | + |
||
500 | +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") |
||
501 | + |
||
502 | +OUTPUT_ARCH(mips) |
||
503 | +ENTRY(_start) |
||
504 | +SECTIONS |
||
505 | +{ |
||
506 | + . = 0x80000000; |
||
507 | + . = ALIGN(4); |
||
508 | + .text : |
||
509 | + { |
||
510 | + *(.text) |
||
511 | + } |
||
512 | + |
||
513 | + . = ALIGN(4); |
||
514 | + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||
515 | + |
||
516 | + . = ALIGN(4); |
||
517 | + .data : { *(.data) } |
||
518 | + |
||
519 | + . = ALIGN(4); |
||
520 | + .sdata : { *(.sdata) } |
||
521 | + |
||
522 | + _gp = ALIGN(16); |
||
523 | + |
||
524 | + __got_start = .; |
||
525 | + .got : { *(.got) } |
||
526 | + __got_end = .; |
||
527 | + |
||
528 | + . = .; |
||
529 | + __u_boot_cmd_start = .; |
||
530 | + .u_boot_cmd : { *(.u_boot_cmd) } |
||
531 | + __u_boot_cmd_end = .; |
||
532 | + |
||
533 | + uboot_end_data = .; |
||
534 | + num_got_entries = (__got_end - __got_start) >> 2; |
||
535 | + |
||
536 | + . = ALIGN(4); |
||
537 | + .sbss : { *(.sbss) } |
||
538 | + .bss : { *(.bss) } |
||
539 | + uboot_end = .; |
||
540 | +} |
||
541 | +ASSERT(uboot_end <= 0x80002000, "NAND bootstrap too big"); |
||
542 | diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c |
||
543 | index 3ec34f3..24a4921 100644 |
||
544 | --- a/drivers/mtd/nand/jz4740_nand.c |
||
545 | +++ b/drivers/mtd/nand/jz4740_nand.c |
||
546 | @@ -15,6 +15,9 @@ |
||
547 | #include <asm/io.h> |
||
548 | #include <asm/jz4740.h> |
||
549 | |||
550 | +#ifdef CONFIG_SPL_BUILD |
||
551 | +#define printf(s) puts(s) |
||
552 | +#endif |
||
553 | #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000) |
||
554 | #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) |
||
555 | #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) |
||
556 | @@ -176,7 +179,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, |
||
557 | for (k = 0; k < 9; k++) |
||
558 | writeb(read_ecc[k], &emc->nfpar[k]); |
||
559 | } |
||
560 | - /* Set PRDY */ |
||
561 | + |
||
562 | writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr); |
||
563 | |||
564 | /* Wait for completion */ |
||
565 | @@ -184,7 +187,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, |
||
566 | status = readl(&emc->nfints); |
||
567 | } while (!(status & EMC_NFINTS_DECF)); |
||
568 | |||
569 | - /* disable ecc */ |
||
570 | + /* Disable ECC */ |
||
571 | writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr); |
||
572 | |||
573 | /* Check decoding */ |
||
574 | @@ -192,7 +195,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, |
||
575 | return 0; |
||
576 | |||
577 | if (status & EMC_NFINTS_UNCOR) { |
||
578 | - printf("uncorrectable ecc\n"); |
||
579 | + printf("JZ4740 uncorrectable ECC\n"); |
||
580 | return -1; |
||
581 | } |
||
582 | |||
583 | @@ -230,6 +233,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, |
||
584 | return errcnt; |
||
585 | } |
||
586 | |||
587 | +#ifdef CONFIG_SPL_BUILD |
||
588 | +static void jz_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
||
589 | +{ |
||
590 | + int i; |
||
591 | + struct nand_chip *this = mtd->priv; |
||
592 | + |
||
593 | +#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \ |
||
594 | + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2) |
||
595 | + for (i = 0; i < len; i += 2) |
||
596 | + buf[i] = readw(this->IO_ADDR_R); |
||
597 | +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \ |
||
598 | + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2) |
||
599 | + for (i = 0; i < len; i++) |
||
600 | + buf[i] = readb(this->IO_ADDR_R); |
||
601 | +#else |
||
602 | + #error JZ4740_NANDBOOT_CFG not defined or wrong |
||
603 | +#endif |
||
604 | +} |
||
605 | + |
||
606 | +static uint8_t jz_nand_read_byte(struct mtd_info *mtd) |
||
607 | +{ |
||
608 | + struct nand_chip *this = mtd->priv; |
||
609 | + return readb(this->IO_ADDR_R); |
||
610 | +} |
||
611 | +#endif |
||
612 | + |
||
613 | /* |
||
614 | * Main initialization routine |
||
615 | */ |
||
616 | @@ -254,6 +283,10 @@ int board_nand_init(struct nand_chip *nand) |
||
617 | nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; |
||
618 | nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; |
||
619 | nand->ecc.layout = &qi_lb60_ecclayout_2gb; |
||
620 | +#ifdef CONFIG_SPL_BUILD |
||
621 | + nand->read_byte = jz_nand_read_byte; |
||
622 | + nand->read_buf = jz_nand_read_buf; |
||
623 | +#endif |
||
624 | nand->chip_delay = 50; |
||
625 | nand->options = NAND_USE_FLASH_BBT; |
||
626 | |||
627 | diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h |
||
628 | index 4bb5bbc..7bff444 100644 |
||
629 | --- a/include/configs/qi_lb60.h |
||
630 | +++ b/include/configs/qi_lb60.h |
||
631 | @@ -1,5 +1,5 @@ |
||
632 | /* |
||
633 | - * Authors: Xiangfu Liu <xiangfu.z@gmail.com> |
||
634 | + * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> |
||
635 | * |
||
636 | * This program is free software; you can redistribute it and/or |
||
637 | * modify it under the terms of the GNU General Public License |
||
638 | @@ -14,7 +14,6 @@ |
||
639 | #define CONFIG_SYS_LITTLE_ENDIAN |
||
640 | #define CONFIG_JZSOC /* Jz SoC */ |
||
641 | #define CONFIG_JZ4740 /* Jz4740 SoC */ |
||
642 | -#define CONFIG_NAND_JZ4740 |
||
643 | |||
644 | #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ |
||
645 | #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ |
||
646 | @@ -24,24 +23,43 @@ |
||
647 | #define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */ |
||
648 | #define CONFIG_BAUDRATE 57600 |
||
649 | |||
650 | +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) |
||
651 | +#define CONFIG_BOOTDELAY 0 |
||
652 | +#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" |
||
653 | +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x280000;bootm" |
||
654 | + |
||
655 | +/* |
||
656 | + * Miscellaneous configurable options |
||
657 | + */ |
||
658 | +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
||
659 | +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
||
660 | +#define CONFIG_SYS_LOAD_ADDR 0x80600000 |
||
661 | +#define CONFIG_SYS_MEMTEST_START 0x80100000 |
||
662 | +#define CONFIG_SYS_MEMTEST_END 0x80A00000 |
||
663 | +#define CONFIG_SYS_TEXT_BASE 0x80100000 |
||
664 | +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||
665 | + |
||
666 | +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
||
667 | +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) |
||
668 | + |
||
669 | +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||
670 | +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||
671 | + |
||
672 | +#define CONFIG_SYS_LONGHELP |
||
673 | +#define CONFIG_SYS_MAXARGS 16 |
||
674 | +#define CONFIG_SYS_PROMPT "NanoNote# " |
||
675 | + |
||
676 | #define CONFIG_SKIP_LOWLEVEL_INIT |
||
677 | #define CONFIG_BOARD_EARLY_INIT_F |
||
678 | #define CONFIG_SYS_NO_FLASH |
||
679 | #define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */ |
||
680 | -#define CONFIG_ENV_OVERWRITE |
||
681 | - |
||
682 | -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) |
||
683 | -#define CONFIG_BOOTDELAY 0 |
||
684 | -#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" |
||
685 | -#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" |
||
686 | |||
687 | /* |
||
688 | - * Command line configuration. |
||
689 | + * Command line configuration |
||
690 | */ |
||
691 | #define CONFIG_CMD_BOOTD /* bootd */ |
||
692 | #define CONFIG_CMD_CONSOLE /* coninfo */ |
||
693 | #define CONFIG_CMD_ECHO /* echo arguments */ |
||
694 | - |
||
695 | #define CONFIG_CMD_LOADB /* loadb */ |
||
696 | #define CONFIG_CMD_LOADS /* loads */ |
||
697 | #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ |
||
698 | @@ -58,45 +76,16 @@ |
||
699 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||
700 | |||
701 | /* |
||
702 | - * Miscellaneous configurable options |
||
703 | - */ |
||
704 | -#define CONFIG_SYS_MAXARGS 16 |
||
705 | -#define CONFIG_SYS_LONGHELP |
||
706 | -#define CONFIG_SYS_PROMPT "NanoNote# " |
||
707 | -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||
708 | -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||
709 | - |
||
710 | -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
||
711 | -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) |
||
712 | - |
||
713 | -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
||
714 | -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
||
715 | -#define CONFIG_SYS_LOAD_ADDR 0x80600000 |
||
716 | -#define CONFIG_SYS_MEMTEST_START 0x80100000 |
||
717 | -#define CONFIG_SYS_MEMTEST_END 0x80800000 |
||
718 | - |
||
719 | -/* |
||
720 | - * Environment |
||
721 | + * NAND driver configuration |
||
722 | */ |
||
723 | -#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */ |
||
724 | - |
||
725 | -#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||
726 | -/* |
||
727 | - * if board nand flash is 1GB, set to 1 |
||
728 | - * if board nand flash is 2GB, set to 2 |
||
729 | - * for change the PAGE_SIZE and BLOCK_SIZE |
||
730 | - * will delete when there is no 1GB flash |
||
731 | - */ |
||
732 | -#define NANONOTE_NAND_SIZE 2 |
||
733 | - |
||
734 | -#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE) |
||
735 | -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10) |
||
736 | -/* nand bad block was marked at this page in a block, start from 0 */ |
||
737 | +#define CONFIG_NAND_JZ4740 |
||
738 | +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 |
||
739 | +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 << 10) |
||
740 | +/* NAND bad block was marked at this page in a block, start from 0 */ |
||
741 | #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127 |
||
742 | #define CONFIG_SYS_NAND_PAGE_COUNT 128 |
||
743 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
||
744 | -/* ECC offset position in oob area, default value is 6 if it isn't defined */ |
||
745 | -#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE) |
||
746 | +#define CONFIG_SYS_NAND_ECC_POS 12 |
||
747 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
||
748 | #define CONFIG_SYS_NAND_ECCBYTES 9 |
||
749 | #define CONFIG_SYS_NAND_ECCPOS \ |
||
750 | @@ -115,10 +104,9 @@ |
||
751 | #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE |
||
752 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||
753 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ |
||
754 | -#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000 |
||
755 | |||
756 | /* |
||
757 | - * IPL (Initial Program Loader, integrated inside CPU) |
||
758 | + * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU) |
||
759 | * Will load first 8k from NAND (SPL) into cache and execute it from there. |
||
760 | * |
||
761 | * SPL (Secondary Program Loader) |
||
762 | @@ -130,77 +118,88 @@ |
||
763 | * NUB (NAND U-Boot) |
||
764 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started |
||
765 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
||
766 | - * |
||
767 | */ |
||
768 | + |
||
769 | +/* |
||
770 | + * NAND SPL configuration |
||
771 | + */ |
||
772 | +#define CONFIG_SPL |
||
773 | +#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||
774 | +#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||
775 | +#define CONFIG_SPL_NAND_LOAD |
||
776 | +#define CONFIG_SPL_NAND_SIMPLE |
||
777 | +#define CONFIG_SPL_NAND_SUPPORT |
||
778 | +#define CONFIG_SPL_TEXT_BASE 0x80000000 |
||
779 | +#define CONFIG_SPL_START_S_PATH "arch/mips/cpu/xburst/spl" |
||
780 | + |
||
781 | +#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||
782 | +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
||
783 | +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 |
||
784 | + |
||
785 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */ |
||
786 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
||
787 | -/* Start NUB from this addr*/ |
||
788 | + /* Start NUB from this addr */ |
||
789 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS (32 << 10) /* Offset of NUB */ |
||
790 | +#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */ |
||
791 | |||
792 | /* |
||
793 | - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) |
||
794 | + * Environment configuration |
||
795 | */ |
||
796 | -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */ |
||
797 | -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ |
||
798 | - |
||
799 | +#define CONFIG_ENV_OVERWRITE |
||
800 | +#define CONFIG_ENV_IS_IN_NAND |
||
801 | #define CONFIG_ENV_SIZE (4 << 10) |
||
802 | #define CONFIG_ENV_OFFSET \ |
||
803 | (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE) |
||
804 | #define CONFIG_ENV_OFFSET_REDUND \ |
||
805 | (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE) |
||
806 | |||
807 | -#define CONFIG_SYS_TEXT_BASE 0x80100000 |
||
808 | -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||
809 | - |
||
810 | /* |
||
811 | - * SDRAM Info. |
||
812 | + * CPU cache configuration |
||
813 | */ |
||
814 | -#define CONFIG_NR_DRAM_BANKS 1 |
||
815 | +#define CONFIG_SYS_DCACHE_SIZE 16384 |
||
816 | +#define CONFIG_SYS_ICACHE_SIZE 16384 |
||
817 | +#define CONFIG_SYS_CACHELINE_SIZE 32 |
||
818 | |||
819 | /* |
||
820 | - * Cache Configuration |
||
821 | + * SDRAM configuration |
||
822 | */ |
||
823 | -#define CONFIG_SYS_DCACHE_SIZE 16384 |
||
824 | -#define CONFIG_SYS_ICACHE_SIZE 16384 |
||
825 | -#define CONFIG_SYS_CACHELINE_SIZE 32 |
||
826 | +#define CONFIG_NR_DRAM_BANKS 1 |
||
827 | + |
||
828 | +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ |
||
829 | +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
||
830 | +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
||
831 | +#define SDRAM_COL 9 /* Column address: 8 to 12 */ |
||
832 | +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
||
833 | +#define SDRAM_TRAS 45 /* RAS# Active Time */ |
||
834 | +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
||
835 | +#define SDRAM_TPC 20 /* RAS# Precharge Time */ |
||
836 | +#define SDRAM_TRWL 7 /* Write Latency Time */ |
||
837 | +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ |
||
838 | |||
839 | /* |
||
840 | - * GPIO definition |
||
841 | + * GPIO configuration |
||
842 | */ |
||
843 | -#define GPIO_LCD_CS (2 * 32 + 21) |
||
844 | -#define GPIO_AMP_EN (3 * 32 + 4) |
||
845 | +#define GPIO_LCD_CS (2 * 32 + 21) |
||
846 | +#define GPIO_AMP_EN (3 * 32 + 4) |
||
847 | |||
848 | -#define GPIO_SDPW_EN (3 * 32 + 2) |
||
849 | -#define GPIO_SD_DETECT (3 * 32 + 0) |
||
850 | +#define GPIO_SDPW_EN (3 * 32 + 2) |
||
851 | +#define GPIO_SD_DETECT (3 * 32 + 0) |
||
852 | |||
853 | -#define GPIO_BUZZ_PWM (3 * 32 + 27) |
||
854 | -#define GPIO_USB_DETECT (3 * 32 + 28) |
||
855 | +#define GPIO_BUZZ_PWM (3 * 32 + 27) |
||
856 | +#define GPIO_USB_DETECT (3 * 32 + 28) |
||
857 | |||
858 | -#define GPIO_AUDIO_POP (1 * 32 + 29) |
||
859 | -#define GPIO_COB_TEST (1 * 32 + 30) |
||
860 | +#define GPIO_AUDIO_POP (1 * 32 + 29) |
||
861 | +#define GPIO_COB_TEST (1 * 32 + 30) |
||
862 | |||
863 | #define GPIO_KEYOUT_BASE (2 * 32 + 10) |
||
864 | -#define GPIO_KEYIN_BASE (3 * 32 + 18) |
||
865 | -#define GPIO_KEYIN_8 (3 * 32 + 26) |
||
866 | +#define GPIO_KEYIN_BASE (3 * 32 + 18) |
||
867 | +#define GPIO_KEYIN_8 (3 * 32 + 26) |
||
868 | |||
869 | -#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ |
||
870 | +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ |
||
871 | #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ |
||
872 | |||
873 | #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ |
||
874 | #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ |
||
875 | #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ |
||
876 | |||
877 | -/* SDRAM paramters */ |
||
878 | -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ |
||
879 | -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
||
880 | -#define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
||
881 | -#define SDRAM_COL 9 /* Column address: 8 to 12 */ |
||
882 | -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
||
883 | - |
||
884 | -/* SDRAM Timings, unit: ns */ |
||
885 | -#define SDRAM_TRAS 45 /* RAS# Active Time */ |
||
886 | -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
||
887 | -#define SDRAM_TPC 20 /* RAS# Precharge Time */ |
||
888 | -#define SDRAM_TRWL 7 /* Write Latency Time */ |
||
889 | -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ |
||
890 | - |
||
891 | #endif |
||
892 | -- |
||
893 | 1.7.9.5 |
||
894 |