OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001 |
2 | From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
||
3 | Date: Tue, 6 Jan 2015 21:26:44 +0100 |
||
4 | Subject: sun6i: Fix and document PLL LDO voltage selection |
||
5 | |||
6 | The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had |
||
7 | their meaning reversed. This is fixed by this change-set. With this |
||
8 | changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident |
||
9 | as setting the voltage to 1.37v (which it had done all along, even |
||
10 | though stating a different target voltage). |
||
11 | |||
12 | After changing the PLL LDO setting, it will take a little while for |
||
13 | the voltage output to settle. A sdelay()-based loop waits the same |
||
14 | order of magnitude as Boot1. |
||
15 | |||
16 | Furthermore, a bit of documentation is added to clarify that the |
||
17 | required setting for the PLL LDO is 1.37v as per the A31 manual. |
||
18 | |||
19 | --- a/arch/arm/mach-sunxi/clock_sun6i.c |
||
20 | +++ b/arch/arm/mach-sunxi/clock_sun6i.c |
||
21 | @@ -25,13 +25,26 @@ void clock_init_safe(void) |
||
22 | struct sunxi_prcm_reg * const prcm = |
||
23 | (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; |
||
24 | |||
25 | - /* Set PLL ldo voltage without this PLL6 does not work properly */ |
||
26 | + /* Set PLL ldo voltage without this PLL6 does not work properly. |
||
27 | + * |
||
28 | + * As the A31 manual states, that "before enable PLL, PLLVDD |
||
29 | + * LDO should be set to 1.37v", we need to configure this to 2.5v |
||
30 | + * in the "PLL Input Power Select" (0 << 15) and (7 << 16). |
||
31 | + */ |
||
32 | clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, |
||
33 | PRCM_PLL_CTRL_LDO_KEY); |
||
34 | clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, |
||
35 | PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | |
||
36 | - PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); |
||
37 | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370)); |
||
38 | clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); |
||
39 | + |
||
40 | + /* Give the PLL LDO voltage setting some time to take hold. |
||
41 | + * Notes: |
||
42 | + * 1) We need to use sdelay() as the timers aren't set up yet. |
||
43 | + * 2) The 100k iterations come from Boot1, which spin's for 100k |
||
44 | + * iterations through a loop. |
||
45 | + */ |
||
46 | + sdelay(100000); |
||
47 | #endif |
||
48 | |||
49 | #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) |
||
50 | --- a/arch/arm/include/asm/arch-sunxi/prcm.h |
||
51 | +++ b/arch/arm/include/asm/arch-sunxi/prcm.h |
||
52 | @@ -110,13 +110,13 @@ |
||
53 | #define PRCM_PLL_CTRL_LDO_OUT_MASK \ |
||
54 | __PRCM_PLL_CTRL_LDO_OUT(0x7) |
||
55 | /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ |
||
56 | -#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ |
||
57 | - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) |
||
58 | #define PRCM_PLL_CTRL_LDO_OUT_H(n) \ |
||
59 | + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) |
||
60 | +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ |
||
61 | __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) |
||
62 | -#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ |
||
63 | - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) |
||
64 | #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ |
||
65 | + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) |
||
66 | +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ |
||
67 | __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) |
||
68 | #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) |
||
69 | #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) |