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1 office 1 #include <common.h>
2 #include <spl.h>
3 #include <phy.h>
4 #include <netdev.h>
5 #include <ide.h>
6 #include <nand.h>
7 #include <asm/arch/spl.h>
8 #include <asm/arch/pinmux.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sysctl.h>
11  
12 DECLARE_GLOBAL_DATA_PTR;
13  
14 #ifdef CONFIG_SPL_BUILD
15  
16 #ifdef DEBUG
17 #define DILIGENCE (1048576/4)
18 static int test_memory(u32 memory)
19 {
20 volatile u32 *read;
21 volatile u32 *write;
22 const u32 INIT_PATTERN = 0xAA55AA55;
23 const u32 INC_PATTERN = 0x01030507;
24 u32 pattern;
25 int check;
26 int i;
27  
28 check = 0;
29 read = write = (volatile u32 *) memory;
30 pattern = INIT_PATTERN;
31 for (i = 0; i < DILIGENCE; i++) {
32 *write++ = pattern;
33 pattern += INC_PATTERN;
34 }
35 puts("testing\n");
36 pattern = INIT_PATTERN;
37 for (i = 0; i < DILIGENCE; i++) {
38 check += (pattern == *read++) ? 1 : 0;
39 pattern += INC_PATTERN;
40 }
41 return (check == DILIGENCE) ? 0 : -1;
42 }
43 #endif
44  
45 void uart_init(void)
46 {
47 /* Reset UART1 */
48 reset_block(SYS_CTRL_RST_UART1, 1);
49 udelay(100);
50 reset_block(SYS_CTRL_RST_UART1, 0);
51 udelay(100);
52  
53 /* Setup pin mux'ing for UART1 */
54 pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
55 pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
56 }
57  
58 extern void init_ddr(int mhz);
59  
60 void board_inithw(void)
61 {
62 int plla_freq;
63 #ifdef DEBUG
64 int i;
65 #endif /* DEBUG */
66  
67 timer_init();
68 uart_init();
69 preloader_console_init();
70  
71 plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
72 init_ddr(plla_freq);
73  
74 #ifdef DEBUG
75 if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
76 puts("memory test failed\n");
77 } else {
78 puts("memory test done\n");
79 }
80 #endif /* DEBUG */
81 #ifdef CONFIG_SPL_BSS_DRAM_START
82 extern char __bss_dram_start[];
83 extern char __bss_dram_end[];
84 memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
85 #endif
86 }
87  
88 void board_init_f(ulong dummy)
89 {
90 /* Set the stack pointer. */
91 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
92  
93 /* Clear the BSS. */
94 memset(__bss_start, 0, __bss_end - __bss_start);
95  
96 /* Set global data pointer. */
97 gd = &gdata;
98  
99 board_inithw();
100  
101 board_init_r(NULL, 0);
102 }
103  
104 u32 spl_boot_device(void)
105 {
106 return CONFIG_SPL_BOOT_DEVICE;
107 }
108  
109 #ifdef CONFIG_SPL_BLOCK_SUPPORT
110 void spl_block_device_init(void)
111 {
112 ide_init();
113 }
114 #endif
115  
116 #ifdef CONFIG_SPL_OS_BOOT
117 int spl_start_uboot(void)
118 {
119 /* break into full u-boot on 'c' */
120 return (serial_tstc() && serial_getc() == 'c');
121 }
122 #endif
123  
124 void spl_display_print(void)
125 {
126 /* print a hint, so that we will not use the wrong SPL by mistake */
127 puts(" Boot device: " BOOT_DEVICE_TYPE "\n" );
128 }
129  
130 void lowlevel_init(void)
131 {
132 }
133  
134 #ifdef USE_DL_PREFIX
135 /* quick and dirty memory allocation */
136 static ulong next_mem = CONFIG_SPL_MALLOC_START;
137  
138 void *memalign(size_t alignment, size_t bytes)
139 {
140 ulong mem = ALIGN(next_mem, alignment);
141  
142 next_mem = mem + bytes;
143  
144 if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
145 printf("spl: out of memory\n");
146 hang();
147 }
148  
149 return (void *)mem;
150 }
151  
152 void free(void* mem)
153 {
154 }
155 #endif
156  
157 #endif /* CONFIG_SPL_BUILD */
158  
159 int board_early_init_f(void)
160 {
161 return 0;
162 }
163  
164 #define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
165 #define STATIC_READ_CYCLE_SHIFT 0
166 #define STATIC_DELAYED_OE (1 << 7)
167 #define STATIC_WRITE_CYCLE_SHIFT 8
168 #define STATIC_WRITE_PULSE_SHIFT 16
169 #define STATIC_WRITE_BURST_EN (1 << 23)
170 #define STATIC_TURN_AROUND_SHIFT 24
171 #define STATIC_BUFFER_PRESENT (1 << 28)
172 #define STATIC_READ_BURST_EN (1 << 29)
173 #define STATIC_BUS_WIDTH8 (0 << 30)
174 #define STATIC_BUS_WIDTH16 (1 << 30)
175 #define STATIC_BUS_WIDTH32 (2 << 30)
176  
177 void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
178 {
179 struct nand_chip *this = mtd->priv;
180 unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
181  
182 if (ctrl & NAND_CTRL_CHANGE) {
183 nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
184 if (ctrl & NAND_CLE)
185 nandaddr |= BIT(NAND_CLE_ADDR_PIN);
186 else if (ctrl & NAND_ALE)
187 nandaddr |= BIT(NAND_ALE_ADDR_PIN);
188 this->IO_ADDR_W = (void __iomem *) nandaddr;
189 }
190  
191 if (cmd != NAND_CMD_NONE)
192 writeb(cmd, (void __iomem *) nandaddr);
193 }
194  
195 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
196  
197 int nand_dev_ready(struct mtd_info *mtd)
198 {
199 struct nand_chip *chip = mtd->priv;
200  
201 udelay(chip->chip_delay);
202  
203 return 1;
204 }
205  
206 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
207 {
208 int i;
209 struct nand_chip *chip = mtd->priv;
210  
211 for (i = 0; i < len; i++)
212 buf[i] = readb(chip->IO_ADDR_R);
213 }
214  
215 void nand_dev_reset(struct nand_chip *chip)
216 {
217 writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
218 udelay(chip->chip_delay);
219 writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
220 while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
221 ;
222 }
223 }
224  
225 #else
226  
227 #define nand_dev_reset(chip) /* framework will reset the chip anyway */
228 #define nand_read_buf NULL /* framework will provide a default one */
229 #define nand_dev_ready NULL /* dev_ready is optional */
230  
231 #endif
232  
233 int board_nand_init(struct nand_chip *chip)
234 {
235 /* Block reset Static core */
236 reset_block(SYS_CTRL_RST_STATIC, 1);
237 reset_block(SYS_CTRL_RST_STATIC, 0);
238  
239 /* Enable clock to Static core */
240 enable_clock(SYS_CTRL_CLK_STATIC);
241  
242 /* enable flash support on static bus.
243 * Enable static bus onto GPIOs, only CS0 */
244 pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
245 pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
246 pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
247 pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
248 pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
249 pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
250 pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
251 pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
252  
253 pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
254 pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
255 pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
256 pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
257 pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
258  
259 /* Setup the static bus CS0 to access FLASH */
260  
261 writel((0x3f << STATIC_READ_CYCLE_SHIFT)
262 | (0x3f << STATIC_WRITE_CYCLE_SHIFT)
263 | (0x1f << STATIC_WRITE_PULSE_SHIFT)
264 | (0x03 << STATIC_TURN_AROUND_SHIFT) |
265 STATIC_BUS_WIDTH16,
266 STATIC_CTL_BANK0);
267  
268 chip->cmd_ctrl = nand_hwcontrol;
269 chip->ecc.mode = NAND_ECC_SOFT;
270 chip->chip_delay = 30;
271 chip->dev_ready = nand_dev_ready;
272 chip->read_buf = nand_read_buf;
273  
274 nand_dev_reset(chip);
275  
276 return 0;
277 }
278  
279 int board_init(void)
280 {
281 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
282 gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
283  
284 /* assume uart is already initialized by SPL */
285  
286 #if defined(CONFIG_START_IDE)
287 puts("IDE: ");
288 ide_init();
289 #endif
290  
291 return 0;
292 }
293  
294 /* copied from board/evb64260/sdram_init.c */
295 /*
296 * Check memory range for valid RAM. A simple memory test determines
297 * the actually available RAM size between addresses `base' and
298 * `base + maxsize'. Some (not all) hardware errors are detected:
299 * - short between address lines
300 * - short between data lines
301 */
302 static long int dram_size (long int *base, long int maxsize)
303 {
304 volatile long int *addr, *b = base;
305 long int cnt, val, save1, save2;
306  
307 #define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
308 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
309 cnt <<= 1) {
310 addr = base + cnt; /* pointer arith! */
311  
312 save1 = *addr; /* save contents of addr */
313 save2 = *b; /* save contents of base */
314  
315 *addr = cnt; /* write cnt to addr */
316 *b = 0; /* put null at base */
317  
318 /* check at base address */
319 if ((*b) != 0) {
320 *addr = save1; /* restore *addr */
321 *b = save2; /* restore *b */
322 return (0);
323 }
324 val = *addr; /* read *addr */
325  
326 *addr = save1;
327 *b = save2;
328  
329 if (val != cnt) {
330 /* fix boundary condition.. STARTVAL means zero */
331 if (cnt == STARTVAL / sizeof (long))
332 cnt = 0;
333 return (cnt * sizeof (long));
334 }
335 }
336 return maxsize;
337 }
338  
339 int dram_init(void)
340 {
341 gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
342 CONFIG_MAX_SDRAM_SIZE);
343 return 0;
344 }
345  
346 int board_eth_init(bd_t *bis)
347 {
348 u32 value;
349  
350 /* set the pin multiplexers to enable talking to Ethernent Phys */
351 pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
352 pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
353  
354 // Ensure the MAC block is properly reset
355 reset_block(SYS_CTRL_RST_MAC, 1);
356 udelay(10);
357 reset_block(SYS_CTRL_RST_MAC, 0);
358  
359 // Enable the clock to the MAC block
360 enable_clock(SYS_CTRL_CLK_MAC);
361  
362 value = readl(SYS_CTRL_GMAC_CTRL);
363 /* Use simple mux for 25/125 Mhz clock switching */
364 value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
365 /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
366 value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
367 /* set auto tx speed */
368 value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
369  
370 writel(value, SYS_CTRL_GMAC_CTRL);
371  
372 return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
373 }
374