OpenWrt – Blame information for rev 1

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1 office 1 #include <common.h>
2 #include <asm/arch/sysctl.h>
3 #include <asm/arch/cpu.h>
4 #include <asm/arch/clock.h>
5  
6 typedef struct {
7 unsigned short mhz;
8 unsigned char refdiv;
9 unsigned char outdiv;
10 unsigned int fbdiv;
11 unsigned short bwadj;
12 unsigned short sfreq;
13 unsigned int sslope;
14 } PLL_CONFIG;
15  
16 const PLL_CONFIG C_PLL_CONFIG[] = {
17 { 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz
18 { 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz
19 { 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz
20 { 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz
21 { 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz
22 { 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz
23 { 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz
24 { 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz
25 { 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz
26 { 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz
27 { 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz
28 { 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz
29 { 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz
30 { 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz
31 { 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz
32 { 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz
33 { 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz
34 { 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz
35 { 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz
36 { 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz
37 { 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
38 };
39  
40 #define PLL_BYPASS (1<<1)
41 #define SAT_ENABLE (1<<3)
42  
43 #define PLL_OUTDIV_SHIFT 4
44 #define PLL_REFDIV_SHIFT 8
45 #define PLL_BWADJ_SHIFT 16
46  
47 #define PLL_LOW_FREQ 500
48 #define PLL_FREQ_STEP 25
49 static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
50 int sfreq, int sslope)
51 {
52 setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
53 udelay(10);
54 reset_block(SYS_CTRL_RST_PLLA, 1);
55 udelay(10);
56  
57 writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
58 SAT_ENABLE | PLL_BYPASS,
59 SYS_CTRL_PLLA_CTRL0);
60  
61 writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
62 writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
63 writel(sslope, SYS_CTRL_PLLA_CTRL3);
64  
65 udelay(10); // 5us delay required (from TCI datasheet), use 10us
66  
67 reset_block(SYS_CTRL_RST_PLLA, 0);
68  
69 udelay(100); // Delay for PLL to lock
70  
71 printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
72 printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
73 printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
74 printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
75  
76 clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
77 puts("\nPLLA Set\n");
78 }
79  
80 int plla_set_config(int mhz)
81 {
82 int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
83 const PLL_CONFIG *cfg;
84  
85 if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
86 debug("Freq %d MHz out of range, default to lowest\n", mhz);
87 index = 0;
88 }
89 cfg = &C_PLL_CONFIG[index];
90  
91 printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
92 plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
93 cfg->sfreq, cfg->sslope);
94  
95 return cfg->mhz;
96 }
97