OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001 |
2 | From: Matti Laakso <malaakso@elisanet.fi> |
||
3 | Date: Sat, 2 Mar 2013 23:34:00 +0100 |
||
4 | Subject: MIPS: add board support for Arcadyan ARV7510 |
||
5 | |||
6 | Signed-off-by: Matti Laakso <malaakso@elisanet.fi> |
||
7 | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
||
8 | |||
9 | --- /dev/null |
||
10 | +++ b/board/arcadyan/arv7510pw/Makefile |
||
11 | @@ -0,0 +1,27 @@ |
||
12 | +# |
||
13 | +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de |
||
14 | +# |
||
15 | +# SPDX-License-Identifier: GPL-2.0+ |
||
16 | +# |
||
17 | + |
||
18 | +include $(TOPDIR)/config.mk |
||
19 | + |
||
20 | +LIB = $(obj)lib$(BOARD).o |
||
21 | + |
||
22 | +COBJS = $(BOARD).o |
||
23 | + |
||
24 | +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) |
||
25 | +OBJS := $(addprefix $(obj),$(COBJS)) |
||
26 | +SOBJS := $(addprefix $(obj),$(SOBJS)) |
||
27 | + |
||
28 | +$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||
29 | + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) |
||
30 | + |
||
31 | +######################################################################### |
||
32 | + |
||
33 | +# defines $(obj).depend target |
||
34 | +include $(SRCTREE)/rules.mk |
||
35 | + |
||
36 | +sinclude $(obj).depend |
||
37 | + |
||
38 | +######################################################################### |
||
39 | --- /dev/null |
||
40 | +++ b/board/arcadyan/arv7510pw/arv7510pw.c |
||
41 | @@ -0,0 +1,72 @@ |
||
42 | +/* |
||
43 | + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> |
||
44 | + * |
||
45 | + * SPDX-License-Identifier: GPL-2.0+ |
||
46 | + */ |
||
47 | + |
||
48 | +#include <common.h> |
||
49 | +#include <switch.h> |
||
50 | +#include <asm/gpio.h> |
||
51 | +#include <asm/lantiq/eth.h> |
||
52 | +#include <asm/lantiq/reset.h> |
||
53 | +#include <asm/lantiq/chipid.h> |
||
54 | +#include <asm/lantiq/cpu.h> |
||
55 | + |
||
56 | +static void gpio_init(void) |
||
57 | +{ |
||
58 | + /* Initialize SSIO GPIOs */ |
||
59 | + gpio_set_altfunc(4, 1, 0, 1); |
||
60 | + gpio_set_altfunc(5, 1, 0, 1); |
||
61 | + gpio_set_altfunc(6, 1, 0, 1); |
||
62 | + ltq_gpio_init(); |
||
63 | + |
||
64 | + /* Power led on */ |
||
65 | + gpio_direction_output(76, 1); |
||
66 | +} |
||
67 | + |
||
68 | +int board_early_init_f(void) |
||
69 | +{ |
||
70 | + gpio_init(); |
||
71 | + |
||
72 | + return 0; |
||
73 | +} |
||
74 | + |
||
75 | +int checkboard(void) |
||
76 | +{ |
||
77 | + puts("Board: " CONFIG_BOARD_NAME "\n"); |
||
78 | + ltq_chip_print_info(); |
||
79 | + |
||
80 | + return 0; |
||
81 | +} |
||
82 | + |
||
83 | +static const struct ltq_eth_port_config eth_port_config[] = { |
||
84 | + /* MAC0: ADM6996I */ |
||
85 | + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, |
||
86 | +}; |
||
87 | + |
||
88 | +static const struct ltq_eth_board_config eth_board_config = { |
||
89 | + .ports = eth_port_config, |
||
90 | + .num_ports = ARRAY_SIZE(eth_port_config), |
||
91 | +}; |
||
92 | + |
||
93 | +int board_eth_init(bd_t *bis) |
||
94 | +{ |
||
95 | + return ltq_eth_initialize(ð_board_config); |
||
96 | +} |
||
97 | + |
||
98 | +static struct switch_device adm6996i_dev = { |
||
99 | + .name = "adm6996i", |
||
100 | + .cpu_port = 5, |
||
101 | + .port_mask = 0xF, |
||
102 | +}; |
||
103 | + |
||
104 | +int board_switch_init(void) |
||
105 | +{ |
||
106 | + /* Deactivate HRST line to release reset of ADM6996I switch */ |
||
107 | + ltq_reset_once(LTQ_RESET_HARD, 200000); |
||
108 | + |
||
109 | + /* ADM6996I needs some time to come out of reset */ |
||
110 | + __udelay(50000); |
||
111 | + |
||
112 | + return switch_device_register(&adm6996i_dev); |
||
113 | +} |
||
114 | --- /dev/null |
||
115 | +++ b/board/arcadyan/arv7510pw/config.mk |
||
116 | @@ -0,0 +1,7 @@ |
||
117 | +# |
||
118 | +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com |
||
119 | +# |
||
120 | +# SPDX-License-Identifier: GPL-2.0+ |
||
121 | +# |
||
122 | + |
||
123 | +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) |
||
124 | --- /dev/null |
||
125 | +++ b/board/arcadyan/arv7510pw/ddr_settings.h |
||
126 | @@ -0,0 +1,53 @@ |
||
127 | +/* |
||
128 | + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> |
||
129 | + * |
||
130 | + * SPDX-License-Identifier: GPL-2.0+ |
||
131 | + */ |
||
132 | + |
||
133 | +#define MC_DC00_VALUE 0x1B1B |
||
134 | +#define MC_DC01_VALUE 0x0 |
||
135 | +#define MC_DC02_VALUE 0x0 |
||
136 | +#define MC_DC03_VALUE 0x0 |
||
137 | +#define MC_DC04_VALUE 0x0 |
||
138 | +#define MC_DC05_VALUE 0x200 |
||
139 | +#define MC_DC06_VALUE 0x605 |
||
140 | +#define MC_DC07_VALUE 0x303 |
||
141 | +#define MC_DC08_VALUE 0x102 |
||
142 | +#define MC_DC09_VALUE 0x70A |
||
143 | +#define MC_DC10_VALUE 0x203 |
||
144 | +#define MC_DC11_VALUE 0xC02 |
||
145 | +#define MC_DC12_VALUE 0x1C8 |
||
146 | +#define MC_DC13_VALUE 0x1 |
||
147 | +#define MC_DC14_VALUE 0x0 |
||
148 | +#define MC_DC15_VALUE 0x120 |
||
149 | +#define MC_DC16_VALUE 0xC800 |
||
150 | +#define MC_DC17_VALUE 0xD |
||
151 | +#define MC_DC18_VALUE 0x301 |
||
152 | +#define MC_DC19_VALUE 0x200 |
||
153 | +#define MC_DC20_VALUE 0xA04 |
||
154 | +#define MC_DC21_VALUE 0x1700 |
||
155 | +#define MC_DC22_VALUE 0x1717 |
||
156 | +#define MC_DC23_VALUE 0x0 |
||
157 | +#define MC_DC24_VALUE 0x52 |
||
158 | +#define MC_DC25_VALUE 0x0 |
||
159 | +#define MC_DC26_VALUE 0x0 |
||
160 | +#define MC_DC27_VALUE 0x0 |
||
161 | +#define MC_DC28_VALUE 0x510 |
||
162 | +#define MC_DC29_VALUE 0x4E20 |
||
163 | +#define MC_DC30_VALUE 0x8235 |
||
164 | +#define MC_DC31_VALUE 0x0 |
||
165 | +#define MC_DC32_VALUE 0x0 |
||
166 | +#define MC_DC33_VALUE 0x0 |
||
167 | +#define MC_DC34_VALUE 0x0 |
||
168 | +#define MC_DC35_VALUE 0x0 |
||
169 | +#define MC_DC36_VALUE 0x0 |
||
170 | +#define MC_DC37_VALUE 0x0 |
||
171 | +#define MC_DC38_VALUE 0x0 |
||
172 | +#define MC_DC39_VALUE 0x0 |
||
173 | +#define MC_DC40_VALUE 0x0 |
||
174 | +#define MC_DC41_VALUE 0x0 |
||
175 | +#define MC_DC42_VALUE 0x0 |
||
176 | +#define MC_DC43_VALUE 0x0 |
||
177 | +#define MC_DC44_VALUE 0x0 |
||
178 | +#define MC_DC45_VALUE 0x500 |
||
179 | +#define MC_DC46_VALUE 0x0 |
||
180 | --- a/boards.cfg |
||
181 | +++ b/boards.cfg |
||
182 | @@ -505,6 +505,9 @@ Active mips mips32 au1x0 |
||
183 | Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> |
||
184 | Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> |
||
185 | Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> |
||
186 | +Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> |
||
187 | +Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> |
||
188 | +Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> |
||
189 | Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> |
||
190 | Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> |
||
191 | Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> |
||
192 | --- /dev/null |
||
193 | +++ b/include/configs/arv7510pw.h |
||
194 | @@ -0,0 +1,77 @@ |
||
195 | +/* |
||
196 | + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> |
||
197 | + * |
||
198 | + * SPDX-License-Identifier: GPL-2.0+ |
||
199 | + */ |
||
200 | + |
||
201 | +#ifndef __CONFIG_H |
||
202 | +#define __CONFIG_H |
||
203 | + |
||
204 | +#define CONFIG_MACH_TYPE "ARV7510PW" |
||
205 | +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE |
||
206 | +#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW" |
||
207 | + |
||
208 | +/* Configure SoC */ |
||
209 | +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ |
||
210 | +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ |
||
211 | +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ |
||
212 | + |
||
213 | +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ |
||
214 | + |
||
215 | +/* Switch devices */ |
||
216 | +#define CONFIG_SWITCH_MULTI |
||
217 | +#define CONFIG_SWITCH_ADM6996I |
||
218 | + |
||
219 | +/* SSIO */ |
||
220 | +#define CONFIG_LTQ_SSIO_SHIFT_REGS |
||
221 | +#define CONFIG_LTQ_SSIO_EDGE_FALLING |
||
222 | +#define CONFIG_LTQ_SSIO_GPHY1_MODE 0 |
||
223 | +#define CONFIG_LTQ_SSIO_GPHY2_MODE 0 |
||
224 | +#define CONFIG_LTQ_SSIO_INIT_VALUE 0 |
||
225 | + |
||
226 | +/* Environment */ |
||
227 | +#if defined(CONFIG_SYS_BOOT_NOR) |
||
228 | +#define CONFIG_ENV_IS_IN_FLASH |
||
229 | +#define CONFIG_ENV_OVERWRITE |
||
230 | +#define CONFIG_ENV_OFFSET (256 * 1024) |
||
231 | +#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||
232 | +#else |
||
233 | +#define CONFIG_ENV_IS_NOWHERE |
||
234 | +#endif |
||
235 | + |
||
236 | +#define CONFIG_ENV_SIZE (8 * 1024) |
||
237 | +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
||
238 | + |
||
239 | +/* Brnboot loadable image */ |
||
240 | +#if defined(CONFIG_SYS_BOOT_BRN) |
||
241 | +#define CONFIG_SYS_TEXT_BASE 0x80002000 |
||
242 | +#define CONFIG_SKIP_LOWLEVEL_INIT |
||
243 | +#define CONFIG_SYS_DISABLE_CACHE |
||
244 | +#define CONFIG_ENV_OVERWRITE 1 |
||
245 | +#endif |
||
246 | + |
||
247 | +/* Console */ |
||
248 | +#define CONFIG_LTQ_ADVANCED_CONSOLE |
||
249 | +#define CONFIG_BAUDRATE 115200 |
||
250 | +#define CONFIG_CONSOLE_ASC 1 |
||
251 | +#define CONFIG_CONSOLE_DEV "ttyLTQ1" |
||
252 | + |
||
253 | +/* Pull in default board configs for Lantiq XWAY Danube */ |
||
254 | +#include <asm/lantiq/config.h> |
||
255 | +#include <asm/arch/config.h> |
||
256 | + |
||
257 | +/* Buffered write broken in ARV7510PW */ |
||
258 | +#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||
259 | + |
||
260 | +/* Pull in default OpenWrt configs for Lantiq SoC */ |
||
261 | +#include "openwrt-lantiq-common.h" |
||
262 | + |
||
263 | +#define CONFIG_ENV_UPDATE_UBOOT_NOR \ |
||
264 | + "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" |
||
265 | + |
||
266 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
||
267 | + CONFIG_ENV_LANTIQ_DEFAULTS \ |
||
268 | + CONFIG_ENV_UPDATE_UBOOT_NOR \ |
||
269 | + "kernel_addr=0xB0060000\0" |
||
270 | + |
||
271 | +#endif /* __CONFIG_H */ |