OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001 |
2 | From: Luka Perkov <luka@openwrt.org> |
||
3 | Date: Tue, 6 Aug 2013 22:51:00 +0200 |
||
4 | Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx |
||
5 | |||
6 | Signed-off-by: Luka Perkov <luka@openwrt.org> |
||
7 | |||
8 | --- /dev/null |
||
9 | +++ b/board/zyxel/p2812hnufx/Makefile |
||
10 | @@ -0,0 +1,27 @@ |
||
11 | +# |
||
12 | +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de |
||
13 | +# |
||
14 | +# SPDX-License-Identifier: GPL-2.0+ |
||
15 | +# |
||
16 | + |
||
17 | +include $(TOPDIR)/config.mk |
||
18 | + |
||
19 | +LIB = $(obj)lib$(BOARD).o |
||
20 | + |
||
21 | +COBJS = $(BOARD).o |
||
22 | + |
||
23 | +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) |
||
24 | +OBJS := $(addprefix $(obj),$(COBJS)) |
||
25 | +SOBJS := $(addprefix $(obj),$(SOBJS)) |
||
26 | + |
||
27 | +$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||
28 | + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) |
||
29 | + |
||
30 | +######################################################################### |
||
31 | + |
||
32 | +# defines $(obj).depend target |
||
33 | +include $(SRCTREE)/rules.mk |
||
34 | + |
||
35 | +sinclude $(obj).depend |
||
36 | + |
||
37 | +######################################################################### |
||
38 | --- /dev/null |
||
39 | +++ b/board/zyxel/p2812hnufx/config.mk |
||
40 | @@ -0,0 +1,7 @@ |
||
41 | +# |
||
42 | +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com |
||
43 | +# |
||
44 | +# SPDX-License-Identifier: GPL-2.0+ |
||
45 | +# |
||
46 | + |
||
47 | +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) |
||
48 | --- /dev/null |
||
49 | +++ b/board/zyxel/p2812hnufx/ddr_settings.h |
||
50 | @@ -0,0 +1,70 @@ |
||
51 | +/* |
||
52 | + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> |
||
53 | + * |
||
54 | + * The values have been extracted from original ZyXEL U-Boot. |
||
55 | + * |
||
56 | + * SPDX-License-Identifier: GPL-2.0+ |
||
57 | + */ |
||
58 | + |
||
59 | +#define MC_CCR00_VALUE 0x101 |
||
60 | +#define MC_CCR01_VALUE 0x1000100 |
||
61 | +#define MC_CCR02_VALUE 0x1010000 |
||
62 | +#define MC_CCR03_VALUE 0x101 |
||
63 | +#define MC_CCR04_VALUE 0x1000000 |
||
64 | +#define MC_CCR05_VALUE 0x1000101 |
||
65 | +#define MC_CCR06_VALUE 0x1000100 |
||
66 | +#define MC_CCR07_VALUE 0x1010000 |
||
67 | +#define MC_CCR08_VALUE 0x1000101 |
||
68 | +#define MC_CCR09_VALUE 0x0 |
||
69 | +#define MC_CCR10_VALUE 0x2000100 |
||
70 | +#define MC_CCR11_VALUE 0x2000300 |
||
71 | +#define MC_CCR12_VALUE 0x30000 |
||
72 | +#define MC_CCR13_VALUE 0x202 |
||
73 | +#define MC_CCR14_VALUE 0x7080A0F |
||
74 | +#define MC_CCR15_VALUE 0x2040F |
||
75 | +#define MC_CCR16_VALUE 0x40000 |
||
76 | +#define MC_CCR17_VALUE 0x70102 |
||
77 | +#define MC_CCR18_VALUE 0x4020002 |
||
78 | +#define MC_CCR19_VALUE 0x30302 |
||
79 | +#define MC_CCR20_VALUE 0x8000700 |
||
80 | +#define MC_CCR21_VALUE 0x40F020A |
||
81 | +#define MC_CCR22_VALUE 0x0 |
||
82 | +#define MC_CCR23_VALUE 0xC020000 |
||
83 | +#define MC_CCR24_VALUE 0x4401B04 |
||
84 | +#define MC_CCR25_VALUE 0x0 |
||
85 | +#define MC_CCR26_VALUE 0x0 |
||
86 | +#define MC_CCR27_VALUE 0x6420000 |
||
87 | +#define MC_CCR28_VALUE 0x0 |
||
88 | +#define MC_CCR29_VALUE 0x0 |
||
89 | +#define MC_CCR30_VALUE 0x798 |
||
90 | +#define MC_CCR31_VALUE 0x0 |
||
91 | +#define MC_CCR32_VALUE 0x0 |
||
92 | +#define MC_CCR33_VALUE 0x650000 |
||
93 | +#define MC_CCR34_VALUE 0x200C8 |
||
94 | +#define MC_CCR35_VALUE 0x1D445D |
||
95 | +#define MC_CCR36_VALUE 0xC8 |
||
96 | +#define MC_CCR37_VALUE 0xC351 |
||
97 | +#define MC_CCR38_VALUE 0x0 |
||
98 | +#define MC_CCR39_VALUE 0x141F04 |
||
99 | +#define MC_CCR40_VALUE 0x142704 |
||
100 | +#define MC_CCR41_VALUE 0x141B42 |
||
101 | +#define MC_CCR42_VALUE 0x141B42 |
||
102 | +#define MC_CCR43_VALUE 0x566504 |
||
103 | +#define MC_CCR44_VALUE 0x566504 |
||
104 | +#define MC_CCR45_VALUE 0x565F17 |
||
105 | +#define MC_CCR46_VALUE 0x565F17 |
||
106 | +#define MC_CCR47_VALUE 0x0 |
||
107 | +#define MC_CCR48_VALUE 0x0 |
||
108 | +#define MC_CCR49_VALUE 0x0 |
||
109 | +#define MC_CCR50_VALUE 0x0 |
||
110 | +#define MC_CCR51_VALUE 0x0 |
||
111 | +#define MC_CCR52_VALUE 0x133 |
||
112 | +#define MC_CCR53_VALUE 0xF3014B27 |
||
113 | +#define MC_CCR54_VALUE 0xF3014B27 |
||
114 | +#define MC_CCR55_VALUE 0xF3014B27 |
||
115 | +#define MC_CCR56_VALUE 0xF3014B27 |
||
116 | +#define MC_CCR57_VALUE 0x7800301 |
||
117 | +#define MC_CCR58_VALUE 0x7800301 |
||
118 | +#define MC_CCR59_VALUE 0x7800301 |
||
119 | +#define MC_CCR60_VALUE 0x7800301 |
||
120 | +#define MC_CCR61_VALUE 0x4 |
||
121 | --- /dev/null |
||
122 | +++ b/board/zyxel/p2812hnufx/p2812hnufx.c |
||
123 | @@ -0,0 +1,97 @@ |
||
124 | +/* |
||
125 | + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> |
||
126 | + * |
||
127 | + * SPDX-License-Identifier: GPL-2.0+ |
||
128 | + */ |
||
129 | + |
||
130 | +#include <common.h> |
||
131 | +#include <asm/gpio.h> |
||
132 | +#include <asm/lantiq/eth.h> |
||
133 | +#include <asm/lantiq/chipid.h> |
||
134 | +#include <asm/lantiq/cpu.h> |
||
135 | +#include <asm/arch/gphy.h> |
||
136 | + |
||
137 | +#if defined(CONFIG_SPL_BUILD) |
||
138 | +#define do_gpio_init 1 |
||
139 | +#define do_pll_init 1 |
||
140 | +#define do_dcdc_init 0 |
||
141 | +#elif defined(CONFIG_SYS_BOOT_RAM) |
||
142 | +#define do_gpio_init 1 |
||
143 | +#define do_pll_init 0 |
||
144 | +#define do_dcdc_init 1 |
||
145 | +#else |
||
146 | +#define do_gpio_init 0 |
||
147 | +#define do_pll_init 0 |
||
148 | +#define do_dcdc_init 1 |
||
149 | +#endif |
||
150 | + |
||
151 | +static void gpio_init(void) |
||
152 | +{ |
||
153 | + /* EBU.FL_CS1 as output for NAND CE */ |
||
154 | + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); |
||
155 | + /* EBU.FL_A23 as output for NAND CLE */ |
||
156 | + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); |
||
157 | + /* EBU.FL_A24 as output for NAND ALE */ |
||
158 | + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); |
||
159 | + /* GPIO 3.0 as input for NAND Ready Busy */ |
||
160 | + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); |
||
161 | + /* GPIO 3.1 as output for NAND Read */ |
||
162 | + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); |
||
163 | +} |
||
164 | + |
||
165 | +int board_early_init_f(void) |
||
166 | +{ |
||
167 | + if (do_gpio_init) |
||
168 | + gpio_init(); |
||
169 | + |
||
170 | + if (do_pll_init) |
||
171 | + ltq_pll_init(); |
||
172 | + |
||
173 | + if (do_dcdc_init) |
||
174 | + ltq_dcdc_init(0x7F); |
||
175 | + |
||
176 | + return 0; |
||
177 | +} |
||
178 | + |
||
179 | +int checkboard(void) |
||
180 | +{ |
||
181 | + puts("Board: " CONFIG_BOARD_NAME "\n"); |
||
182 | + ltq_chip_print_info(); |
||
183 | + |
||
184 | + return 0; |
||
185 | +} |
||
186 | + |
||
187 | +static const struct ltq_eth_port_config eth_port_config[] = { |
||
188 | + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ |
||
189 | + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, |
||
190 | + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ |
||
191 | + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, |
||
192 | + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ |
||
193 | + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, |
||
194 | + /* GMAC3: unused */ |
||
195 | + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, |
||
196 | + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ |
||
197 | + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, |
||
198 | + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ |
||
199 | + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, |
||
200 | +}; |
||
201 | + |
||
202 | +static const struct ltq_eth_board_config eth_board_config = { |
||
203 | + .ports = eth_port_config, |
||
204 | + .num_ports = ARRAY_SIZE(eth_port_config), |
||
205 | +}; |
||
206 | + |
||
207 | +int board_eth_init(bd_t * bis) |
||
208 | +{ |
||
209 | + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; |
||
210 | + const ulong fw_addr = 0x80FF0000; |
||
211 | + |
||
212 | + ltq_gphy_phy11g_a1x_load(fw_addr); |
||
213 | + |
||
214 | + ltq_cgu_gphy_clk_src(clk); |
||
215 | + |
||
216 | + ltq_rcu_gphy_boot(0, fw_addr); |
||
217 | + ltq_rcu_gphy_boot(1, fw_addr); |
||
218 | + |
||
219 | + return ltq_eth_initialize(ð_board_config); |
||
220 | +} |
||
221 | --- a/boards.cfg |
||
222 | +++ b/boards.cfg |
||
223 | @@ -527,6 +527,8 @@ Active mips mips32 vrx20 |
||
224 | Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
||
225 | Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
||
226 | Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
||
227 | +Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org> |
||
228 | +Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> |
||
229 | Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - |
||
230 | Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - |
||
231 | Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> |
||
232 | --- /dev/null |
||
233 | +++ b/include/configs/p2812hnufx.h |
||
234 | @@ -0,0 +1,69 @@ |
||
235 | +/* |
||
236 | + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> |
||
237 | + * |
||
238 | + * SPDX-License-Identifier: GPL-2.0+ |
||
239 | + */ |
||
240 | + |
||
241 | +#ifndef __CONFIG_H |
||
242 | +#define __CONFIG_H |
||
243 | + |
||
244 | +#define CONFIG_MACH_TYPE "P-2812HNU-Fx" |
||
245 | +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE |
||
246 | +#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx" |
||
247 | + |
||
248 | +/* Configure SoC */ |
||
249 | +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ |
||
250 | + |
||
251 | +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ |
||
252 | + |
||
253 | +#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */ |
||
254 | + |
||
255 | +#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ |
||
256 | +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ |
||
257 | +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ |
||
258 | + |
||
259 | +#define CONFIG_SYS_NAND_PAGE_COUNT 64 |
||
260 | +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
||
261 | +#define CONFIG_SYS_NAND_OOBSIZE 64 |
||
262 | +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||
263 | +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
||
264 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 |
||
265 | + |
||
266 | +#define CONFIG_SYS_DRAM_PROBE |
||
267 | + |
||
268 | +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ |
||
269 | + |
||
270 | +/* Environment */ |
||
271 | +#if defined(CONFIG_SYS_BOOT_NANDSPL) |
||
272 | +#define CONFIG_ENV_IS_IN_NAND |
||
273 | +#define CONFIG_ENV_OVERWRITE |
||
274 | +#define CONFIG_ENV_OFFSET (256 * 1024) |
||
275 | +#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||
276 | +#else |
||
277 | +#define CONFIG_ENV_IS_NOWHERE |
||
278 | +#endif |
||
279 | + |
||
280 | +#define CONFIG_ENV_SIZE (8 * 1024) |
||
281 | +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
||
282 | + |
||
283 | +/* Console */ |
||
284 | +#define CONFIG_LTQ_ADVANCED_CONSOLE |
||
285 | +#define CONFIG_BAUDRATE 115200 |
||
286 | +#define CONFIG_CONSOLE_ASC 1 |
||
287 | +#define CONFIG_CONSOLE_DEV "ttyLTQ1" |
||
288 | + |
||
289 | +/* Pull in default board configs for Lantiq XWAY VRX200 */ |
||
290 | +#include <asm/lantiq/config.h> |
||
291 | +#include <asm/arch/config.h> |
||
292 | + |
||
293 | +/* Pull in default OpenWrt configs for Lantiq SoC */ |
||
294 | +#include "openwrt-lantiq-common.h" |
||
295 | + |
||
296 | +#define CONFIG_ENV_UPDATE_UBOOT_NAND \ |
||
297 | + "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" |
||
298 | + |
||
299 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
||
300 | + CONFIG_ENV_LANTIQ_DEFAULTS \ |
||
301 | + CONFIG_ENV_UPDATE_UBOOT_NAND |
||
302 | + |
||
303 | +#endif /* __CONFIG_H */ |