OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-kirkwood/Kconfig |
2 | +++ b/arch/arm/mach-kirkwood/Kconfig |
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3 | @@ -68,6 +68,9 @@ config TARGET_SBx81LIFKW |
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4 | config TARGET_SBx81LIFXCAT |
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5 | bool "Allied Telesis SBx81GP24/SBx81GT24" |
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6 | |||
7 | +config TARGET_NSA325 |
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8 | + bool "Zyxel NSA325 board" |
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9 | + |
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10 | endchoice |
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11 | |||
12 | config SYS_SOC |
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13 | @@ -91,6 +94,7 @@ source "board/Seagate/goflexhome/Kconfig |
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14 | source "board/Seagate/nas220/Kconfig" |
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15 | source "board/zyxel/nsa310/Kconfig" |
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16 | source "board/zyxel/nsa310s/Kconfig" |
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17 | +source "board/zyxel/nsa325/Kconfig" |
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18 | source "board/alliedtelesis/SBx81LIFKW/Kconfig" |
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19 | source "board/alliedtelesis/SBx81LIFXCAT/Kconfig" |
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20 | |||
21 | --- /dev/null |
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22 | +++ b/board/zyxel/nsa325/Kconfig |
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23 | @@ -0,0 +1,12 @@ |
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24 | +if TARGET_NSA325 |
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25 | + |
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26 | +config SYS_BOARD |
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27 | + default "nsa325" |
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28 | + |
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29 | +config SYS_VENDOR |
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30 | + default "zyxel" |
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31 | + |
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32 | +config SYS_CONFIG_NAME |
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33 | + default "nsa325" |
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34 | + |
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35 | +endif |
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36 | --- /dev/null |
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37 | +++ b/board/zyxel/nsa325/MAINTAINERS |
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38 | @@ -0,0 +1,6 @@ |
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39 | +NSA325 BOARD |
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40 | +M: Alberto Bursi <alberto.bursi@outlook.it> |
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41 | +S: Maintained |
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42 | +F: board/zyxel/nsa325/ |
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43 | +F: include/configs/nsa325.h |
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44 | +F: configs/nsa325_defconfig |
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45 | --- /dev/null |
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46 | +++ b/board/zyxel/nsa325/Makefile |
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47 | @@ -0,0 +1,13 @@ |
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48 | +# |
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49 | +# (C) Copyright 2015 bodhi <mibodhi@gmail.com> |
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50 | +# |
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51 | +# Based on |
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52 | +# (C) Copyright 2009 |
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53 | +# Marvell Semiconductor <www.marvell.com> |
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54 | +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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55 | +# |
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56 | +# SPDX-License-Identifier: GPL-2.0+ |
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57 | +# |
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58 | + |
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59 | +obj-y := nsa325.o |
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60 | + |
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61 | --- /dev/null |
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62 | +++ b/board/zyxel/nsa325/kwbimage.cfg |
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63 | @@ -0,0 +1,78 @@ |
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64 | +# Copyright (C) 2015 bodhi <mibodhi@gmail.com> |
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65 | +# |
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66 | +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2 |
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67 | +# |
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68 | +# See file CREDITS for list of people who contributed to this |
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69 | +# project. |
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70 | +# |
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71 | +# This program is free software; you can redistribute it and/or |
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72 | +# modify it under the terms of the GNU General Public License as |
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73 | +# published by the Free Software Foundation; either version 2 of |
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74 | +# the License, or (at your option) any later version. |
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75 | +# |
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76 | +# This program is distributed in the hope that it will be useful, |
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77 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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78 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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79 | +# GNU General Public License for more details. |
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80 | +# |
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81 | +# You should have received a copy of the GNU General Public License |
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82 | +# along with this program; if not, write to the Free Software |
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83 | +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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84 | +# MA 02110-1301 USA |
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85 | +# |
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86 | +# Refer docs/README.kwimage for more details about how-to configure |
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87 | +# and create kirkwood boot image |
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88 | +# |
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89 | + |
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90 | +# Boot Media configurations |
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91 | +#BOOT_FROM uart |
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92 | +BOOT_FROM nand |
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93 | +NAND_ECC_MODE default |
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94 | +NAND_PAGE_SIZE 0x0800 |
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95 | + |
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96 | +# SOC registers configuration using bootrom header extension |
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97 | +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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98 | + |
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99 | +# Configure RGMII-0 interface pad voltage to 1.8V |
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100 | +DATA 0xFFD100e0 0x1b1b1b9b |
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101 | + |
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102 | +#Dram initalization |
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103 | +DATA 0xFFD01400 0x4301503E # DDR Configuration register |
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104 | +DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low |
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105 | +DATA 0xFFD01408 0x33137777 # DDR Timing (Low) |
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106 | +DATA 0xFFD0140C 0x16000C55 # DDR Timing (High) |
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107 | +DATA 0xFFD01410 0x04000000 # DDR Address Control |
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108 | +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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109 | +DATA 0xFFD01418 0x00000000 # DDR Operation |
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110 | +DATA 0xFFD0141C 0x00000672 # DDR Mode |
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111 | +DATA 0xFFD01420 0x00000004 # DDR Extended Mode |
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112 | +DATA 0xFFD01424 0x0000F14F # DDR Controller Control High |
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113 | +DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing |
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114 | +DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing |
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115 | +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size |
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116 | +DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb |
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117 | +DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1 |
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118 | +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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119 | +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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120 | +DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low) |
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121 | +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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122 | +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control |
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123 | + |
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124 | +DATA 0xFFD015D0 0x00000630 |
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125 | +DATA 0xFFD015D4 0x00000046 |
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126 | +DATA 0xFFD015D8 0x00000008 |
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127 | +DATA 0xFFD015DC 0x00000000 |
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128 | +DATA 0xFFD015E0 0x00000023 |
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129 | +DATA 0xFFD015E4 0x00203C18 |
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130 | +DATA 0xFFD01620 0x00384800 |
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131 | +DATA 0xFFD01480 0x00000001 |
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132 | +DATA 0xFFD20134 0x66666666 |
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133 | +DATA 0xFFD20138 0x00066666 |
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134 | + |
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135 | +#Disable nsa325 hardware watchdog to allow successful kwbooting |
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136 | +DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog |
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137 | +DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it) |
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138 | + |
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139 | +# End of Header extension |
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140 | +DATA 0x0 0x0 |
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141 | + |
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142 | --- /dev/null |
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143 | +++ b/board/zyxel/nsa325/nsa325.c |
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144 | @@ -0,0 +1,265 @@ |
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145 | +/* |
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146 | + * Copyright (C) 2015 bodhi <mibodhi@gmail.com> |
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147 | + * |
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148 | + * Based on |
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149 | + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org> |
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150 | + * |
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151 | + * Based on nsa320.c originall written by |
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152 | + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info> |
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153 | + * |
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154 | + * Based on guruplug.c originally written by |
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155 | + * Siddarth Gore <gores@marvell.com> |
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156 | + * (C) Copyright 2009 |
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157 | + * Marvell Semiconductor <www.marvell.com> |
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158 | + * |
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159 | + * See file CREDITS for list of people who contributed to this |
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160 | + * project. |
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161 | + * |
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162 | + * This program is free software; you can redistribute it and/or |
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163 | + * modify it under the terms of the GNU General Public License as |
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164 | + * published by the Free Software Foundation; either version 2 of |
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165 | + * the License, or (at your option) any later version. |
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166 | + * |
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167 | + * This program is distributed in the hope that it will be useful, |
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168 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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169 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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170 | + * GNU General Public License for more details. |
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171 | + * |
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172 | + * You should have received a copy of the GNU General Public License |
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173 | + * along with this program; if not, write to the Free Software |
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174 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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175 | + * MA 02110-1301 USA |
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176 | + */ |
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177 | + |
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178 | +#include <common.h> |
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179 | +#include <miiphy.h> |
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180 | +#include <asm/arch/soc.h> |
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181 | +#include <asm/arch/mpp.h> |
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182 | +#include <asm/arch/cpu.h> |
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183 | +#include <asm/gpio.h> |
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184 | +#include <asm/io.h> |
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185 | +#include "nsa325.h" |
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186 | +#include <asm/arch/gpio.h> |
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187 | + |
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188 | +DECLARE_GLOBAL_DATA_PTR; |
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189 | + |
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190 | +int board_early_init_f(void) |
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191 | +{ |
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192 | + /* |
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193 | + * default gpio configuration |
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194 | + * There are maximum 64 gpios controlled through 2 sets of registers |
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195 | + * the below configuration configures mainly initial LED status |
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196 | + */ |
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197 | + mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH, |
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198 | + NSA325_OE_LOW, NSA325_OE_HIGH); |
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199 | + |
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200 | + /* Multi-Purpose Pins Functionality configuration */ |
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201 | + /* (all LEDs & power off active high) */ |
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202 | + u32 kwmpp_config[] = { |
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203 | + MPP0_NF_IO2, |
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204 | + MPP1_NF_IO3, |
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205 | + MPP2_NF_IO4, |
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206 | + MPP3_NF_IO5, |
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207 | + MPP4_NF_IO6, |
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208 | + MPP5_NF_IO7, |
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209 | + MPP6_SYSRST_OUTn, |
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210 | + MPP7_GPO, |
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211 | + MPP8_TW_SDA, /* PCF8563 RTC chip */ |
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212 | + MPP9_TW_SCK, /* connected to TWSI */ |
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213 | + MPP10_UART0_TXD, |
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214 | + MPP11_UART0_RXD, |
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215 | + MPP12_GPO, /* HDD2 LED (green) */ |
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216 | + MPP13_GPIO, /* HDD2 LED (red) */ |
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217 | + MPP14_GPIO, /* MCU DATA pin (in) */ |
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218 | + MPP15_GPIO, /* USB LED (green) */ |
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219 | + MPP16_GPIO, /* MCU CLK pin (out) */ |
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220 | + MPP17_GPIO, /* MCU ACT pin (out) */ |
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221 | + MPP18_NF_IO0, |
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222 | + MPP19_NF_IO1, |
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223 | + MPP20_GPIO, |
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224 | + MPP21_GPIO, /* USB power */ |
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225 | + MPP22_GPIO, |
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226 | + MPP23_GPIO, |
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227 | + MPP24_GPIO, |
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228 | + MPP25_GPIO, |
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229 | + MPP26_GPIO, |
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230 | + MPP27_GPIO, |
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231 | + MPP28_GPIO, /* SYS LED (green) */ |
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232 | + MPP29_GPIO, /* SYS LED (orange) */ |
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233 | + MPP30_GPIO, |
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234 | + MPP31_GPIO, |
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235 | + MPP32_GPIO, |
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236 | + MPP33_GPIO, |
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237 | + MPP34_GPIO, |
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238 | + MPP35_GPIO, |
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239 | + MPP36_GPIO, /* reset button */ |
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240 | + MPP37_GPIO, /* copy button */ |
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241 | + MPP38_GPIO, /* VID B0 */ |
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242 | + MPP39_GPIO, /* COPY LED (green) */ |
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243 | + MPP40_GPIO, /* COPY LED (red) */ |
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244 | + MPP41_GPIO, /* HDD1 LED (green) */ |
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245 | + MPP42_GPIO, /* HDD1 LED (red) */ |
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246 | + MPP43_GPIO, /* HTP pin */ |
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247 | + MPP44_GPIO, /* buzzer */ |
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248 | + MPP45_GPIO, /* VID B1 */ |
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249 | + MPP46_GPIO, /* power button */ |
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250 | + MPP47_GPIO, /* HDD2 power */ |
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251 | + MPP48_GPIO, /* power off */ |
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252 | + 0 |
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253 | + }; |
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254 | + kirkwood_mpp_conf(kwmpp_config, NULL); |
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255 | + return 0; |
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256 | +} |
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257 | + |
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258 | +int board_init(void) |
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259 | +{ |
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260 | + |
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261 | + /* address of boot parameters */ |
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262 | + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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263 | + |
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264 | + /* This disables the hardware watchdog in the mcu on this board. */ |
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265 | + kw_gpio_set_valid(14, 1); |
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266 | + kw_gpio_direction_output(14, 0); |
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267 | + kw_gpio_set_value(14, 1); |
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268 | + |
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269 | + return 0; |
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270 | +} |
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271 | + |
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272 | +#ifdef CONFIG_RESET_PHY_R |
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273 | +/* Configure and enable MV88E1318 PHY */ |
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274 | +void reset_phy(void) |
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275 | +{ |
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276 | + u16 reg; |
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277 | + u16 devadr; |
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278 | + char *name = "egiga0"; |
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279 | + |
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280 | + if (miiphy_set_current_dev(name)) |
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281 | + return; |
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282 | + |
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283 | + /* command to read PHY dev address */ |
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284 | + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
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285 | + printf("Err..%s could not read PHY dev address\n", |
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286 | + __FUNCTION__); |
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287 | + return; |
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288 | + } |
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289 | + |
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290 | + /* Set RGMII delay */ |
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291 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); |
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292 | + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); |
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293 | + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); |
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294 | + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); |
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295 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); |
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296 | + |
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297 | + /* reset the phy */ |
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298 | + miiphy_reset(name, devadr); |
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299 | + |
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300 | + /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */ |
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301 | + /* and has an MCU attached to the LED[2] via tristate interrupt */ |
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302 | + reg = 0; |
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303 | + |
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304 | + /* switch to LED register page */ |
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305 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); |
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306 | + /* read out LED polarity register */ |
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307 | + miiphy_read(name, devadr, MV88E1318_LED_POL_REG, ®); |
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308 | + /* clear 4, set 5 - LED2 low, tri-state */ |
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309 | + reg &= ~(MV88E1318_LED2_4); |
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310 | + reg |= (MV88E1318_LED2_5); |
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311 | + /* write back LED polarity register */ |
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312 | + miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg); |
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313 | + /* jump back to page 0, per the PHY chip documenation. */ |
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314 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); |
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315 | + |
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316 | + /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */ |
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317 | + miiphy_write(name, devadr, 0x4, 0x1e1); |
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318 | + miiphy_write(name, devadr, 0x9, 0x300); |
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319 | + /* Downshift */ |
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320 | + miiphy_write(name, devadr, 0x10, 0x3860); |
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321 | + miiphy_write(name, devadr, 0x0, 0x9140); |
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322 | + |
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323 | + printf("MV88E1318 PHY initialized on %s\n", name); |
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324 | + |
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325 | +} |
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326 | +#endif /* CONFIG_RESET_PHY_R */ |
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327 | + |
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328 | +#ifdef CONFIG_SHOW_BOOT_PROGRESS |
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329 | +void show_boot_progress(int val) |
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330 | +{ |
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331 | + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; |
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332 | + u32 dout0 = readl(&gpio0->dout); |
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333 | + u32 blen0 = readl(&gpio0->blink_en); |
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334 | + |
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335 | + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; |
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336 | + u32 dout1 = readl(&gpio1->dout); |
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337 | + u32 blen1 = readl(&gpio1->blink_en); |
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338 | + |
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339 | + switch (val) { |
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340 | + case BOOTSTAGE_ID_DECOMP_IMAGE: |
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341 | + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en); |
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342 | + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout); |
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343 | + break; |
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344 | + case BOOTSTAGE_ID_RUN_OS: |
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345 | + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout); |
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346 | + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); |
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347 | + break; |
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348 | + case BOOTSTAGE_ID_NET_START: |
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349 | + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); |
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350 | + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); |
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351 | + break; |
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352 | + case BOOTSTAGE_ID_NET_LOADED: |
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353 | + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); |
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354 | + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); |
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355 | + break; |
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356 | + case -BOOTSTAGE_ID_NET_NETLOOP_OK: |
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357 | + case -BOOTSTAGE_ID_NET_LOADED: |
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358 | + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); |
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359 | + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); |
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360 | + break; |
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361 | + default: |
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362 | + if (val < 0) { |
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363 | + /* error */ |
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364 | + printf("Error occured, error code = %d\n", -val); |
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365 | + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); |
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366 | + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en); |
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367 | + } |
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368 | + break; |
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369 | + } |
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370 | +} |
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371 | +#endif |
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372 | + |
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373 | +#if defined(CONFIG_KIRKWOOD_GPIO) |
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374 | +/* Return GPIO button status */ |
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375 | +/* |
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376 | +un-pressed: |
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377 | + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear ) |
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378 | + gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear ) |
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379 | + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear ) |
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380 | +pressed |
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381 | + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear ) |
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382 | + gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear ) |
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383 | + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear ) |
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384 | +*/ |
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385 | + |
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386 | +static int |
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387 | +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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388 | +{ |
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389 | + if (strcmp(argv[1], "power") == 0) { |
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390 | + kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK); |
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391 | + kw_gpio_direction_input(BTN_POWER); |
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392 | + return !kw_gpio_get_value(BTN_POWER); |
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393 | + } |
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394 | + else if (strcmp(argv[1], "reset") == 0) |
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395 | + return kw_gpio_get_value(BTN_RESET); |
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396 | + else if (strcmp(argv[1], "copy") == 0) |
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397 | + return kw_gpio_get_value(BTN_COPY); |
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398 | + else |
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399 | + return -1; |
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400 | +} |
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401 | + |
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402 | + |
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403 | +U_BOOT_CMD(button, 2, 0, do_read_button, |
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404 | + "Return GPIO button status 0=off 1=on", |
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405 | + "- button power|reset|copy: test buttons states\n" |
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406 | +); |
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407 | + |
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408 | +#endif |
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409 | + |
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410 | --- /dev/null |
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411 | +++ b/board/zyxel/nsa325/nsa325.h |
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412 | @@ -0,0 +1,77 @@ |
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413 | +/* |
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414 | + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org> |
||
415 | + * |
||
416 | + * Based on nsa320.h originall written by |
||
417 | + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info> |
||
418 | + * |
||
419 | + * Based on guruplug.h originally written by |
||
420 | + * Siddarth Gore <gores@marvell.com> |
||
421 | + * (C) Copyright 2009 |
||
422 | + * Marvell Semiconductor <www.marvell.com> |
||
423 | + * |
||
424 | + * See file CREDITS for list of people who contributed to this |
||
425 | + * project. |
||
426 | + * |
||
427 | + * This program is free software; you can redistribute it and/or |
||
428 | + * modify it under the terms of the GNU General Public License as |
||
429 | + * published by the Free Software Foundation; either version 2 of |
||
430 | + * the License, or (at your option) any later version. |
||
431 | + * |
||
432 | + * This program is distributed in the hope that it will be useful, |
||
433 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
434 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
435 | + * GNU General Public License for more details. |
||
436 | + * |
||
437 | + * You should have received a copy of the GNU General Public License |
||
438 | + * along with this program; if not, write to the Free Software |
||
439 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||
440 | + * MA 02110-1301 USA |
||
441 | + */ |
||
442 | + |
||
443 | +#ifndef __NSA325_H |
||
444 | +#define __NSA325_H |
||
445 | + |
||
446 | +/* low GPIO's */ |
||
447 | +#define HDD2_GREEN_LED (1 << 12) |
||
448 | +#define HDD2_RED_LED (1 << 13) |
||
449 | +#define USB_GREEN_LED (1 << 15) |
||
450 | +#define USB_POWER (1 << 21) |
||
451 | +#define SYS_GREEN_LED (1 << 28) |
||
452 | +#define SYS_ORANGE_LED (1 << 29) |
||
453 | + |
||
454 | +#define PIN_USB_GREEN_LED 15 |
||
455 | +#define PIN_USB_POWER 21 |
||
456 | + |
||
457 | +#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \ |
||
458 | + USB_GREEN_LED | USB_POWER | \ |
||
459 | + SYS_GREEN_LED | SYS_ORANGE_LED)) |
||
460 | +#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER) |
||
461 | + |
||
462 | +/* high GPIO's */ |
||
463 | +#define COPY_GREEN_LED (1 << 7) |
||
464 | +#define COPY_RED_LED (1 << 8) |
||
465 | +#define HDD1_GREEN_LED (1 << 9) |
||
466 | +#define HDD1_RED_LED (1 << 10) |
||
467 | +#define HDD2_POWER (1 << 15) |
||
468 | +#define WATCHDOG_SIGNAL (1 << 14) |
||
469 | + |
||
470 | +#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \ |
||
471 | + HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL )) |
||
472 | +#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER) |
||
473 | + |
||
474 | +/* PHY related */ |
||
475 | +#define MV88E1318_PGADR_REG 22 |
||
476 | +#define MV88E1318_MAC_CTRL_PG 2 |
||
477 | +#define MV88E1318_MAC_CTRL_REG 21 |
||
478 | +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) |
||
479 | +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) |
||
480 | +#define MV88E1318_LED_PG 3 |
||
481 | +#define MV88E1318_LED_POL_REG 17 |
||
482 | +#define MV88E1318_LED2_4 (1 << 4) |
||
483 | +#define MV88E1318_LED2_5 (1 << 5) |
||
484 | + |
||
485 | +#define BTN_POWER 46 |
||
486 | +#define BTN_RESET 36 |
||
487 | +#define BTN_COPY 37 |
||
488 | + |
||
489 | +#endif /* __NSA325_H */ |
||
490 | --- /dev/null |
||
491 | +++ b/configs/nsa325_defconfig |
||
492 | @@ -0,0 +1,40 @@ |
||
493 | +CONFIG_ARM=y |
||
494 | +CONFIG_KIRKWOOD=y |
||
495 | +CONFIG_SYS_TEXT_BASE=0x600000 |
||
496 | +CONFIG_TARGET_NSA325=y |
||
497 | +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server" |
||
498 | +CONFIG_NR_DRAM_BANKS=2 |
||
499 | +CONFIG_BOOTDELAY=3 |
||
500 | +CONFIG_SYS_PROMPT="NSA325> " |
||
501 | +# CONFIG_CMD_IMLS is not set |
||
502 | +# CONFIG_CMD_FLASH is not set |
||
503 | +CONFIG_MVGBE=y |
||
504 | +CONFIG_MII=y |
||
505 | +CONFIG_SYS_NS16550=y |
||
506 | +CONFIG_CMD_FDT=y |
||
507 | +CONFIG_OF_LIBFDT=y |
||
508 | +CONFIG_CMD_SETEXPR=y |
||
509 | +CONFIG_CMD_DHCP=y |
||
510 | +CONFIG_CMD_MII=y |
||
511 | +CONFIG_CMD_PING=y |
||
512 | +CONFIG_CMD_DNS=y |
||
513 | +CONFIG_CMD_SNTP=y |
||
514 | +CONFIG_CMD_USB=y |
||
515 | +CONFIG_USB=y |
||
516 | +CONFIG_CMD_DATE=y |
||
517 | +CONFIG_CMD_EXT2=y |
||
518 | +CONFIG_CMD_EXT4=y |
||
519 | +CONFIG_CMD_FAT=y |
||
520 | +CONFIG_CMD_JFFS2=y |
||
521 | +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)" |
||
522 | +CONFIG_CMD_MTDPARTS=y |
||
523 | +CONFIG_CMD_ENV=y |
||
524 | +CONFIG_CMD_NAND=y |
||
525 | +CONFIG_EFI_PARTITION=y |
||
526 | +CONFIG_ENV_IS_IN_NAND=y |
||
527 | +CONFIG_CMD_UBI=y |
||
528 | +CONFIG_USB_EHCI_HCD=y |
||
529 | +CONFIG_USB_STORAGE=y |
||
530 | +CONFIG_LZMA=y |
||
531 | +CONFIG_LZO=y |
||
532 | +CONFIG_SYS_LONGHELP=y |
||
533 | --- /dev/null |
||
534 | +++ b/include/configs/nsa325.h |
||
535 | @@ -0,0 +1,120 @@ |
||
536 | +/* |
||
537 | + * (C) Copyright 2016 bodhi <mibodhi@gmail.com> |
||
538 | + * |
||
539 | + * Based on |
||
540 | + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org> |
||
541 | + * Based on |
||
542 | + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info> |
||
543 | + * |
||
544 | + * Based on guruplug.h originally written by |
||
545 | + * Siddarth Gore <gores@marvell.com> |
||
546 | + * (C) Copyright 2009 |
||
547 | + * Marvell Semiconductor <www.marvell.com> |
||
548 | + * |
||
549 | + * See file CREDITS for list of people who contributed to this |
||
550 | + * project. |
||
551 | + * |
||
552 | + * This program is free software; you can redistribute it and/or |
||
553 | + * modify it under the terms of the GNU General Public License as |
||
554 | + * published by the Free Software Foundation; either version 2 of |
||
555 | + * the License, or (at your option) any later version. |
||
556 | + * |
||
557 | + * This program is distributed in the hope that it will be useful, |
||
558 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
559 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
560 | + * GNU General Public License for more details. |
||
561 | + * |
||
562 | + * You should have received a copy of the GNU General Public License |
||
563 | + * along with this program; if not, write to the Free Software |
||
564 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||
565 | + * MA 02110-1301 USA |
||
566 | + */ |
||
567 | + |
||
568 | +#ifndef _CONFIG_NSA325_H |
||
569 | +#define _CONFIG_NSA325_H |
||
570 | + |
||
571 | +/* |
||
572 | + * High Level Configuration Options (easy to change) |
||
573 | + */ |
||
574 | +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ |
||
575 | +#define CONFIG_KW88F6281 1 /* SOC Name */ |
||
576 | + |
||
577 | +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||
578 | + |
||
579 | +/* |
||
580 | + * Misc Configuration Options |
||
581 | + */ |
||
582 | +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ |
||
583 | + |
||
584 | +/* |
||
585 | + * Commands configuration |
||
586 | + */ |
||
587 | +#define CONFIG_PREBOOT |
||
588 | + |
||
589 | +/* |
||
590 | + * mv-common.h should be defined after CMD configs since it used them |
||
591 | + * to enable certain macros |
||
592 | + */ |
||
593 | +#include "mv-common.h" |
||
594 | + |
||
595 | +/* |
||
596 | + * Environment variables configurations |
||
597 | + */ |
||
598 | +#ifdef CONFIG_CMD_NAND |
||
599 | +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
||
600 | +#endif |
||
601 | +/* |
||
602 | + * max 4k env size is enough, but in case of nand |
||
603 | + * it has to be rounded to sector size |
||
604 | + */ |
||
605 | +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
||
606 | +#define CONFIG_ENV_ADDR 0xc0000 |
||
607 | +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ |
||
608 | + |
||
609 | +/* |
||
610 | + * Default environment variables |
||
611 | + */ |
||
612 | +#define CONFIG_BOOTCOMMAND \ |
||
613 | + "ubi part ubi; " \ |
||
614 | + "ubi read 0x800000 kernel; " \ |
||
615 | + "bootm 0x800000" |
||
616 | + |
||
617 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
||
618 | + "console=console=ttyS0,115200\0" \ |
||
619 | + "mtdids=nand0=orion_nand\0" \ |
||
620 | + "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \ |
||
621 | + "bootargs_root=\0" |
||
622 | + |
||
623 | +/* |
||
624 | + * Ethernet Driver configuration |
||
625 | + */ |
||
626 | +#ifdef CONFIG_CMD_NET |
||
627 | +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
||
628 | +#define CONFIG_PHY_BASE_ADR 0x1 |
||
629 | +#define CONFIG_NETCONSOLE |
||
630 | +#endif /* CONFIG_CMD_NET */ |
||
631 | + |
||
632 | +/* |
||
633 | + * SATA Driver configuration |
||
634 | + */ |
||
635 | +#ifdef CONFIG_MVSATA_IDE |
||
636 | +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
||
637 | +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
||
638 | +#endif /* CONFIG_MVSATA_IDE */ |
||
639 | + |
||
640 | +/* |
||
641 | + * File system |
||
642 | + */ |
||
643 | +#define CONFIG_JFFS2_NAND |
||
644 | +#define CONFIG_JFFS2_LZO |
||
645 | + |
||
646 | +/* |
||
647 | + * Date Time |
||
648 | + */ |
||
649 | +#ifdef CONFIG_CMD_DATE |
||
650 | +#define CONFIG_RTC_MV |
||
651 | +#endif /* CONFIG_CMD_DATE */ |
||
652 | + |
||
653 | +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ |
||
654 | + |
||
655 | +#endif /* _CONFIG_NSA325_H */ |