WebSVN – nexmon – Blame – Rev 1 – /patches/include/debug.h

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office

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#ifndef DEBUG_H

#define DEBUG_H

struct trace {

unsigned int exception_id;

unsigned int PC;

unsigned int CPSR;

unsigned int SPSR;

unsigned int r0;

unsigned int r1;

unsigned int r2;

unsigned int r3;

unsigned int r4;

unsigned int r5;

unsigned int r6;

unsigned int r7;

unsigned int r8;

unsigned int r9;

unsigned int r10;

unsigned int r11;

unsigned int r12;

unsigned int sp;

unsigned int lr;

unsigned int pc;

} __attribute__((packed));

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/* the number of available watch- and breakpoints */

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#define DBG_NUMBER_OF_WATCHPOINTS 4

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#define DBG_NUMBER_OF_BREAKPOINTS 4

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#define SET_DBG_VALUE(name, value) (((value) & name ## _MASK) << name ## _SHIFT)

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#define GET_DBG_VALUE(name, reg) (((reg) >> name ## _SHIFT) & name ## _MASK)

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#define GET_DBG_MASK(name) (name ## _MASK << name ## _SHIFT)

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#define GET_DBG_INV_MASK(name) ~GET_DBG_MASK(name)

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#define UPDATE_DBG_REG(reg, mask, value) (((reg) & ~(mask)) | (value))

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/* The address where the memory mapped debug registers are located */

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#define DBGBASE (0x18007000)

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/* C11.11.20 DBGDSCR - Debug Status and Control Register */

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#define DBGDSCR (*(volatile int *) (DBGBASE + 0x88))

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// MASK masks the bits before shifting left or after shifting right

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/* DBGDTRRX register full (read only) */

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#define DBGDSCR_RXfull_SHIFT 30

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#define DBGDSCR_RXfull_MASK 1

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#define DBGDSCR_RXfull_EMPTY 0

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#define DBGDSCR_RXfull_FULL 1

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/* DBGDTRTX register full (read only) */

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#define DBGDSCR_TXfull_SHIFT 29

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#define DBGDSCR_TXfull_MASK 1

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#define DBGDSCR_TXfull_EMPTY 0

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#define DBGDSCR_TXfull_FULL 1

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/* Latched RXfull (read only) */

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#define DBGDSCR_RXfull_I_SHIFT 27

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#define DBGDSCR_RXfull_I_MASK 1

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/* Latched TXfull (read only) */

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#define DBGDSCR_TXfull_I_SHIFT 26

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#define DBGDSCR_TXfull_I_MASK 1

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/* Sticky Pipeline Advance bit (read only) */

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#define DBGDSCR_PipeAdv_SHIFT 25

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#define DBGDSCR_PipeAdv_MASK 1

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/* Latched Instruction Complete (read only) */

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#define DBGDSCR_InstrCompl_I_SHIFT 24

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#define DBGDSCR_InstrCompl_I_MASK 1

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#define DBGDSCR_InstrCompl_I_NOT_COMPLETED 0

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#define DBGDSCR_InstrCompl_I_COMPLETED 1

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/* External DCC access mode */

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#define DBGDSCR_ExtDCCmode_SHIFT 20

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#define DBGDSCR_ExtDCCmode_MASK 3

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#define DBGDSCR_ExtDCCmode_NON_BLOCKING_MODE 0x0

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#define DBGDSCR_ExtDCCmode_STALL_MODE 0x1

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#define DBGDSCR_ExtDCCmode_FAST_MODE 0x2

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/* Asynchronous Aborts Discarded */

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#define DBGDSCR_ADAdiscard_SHIFT 19

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#define DBGDSCR_ADAdiscard_MASK 1

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/* Non-secure state status */

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#define DBGDSCR_NS_SHIFT 18

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#define DBGDSCR_NS_MASK 1

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/* Secure PL1 Non_invasive Debug Disabled */

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#define DBGDSCR_SPNIDdis_SHIFT 17

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#define DBGDSCR_SPNIDdis_MASK 1

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#define DBGDSCR_SPNIDdis_PERMITTED 0

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#define DBGDSCR_SPNIDdis_NOT_PERMITTED 1

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/* Secure PL1 Invasive Debug Disabled bit */

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#define DBGDSCR_SPIDdis_SHIFT 16

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#define DBGDSCR_SPIDdis_MASK 1

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#define DBGDSCR_SPIDdis_PERMITTED 0

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#define DBGDSCR_SPIDdis_NOT_PERMITTED 1

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/* Monitor debug-mode enable */

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#define DBGDSCR_MDBGen_SHIFT 15

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#define DBGDSCR_MDBGen_MASK 1

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#define DBGDSCR_MDBGen_DISABLED 0

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#define DBGDSCR_MDBGen_ENABLED 1

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/* Halting debug-mode enable */

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#define DBGDSCR_HDBGen_SHIFT 14

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#define DBGDSCR_HDBGen_MASK 1

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#define DBGDSCR_HDBGen_DISABLED 0

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#define DBGDSCR_HDBGen_ENABLED 1

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/* Execute ARM instruction enable */

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#define DBGDSCR_ITRen_SHIFT 13

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#define DBGDSCR_ITRen_MASK 1

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#define DBGDSCR_ITRen_DISABLED 0

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#define DBGDSCR_ITRen_ENABLED 1

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/* User mode access to Debug Communications Channel (DCC) disabled */

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#define DBGDSCR_UDCCdis_SHIFT 12

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#define DBGDSCR_UDCCdis_MASK 1

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#define DBGDSCR_UDCCdis_ENABLED 0

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#define DBGDSCR_UDCCdis_DISABLED 1

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/* Interrumpts Disable */

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#define DBGDSCR_INTdis_SHIFT 11

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#define DBGDSCR_INTdis_MASK 1

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#define DBGDSCR_INTdis_ENABLED 0

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#define DBGDSCR_INTdis_DISABLED 1

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/* Force Debug Acknowledge */

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#define DBGDSCR_DBGack_SHIFT 10

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#define DBGDSCR_DBGack_MASK 1

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/* Fault status */

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#define DBGDSCR_FS_SHIFT 9

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#define DBGDSCR_FS_MASK 1

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/* Sticky Undefined Instruction */

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#define DBGDSCR_UND_I_SHIFT 8

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#define DBGDSCR_UND_I_MASK 1

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/* Sticky Asynchronous Abort */

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#define DBGDSCR_ADABORT_I_SHIFT 7

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#define DBGDSCR_ADABORT_I_MASK 1

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/* Sticky Synchronous Data Abort */

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#define DBGDSCR_SDABORT_I_SHIFT 6

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#define DBGDSCR_SDABORT_I_MASK 1

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/* Method of Debug entry */

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#define DBGDSCR_MOE_SHIFT 2

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#define DBGDSCR_MOE_MASK 0xF

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/* Processor Restarted */

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#define DBGDSCR_RESTARTED_SHIFT 1

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#define DBGDSCR_RESTARTED_MASK 1

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/* Processor Halted */

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#define DBGDSCR_HALTED_SHIFT 0

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#define DBGDSCR_HALTED_MASK 1

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#define DBGDSCR_HALTED_NON_DEBUG_STATE 0

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#define DBGDSCR_HALTED_DEBUG_STATE 1

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/* C11.11.3 DBGBVR - Breakpoint Value Registers */

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#define DBGBVR0 (*(volatile int *) (DBGBASE + 0x100))

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#define DBGBVR1 (*(volatile int *) (DBGBASE + 0x104))

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#define DBGBVR2 (*(volatile int *) (DBGBASE + 0x108))

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#define DBGBVR3 (*(volatile int *) (DBGBASE + 0x10C))

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#define DBGBVR4 (*(volatile int *) (DBGBASE + 0x110))

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#define DBGBVR5 (*(volatile int *) (DBGBASE + 0x114))

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#define DBGBVR6 (*(volatile int *) (DBGBASE + 0x118))

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#define DBGBVR7 (*(volatile int *) (DBGBASE + 0x11C))

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/* The last two bits of an instruction address needs to be set to 0 */

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#define DBGBVR_ADDRMASK (0xFFFFFFFC)

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/* C11.11.2 DBGBCR - Breakpoint Control Registers */

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#define DBGBCR0 (*(volatile int *) (DBGBASE + 0x140))

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#define DBGBCR1 (*(volatile int *) (DBGBASE + 0x144))

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#define DBGBCR2 (*(volatile int *) (DBGBASE + 0x148))

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#define DBGBCR3 (*(volatile int *) (DBGBASE + 0x14C))

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#define DBGBCR4 (*(volatile int *) (DBGBASE + 0x150))

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#define DBGBCR5 (*(volatile int *) (DBGBASE + 0x154))

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#define DBGBCR6 (*(volatile int *) (DBGBASE + 0x158))

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#define DBGBCR7 (*(volatile int *) (DBGBASE + 0x15C))

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/* Address range mask */

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#define DBGBCR_MASK_SHIFT 24

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#define DBGBCR_MASK_MASK 0x1F

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#define DBGBCR_MASK_NO_MASK 0

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#define DBGBCR_MASK_00000007 3

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#define DBGBCR_MASK_0000000F 4

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#define DBGBCR_MASK_0000001F 5

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#define DBGBCR_MASK_0000003F 6

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#define DBGBCR_MASK_0000007F 7

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#define DBGBCR_MASK_000000FF 8

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#define DBGBCR_MASK_000001FF 9

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#define DBGBCR_MASK_000003FF 10

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#define DBGBCR_MASK_000007FF 11

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#define DBGBCR_MASK_00000FFF 12

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#define DBGBCR_MASK_00001FFF 13

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#define DBGBCR_MASK_00003FFF 14

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#define DBGBCR_MASK_00007FFF 15

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#define DBGBCR_MASK_0000FFFF 16

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#define DBGBCR_MASK_0001FFFF 17

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#define DBGBCR_MASK_0003FFFF 18

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#define DBGBCR_MASK_0007FFFF 19

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#define DBGBCR_MASK_000FFFFF 20

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#define DBGBCR_MASK_001FFFFF 21

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#define DBGBCR_MASK_003FFFFF 22

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#define DBGBCR_MASK_007FFFFF 23

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#define DBGBCR_MASK_00FFFFFF 24

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#define DBGBCR_MASK_01FFFFFF 25

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#define DBGBCR_MASK_03FFFFFF 26

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#define DBGBCR_MASK_07FFFFFF 27

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#define DBGBCR_MASK_0FFFFFFF 28

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#define DBGBCR_MASK_1FFFFFFF 29

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#define DBGBCR_MASK_3FFFFFFF 30

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#define DBGBCR_MASK_7FFFFFFF 31

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/* Breakpoint type */

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#define DBGBCR_BT_SHIFT 20

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#define DBGBCR_BT_MASK 0xF

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#define DBGBCR_BT_UNLINKED_INSTR_ADDR_MATCH 0

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#define DBGBCR_BT_LINKED_INSTR_ADDR_MATCH 1

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#define DBGBCR_BT_UNLINKED_CONTEXT_ID_MATCH 2

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#define DBGBCR_BT_LINKED_CONTEXT_ID_MATCH 3

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#define DBGBCR_BT_UNLINKED_INSTR_ADDR_MISMATCH 4

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#define DBGBCR_BT_LINKED_INSTR_ADDR_MISMATCH 5

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/* Linked breakpoint number */

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#define DBGBCR_LBN_SHIFT 16

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#define DBGBCR_LBN_MASK 0xF

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/* Security state control */

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#define DBGBCR_SSC_SHIFT 14

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#define DBGBCR_SSC_MASK 3

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/* Hyp mode control bit */

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#define DBGBCR_HMC_SHIFT 13

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#define DBGBCR_HMC_MASK 1

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/* Byte address select */

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#define DBGBCR_BAS_SHIFT 5

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#define DBGBCR_BAS_MASK 0xF

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#define GET_BAS_FOR_THUMB_ADDR(addr) (3 << (addr & 2))

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/* Privileged mode control */

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#define DBGBCR_PMC_SHIFT 1

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#define DBGBCR_PMC_MASK 3

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/* combined options for SSC, HMC and PMC */

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/* secure and non secure modes */

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#define DBGBCR_SSC_HMC_PMC__PL0_SUP_SYS						(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 0))

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#define DBGBCR_SSC_HMC_PMC__PL1								(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 1))

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#define DBGBCR_SSC_HMC_PMC__PL0								(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 2))

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#define DBGBCR_SSC_HMC_PMC__SEC_ALL__NON_SEC_PL1_PL0		(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 3))

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#define DBGBCR_SSC_HMC_PMC__SEC_PL1__NON_SEC_PL2_PL1		(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 1) | SET_DBG_VALUE(DBGBCR_PMC, 1))

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#define DBGBCR_SSC_HMC_PMC__ALL								(SET_DBG_VALUE(DBGBCR_SSC, 0) | SET_DBG_VALUE(DBGBCR_HMC, 1) | SET_DBG_VALUE(DBGBCR_PMC, 3))

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/* only non-secure modes */

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL0_SUP_SYS				(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 0))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL2						(SET_DBG_VALUE(DBGBCR_SSC, 3) | SET_DBG_VALUE(DBGBCR_HMC, 1) | SET_DBG_VALUE(DBGBCR_PMC, 0))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL1						(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 1))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL0						(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 2))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL1_PL0					(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 3))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_PL2_PL1					(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 1) | SET_DBG_VALUE(DBGBCR_PMC, 1))

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#define DBGBCR_SSC_HMC_PMC__NON_SEC_ALL						(SET_DBG_VALUE(DBGBCR_SSC, 1) | SET_DBG_VALUE(DBGBCR_HMC, 1) | SET_DBG_VALUE(DBGBCR_PMC, 3))

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/* only secure modes */

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#define DBGBCR_SSC_HMC_PMC__SEC_PL0_SUP_SYS					(SET_DBG_VALUE(DBGBCR_SSC, 2) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 0))

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#define DBGBCR_SSC_HMC_PMC__SEC_PL1							(SET_DBG_VALUE(DBGBCR_SSC, 2) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 1))

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#define DBGBCR_SSC_HMC_PMC__SEC_PL0							(SET_DBG_VALUE(DBGBCR_SSC, 2) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 2))

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#define DBGBCR_SSC_HMC_PMC__SEC_ALL							(SET_DBG_VALUE(DBGBCR_SSC, 2) | SET_DBG_VALUE(DBGBCR_HMC, 0) | SET_DBG_VALUE(DBGBCR_PMC, 3))

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#define DBGBCR_SSC_HMC_PMC_SHIFT 0

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#define DBGBCR_SSC_HMC_PMC_MASK (GET_DBG_MASK(DBGBCR_SSC) | GET_DBG_MASK(DBGBCR_HMC) | GET_DBG_MASK(DBGBCR_PMC))

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/* Breakpoint enable */

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#define DBGBCR_E_SHIFT 0

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#define DBGBCR_E_MASK 1

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#define DBGBCR_E_DISABLED 0

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#define DBGBCR_E_ENABLED 1

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/* DBGLAR - Lock Access Register */

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#define DBGLAR (*(volatile int *) (DBGBASE + 0xFB0))

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#define DBGLAR_UNLOCK_CODE (0xC5ACCE55)

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/* Breakpoint numbers one-hot encoded */

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#define DBGBP0 (1 << 0)

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#define DBGBP1 (1 << 1)

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#define DBGBP2 (1 << 2)

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#define DBGBP3 (1 << 3)

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/* Watch numbers one-hot encoded */

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#define DBGWP0 (1 << 0)

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#define DBGWP1 (1 << 1)

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#define DBGWP2 (1 << 2)

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#define DBGWP3 (1 << 3)

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/* C11.11.46 DBGWVR - Watchpoint Value Registers */

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#define DBGWVR0 (*(volatile int *) (DBGBASE + 0x180))

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#define DBGWVR1 (*(volatile int *) (DBGBASE + 0x184))

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#define DBGWVR2 (*(volatile int *) (DBGBASE + 0x188))

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#define DBGWVR3 (*(volatile int *) (DBGBASE + 0x18C))

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#define DBGWVR4 (*(volatile int *) (DBGBASE + 0x190))

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#define DBGWVR5 (*(volatile int *) (DBGBASE + 0x194))

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#define DBGWVR6 (*(volatile int *) (DBGBASE + 0x198))

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#define DBGWVR7 (*(volatile int *) (DBGBASE + 0x19C))

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/* The last two bits of an address needs to be set to 0 */

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#define DBGWVR_ADDRMASK (0xFFFFFFFC)

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/* C11.11.44 DBGWCR - Watchpoint Control Registers */

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#define DBGWCR0 (*(volatile int *) (DBGBASE + 0x1C0))

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#define DBGWCR1 (*(volatile int *) (DBGBASE + 0x1C4))

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#define DBGWCR2 (*(volatile int *) (DBGBASE + 0x1C8))

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#define DBGWCR3 (*(volatile int *) (DBGBASE + 0x1CC))

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#define DBGWCR4 (*(volatile int *) (DBGBASE + 0x1D0))

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#define DBGWCR5 (*(volatile int *) (DBGBASE + 0x1D4))

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#define DBGWCR6 (*(volatile int *) (DBGBASE + 0x1D8))

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#define DBGWCR7 (*(volatile int *) (DBGBASE + 0x1DC))

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/* Address range mask */

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#define DBGWCR_MASK_SHIFT 24

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#define DBGWCR_MASK_MASK 0x1F

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#define DBGWCR_MASK_NO_MASK 0

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#define DBGWCR_MASK_00000007 3

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#define DBGWCR_MASK_0000000F 4

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#define DBGWCR_MASK_0000001F 5

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#define DBGWCR_MASK_0000003F 6

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#define DBGWCR_MASK_0000007F 7

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#define DBGWCR_MASK_000000FF 8

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#define DBGWCR_MASK_000001FF 9

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#define DBGWCR_MASK_000003FF 10

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#define DBGWCR_MASK_000007FF 11

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#define DBGWCR_MASK_00000FFF 12

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#define DBGWCR_MASK_00001FFF 13

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#define DBGWCR_MASK_00003FFF 14

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#define DBGWCR_MASK_00007FFF 15

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#define DBGWCR_MASK_0000FFFF 16

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#define DBGWCR_MASK_0001FFFF 17

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#define DBGWCR_MASK_0003FFFF 18

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#define DBGWCR_MASK_0007FFFF 19

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#define DBGWCR_MASK_000FFFFF 20

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#define DBGWCR_MASK_001FFFFF 21

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#define DBGWCR_MASK_003FFFFF 22

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#define DBGWCR_MASK_007FFFFF 23

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#define DBGWCR_MASK_00FFFFFF 24

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#define DBGWCR_MASK_01FFFFFF 25

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#define DBGWCR_MASK_03FFFFFF 26

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#define DBGWCR_MASK_07FFFFFF 27

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#define DBGWCR_MASK_0FFFFFFF 28

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#define DBGWCR_MASK_1FFFFFFF 29

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#define DBGWCR_MASK_3FFFFFFF 30

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#define DBGWCR_MASK_7FFFFFFF 31

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/* Watchpoint type */

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#define DBGWCR_WT_SHIFT 20

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#define DBGWCR_WT_MASK 1

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#define DBGWCR_WT_UNLINKED_DATA_ADDR_MATCH 0

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#define DBGWCR_WT_LINKED_DATA_ADDR_MATCH 1

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/* Linked watchpoint number */

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#define DBGWCR_LBN_SHIFT 16

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#define DBGWCR_LBN_MASK 0xF

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/* Security state control */

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#define DBGWCR_SSC_SHIFT 14

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#define DBGWCR_SSC_MASK 3

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/* Hyp mode control bit */

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#define DBGWCR_HMC_SHIFT 13

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#define DBGWCR_HMC_MASK 1

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/* Byte address select */

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#define DBGWCR_BAS_4BIT_SHIFT 5

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#define DBGWCR_BAS_4BIT_MASK 0xF

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#define DBGWCR_BAS_8BIT_SHIFT 5

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#define DBGWCR_BAS_8BIT_MASK 0xFF

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/* Load/store access control */

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#define DBGWCR_LSC_SHIFT 3

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#define DBGWCR_LSC_MASK 3

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#define DBGWCR_LSC_MATCH_LOAD 1

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#define DBGWCR_LSC_MATCH_STORE 2

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#define DBGWCR_LSC_MATCH_ALL 3

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/* Privileged access control */

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#define DBGWCR_PAC_SHIFT 1

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#define DBGWCR_PAC_MASK 3

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/* combined options for SSC, HMC and PAC */

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/* secure and non secure modes */

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#define DBGWCR_SSC_HMC_PAC__PL1								(SET_DBG_VALUE(DBGWCR_SSC, 0) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 1))

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#define DBGWCR_SSC_HMC_PAC__PL0								(SET_DBG_VALUE(DBGWCR_SSC, 0) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 2))

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#define DBGWCR_SSC_HMC_PAC__PL1_PL0							(SET_DBG_VALUE(DBGWCR_SSC, 0) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 3))

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#define DBGWCR_SSC_HMC_PAC__SEC_PL1__NON_SEC_PL2_PL1		(SET_DBG_VALUE(DBGWCR_SSC, 0) | SET_DBG_VALUE(DBGWCR_HMC, 1) | SET_DBG_VALUE(DBGWCR_PAC, 1))

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#define DBGWCR_SSC_HMC_PAC__ALL								(SET_DBG_VALUE(DBGWCR_SSC, 0) | SET_DBG_VALUE(DBGWCR_HMC, 1) | SET_DBG_VALUE(DBGWCR_PAC, 3))

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/* only non-secure modes */

401

#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL2						(SET_DBG_VALUE(DBGWCR_SSC, 3) | SET_DBG_VALUE(DBGWCR_HMC, 1) | SET_DBG_VALUE(DBGWCR_PAC, 0))

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#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL1						(SET_DBG_VALUE(DBGWCR_SSC, 1) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 1))

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#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL0						(SET_DBG_VALUE(DBGWCR_SSC, 1) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 2))

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#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL1_PL0					(SET_DBG_VALUE(DBGWCR_SSC, 1) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 3))

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#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL2_PL1					(SET_DBG_VALUE(DBGWCR_SSC, 1) | SET_DBG_VALUE(DBGWCR_HMC, 1) | SET_DBG_VALUE(DBGWCR_PAC, 1))

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#define DBGWCR_SSC_HMC_PAC__NON_SEC_PL2_PL1_PL0				(SET_DBG_VALUE(DBGWCR_SSC, 1) | SET_DBG_VALUE(DBGWCR_HMC, 1) | SET_DBG_VALUE(DBGWCR_PAC, 3))

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/* only secure modes */

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#define DBGWCR_SSC_HMC_PAC__SEC_PL1							(SET_DBG_VALUE(DBGWCR_SSC, 2) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 1))

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#define DBGWCR_SSC_HMC_PAC__SEC_PL0							(SET_DBG_VALUE(DBGWCR_SSC, 2) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 2))

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#define DBGWCR_SSC_HMC_PAC__SEC_PL1_PL0						(SET_DBG_VALUE(DBGWCR_SSC, 2) | SET_DBG_VALUE(DBGWCR_HMC, 0) | SET_DBG_VALUE(DBGWCR_PAC, 3))

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#define DBGWCR_SSC_HMC_PAC_SHIFT 0

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#define DBGWCR_SSC_HMC_PAC_MASK (GET_DBG_MASK(DBGWCR_SSC) | GET_DBG_MASK(DBGWCR_HMC) | GET_DBG_MASK(DBGWCR_PAC))

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/* Watchpoint enable */

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#define DBGWCR_E_SHIFT 0

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#define DBGWCR_E_MASK 1

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#define DBGWCR_E_DISABLED 0

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#define DBGWCR_E_ENABLED 1

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/* Processor modes */

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#define DBG_PROCESSOR_MODE_USR 0x10

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#define DBG_PROCESSOR_MODE_FIQ 0x11

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#define DBG_PROCESSOR_MODE_IRQ 0x12

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#define DBG_PROCESSOR_MODE_SVC 0x13

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#define DBG_PROCESSOR_MODE_ABT 0x17

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#define DBG_PROCESSOR_MODE_UND 0x1B

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#define DBG_PROCESSOR_MODE_SYS 0x1F

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/* debug helper macros */

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#define dbg_expand1(x) #x

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#define dbg_expand(x) dbg_expand1(x)

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#define dbg_change_processor_mode(mode) do { \

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asm("cps #" dbg_expand(mode) "\n"); \

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} while (0)

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#define dbg_unlock_debug_registers() do { \

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DBGLAR = DBGLAR_UNLOCK_CODE; \

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} while (0)

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#define dbg_enable_monitor_mode_debugging() do { \

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		DBGDSCR = UPDATE_DBG_REG(DBGDSCR, GET_DBG_MASK(DBGDSCR_MDBGen), SET_DBG_VALUE(DBGDSCR_MDBGen, DBGDSCR_MDBGen_ENABLED)); \

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} while (0)

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#define dbg_disable_monitor_mode_debugging() do { \

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		DBGDSCR = UPDATE_DBG_REG(DBGDSCR, GET_DBG_MASK(DBGDSCR_MDBGen), SET_DBG_VALUE(DBGDSCR_MDBGen, DBGDSCR_MDBGen_DISABLED)); \

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} while (0)

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#define dbg_enable_breakpoint(number) do { \

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		DBGBCR ## number = UPDATE_DBG_REG(DBGBCR ## number, GET_DBG_MASK(DBGBCR_E), SET_DBG_VALUE(DBGBCR_E, DBGBCR_E_ENABLED)); \

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} while (0)

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#define dbg_disable_breakpoint(number) do { \

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		DBGBCR ## number = UPDATE_DBG_REG(DBGBCR ## number, GET_DBG_MASK(DBGBCR_E), SET_DBG_VALUE(DBGBCR_E, DBGBCR_E_DISABLED)); \

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} while (0)

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#define dbg_set_breakpoint_type_to_instr_addr_match(number) do { \

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		DBGBCR ## number = UPDATE_DBG_REG(DBGBCR ## number, GET_DBG_MASK(DBGBCR_BT), SET_DBG_VALUE(DBGBCR_BT, DBGBCR_BT_UNLINKED_INSTR_ADDR_MATCH)); \

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} while (0)

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#define dbg_set_breakpoint_type_to_instr_addr_mismatch(number) do { \

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		DBGBCR ## number = UPDATE_DBG_REG(DBGBCR ## number, GET_DBG_MASK(DBGBCR_BT), SET_DBG_VALUE(DBGBCR_BT, DBGBCR_BT_UNLINKED_INSTR_ADDR_MISMATCH)); \

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} while (0)

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#define dbg_is_breakpoint_enabled(number) (GET_DBG_VALUE(DBGBCR_E, DBGBCR ## number))

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#define dbg_is_breakpoint_type_instr_addr_match(number) (GET_DBG_VALUE(DBGBCR_BT, DBGBCR ## number) == DBGBCR_BT_UNLINKED_INSTR_ADDR_MATCH)

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#define dbg_is_breakpoint_type_instr_addr_mismatch(number) (GET_DBG_VALUE(DBGBCR_BT, DBGBCR ## number) == DBGBCR_BT_UNLINKED_INSTR_ADDR_MISMATCH)

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#define dbg_triggers_on_breakpoint_address(number, address) ((DBGBVR ## number == (address & DBGBVR_ADDRMASK)) && (GET_DBG_VALUE(DBGBCR_BAS, DBGBCR ## number) == GET_BAS_FOR_THUMB_ADDR(address)))

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#define dbg_set_breakpoint_for_addr_match(number, address) do { \

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DBGBCR ## number = 0x0; \

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DBGBVR ## number = (address) & DBGBVR_ADDRMASK; \

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DBGBCR ## number = \

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SET_DBG_VALUE(DBGBCR_BT, DBGBCR_BT_UNLINKED_INSTR_ADDR_MATCH) | \

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SET_DBG_VALUE(DBGBCR_MASK, DBGBCR_MASK_NO_MASK) | \

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SET_DBG_VALUE(DBGBCR_E, DBGBCR_E_ENABLED) | \

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SET_DBG_VALUE(DBGBCR_SSC_HMC_PMC, DBGBCR_SSC_HMC_PMC__PL0_SUP_SYS) | \

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SET_DBG_VALUE(DBGBCR_BAS, GET_BAS_FOR_THUMB_ADDR(address)); \

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} while (0)

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#define dbg_set_breakpoint_for_addr_mismatch(number, address) do { \

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DBGBCR ## number = 0x0; \

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DBGBVR ## number = (address) & DBGBVR_ADDRMASK; \

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DBGBCR ## number = \

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SET_DBG_VALUE(DBGBCR_BT, DBGBCR_BT_UNLINKED_INSTR_ADDR_MISMATCH) | \

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SET_DBG_VALUE(DBGBCR_MASK, DBGBCR_MASK_NO_MASK) | \

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SET_DBG_VALUE(DBGBCR_E, DBGBCR_E_ENABLED) | \

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SET_DBG_VALUE(DBGBCR_SSC_HMC_PMC, DBGBCR_SSC_HMC_PMC__PL0_SUP_SYS) | \

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SET_DBG_VALUE(DBGBCR_BAS, GET_BAS_FOR_THUMB_ADDR(address)); \

} while (0)

#define dbg_enable_watchpoint(number) do { \

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		DBGWCR ## number = UPDATE_DBG_REG(DBGWCR ## number, GET_DBG_MASK(DBGWCR_E), SET_DBG_VALUE(DBGWCR_E, DBGWCR_E_ENABLED)); \

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} while (0)

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#define dbg_disable_watchpoint(number) do { \

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		DBGWCR ## number = UPDATE_DBG_REG(DBGWCR ## number, GET_DBG_MASK(DBGWCR_E), SET_DBG_VALUE(DBGWCR_E, DBGWCR_E_DISABLED)); \

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} while (0)

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#define dbg_set_watchpoint_for_addr_match(number, address) do { \

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DBGWCR ## number = 0x0; \

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DBGWVR ## number = (address) & DBGWVR_ADDRMASK; \

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DBGWCR ## number = \

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SET_DBG_VALUE(DBGWCR_WT, DBGWCR_WT_UNLINKED_DATA_ADDR_MATCH) | \

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SET_DBG_VALUE(DBGWCR_MASK, DBGWCR_MASK_NO_MASK) | \

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SET_DBG_VALUE(DBGWCR_E, DBGWCR_E_ENABLED) | \

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SET_DBG_VALUE(DBGWCR_SSC_HMC_PAC, DBGWCR_SSC_HMC_PAC__ALL) | \

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SET_DBG_VALUE(DBGWCR_LSC, DBGWCR_LSC_MATCH_ALL) | \

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SET_DBG_VALUE(DBGWCR_BAS_4BIT, 0xF); \

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} while (0)

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#define dbg_set_watchpoint_for_addr_match_with_mask(number, address, mask) do { \

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DBGWCR ## number = 0x0; \

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DBGWVR ## number = (address) & DBGWVR_ADDRMASK; \

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DBGWCR ## number = \

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SET_DBG_VALUE(DBGWCR_WT, DBGWCR_WT_UNLINKED_DATA_ADDR_MATCH) | \

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SET_DBG_VALUE(DBGWCR_MASK, mask) | \

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SET_DBG_VALUE(DBGWCR_E, DBGWCR_E_ENABLED) | \

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SET_DBG_VALUE(DBGWCR_SSC_HMC_PAC, DBGWCR_SSC_HMC_PAC__ALL) | \

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SET_DBG_VALUE(DBGWCR_LSC, DBGWCR_LSC_MATCH_ALL) | \

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SET_DBG_VALUE(DBGWCR_BAS_4BIT, 0xF); \

} while (0)

#endif /* DEBUG_H */

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