nexmon – Blame information for rev 1

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Rev Author Line No. Line
1 office 1 diff --git a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/.core.h.swp b/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/.core.h.swp
2 deleted file mode 100644
3 index 2b0426f..0000000
4 Binary files a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/.core.h.swp and /dev/null differ
5 diff --git a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/Makefile b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/Makefile
6 index 0383ba5..adc13fa 100644
7 --- a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/Makefile
8 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/Makefile
9 @@ -16,8 +16,8 @@
10 # CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11  
12 ccflags-y += \
13 - -Idrivers/net/wireless/broadcom/brcm80211/brcmfmac \
14 - -Idrivers/net/wireless/broadcom/brcm80211/include
15 + -Idrivers/net/wireless/brcm80211/brcmfmac \
16 + -I$(NEXMON_ROOT)/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include
17  
18 obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
19 brcmfmac-objs += \
20 diff --git a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/core.c
21 index da8aad4..733673d 100644
22 --- a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
23 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/core.c
24 @@ -17,6 +17,9 @@
25 #include <linux/kernel.h>
26 #include <linux/etherdevice.h>
27 #include <linux/module.h>
28 +/* NEXMON */
29 +#include <linux/if_arp.h>
30 +#include <linux/netlink.h>
31 #include <linux/inetdevice.h>
32 #include <net/cfg80211.h>
33 #include <net/rtnetlink.h>
34 @@ -37,11 +40,121 @@
35 #include "proto.h"
36 #include "pcie.h"
37 #include "common.h"
38 +/* NEXMON */
39 +#include "nexmon_procfs.h"
40 +#include "nexmon_ioctls.h"
41 +
42  
43 #define MAX_WAIT_FOR_8021X_TX msecs_to_jiffies(950)
44  
45 #define BRCMF_BSSIDX_INVALID -1
46  
47 +/* Nexmon */
48 +#define NETLINK_USER 31
49 +#define NEXUDP_IOCTL 0
50 +
51 +#define MONITOR_DISABLED 0
52 +#define MONITOR_IEEE80211 1
53 +#define MONITOR_RADIOTAP 2
54 +#define MONITOR_LOG_ONLY 3
55 +#define MONITOR_DROP_FRM 4
56 +#define MONITOR_IPV4_UDP 5
57 +
58 +static struct netlink_kernel_cfg cfg = {0};
59 +static struct sock *nl_sock = NULL;
60 +static struct net_device *ndev_global = NULL;
61 +
62 +struct nexudp_header {
63 + char nex[3];
64 + char type;
65 + int securitycookie;
66 +} __attribute__((packed));
67 +
68 +struct nexudp_ioctl_header {
69 + struct nexudp_header nexudphdr;
70 + unsigned int cmd;
71 + unsigned int set;
72 + char payload[1];
73 +} __attribute__((packed));
74 +
75 +static void
76 +nexmon_nl_ioctl_handler(struct sk_buff *skb)
77 +{
78 + struct nlmsghdr *nlh = (struct nlmsghdr *) skb->data;
79 + struct nexudp_ioctl_header *frame = (struct nexudp_ioctl_header *) nlmsg_data(nlh);
80 + struct brcmf_if *ifp = netdev_priv(ndev_global);
81 + struct sk_buff *skb_out;
82 + struct nlmsghdr *nlh_tx;
83 +
84 + brcmf_err("NEXMON: %s: Enter\n", __FUNCTION__);
85 +
86 + brcmf_err("NEXMON: %s: %08x %d %d\n", __FUNCTION__, *(int *) frame->nexudphdr.nex, nlmsg_len(nlh), skb->len);
87 +
88 + if (memcmp(frame->nexudphdr.nex, "NEX", 3)) {
89 + brcmf_err("NEXMON: %s: invalid nexudp_ioctl_header\n", __FUNCTION__);
90 + return;
91 + }
92 +
93 + if (frame->nexudphdr.type != NEXUDP_IOCTL) {
94 + brcmf_err("NEXMON: %s: invalid frame type\n", __FUNCTION__);
95 + return;
96 + }
97 +
98 + if (ifp == NULL) {
99 + brcmf_err("NEXMON: %s: ifp is NULL\n", __FUNCTION__);
100 + return;
101 + }
102 +
103 + if (frame->set) {
104 + brcmf_err("NEXMON: %s: calling brcmf_fil_cmd_data_set, cmd: %d\n", __FUNCTION__, frame->cmd);
105 + brcmf_fil_cmd_data_set(ifp, frame->cmd, frame->payload, nlmsg_len(nlh) - sizeof(struct nexudp_ioctl_header) + sizeof(char));
106 +
107 + if (frame->cmd == 108) { // WLC_SET_MONITOR
108 + brcmf_err("NEXMON: %s: WLC_SET_MONITOR = %d\n", __FUNCTION__, *(unsigned int *) frame->payload);
109 + switch(*(unsigned int *) frame->payload) {
110 + case MONITOR_IEEE80211:
111 + ndev_global->type = ARPHRD_IEEE80211;
112 + ndev_global->ieee80211_ptr->iftype = NL80211_IFTYPE_MONITOR;
113 + ndev_global->ieee80211_ptr->wiphy->interface_modes = BIT(NL80211_IFTYPE_MONITOR);
114 + break;
115 +
116 + case MONITOR_RADIOTAP:
117 + ndev_global->type = ARPHRD_IEEE80211_RADIOTAP;
118 + ndev_global->ieee80211_ptr->iftype = NL80211_IFTYPE_MONITOR;
119 + ndev_global->ieee80211_ptr->wiphy->interface_modes = BIT(NL80211_IFTYPE_MONITOR);
120 + break;
121 +
122 + case MONITOR_DISABLED:
123 + case MONITOR_LOG_ONLY:
124 + case MONITOR_DROP_FRM:
125 + case MONITOR_IPV4_UDP:
126 + default:
127 + ndev_global->type = ARPHRD_ETHER;
128 + ndev_global->ieee80211_ptr->iftype = NL80211_IFTYPE_STATION;
129 + ndev_global->ieee80211_ptr->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
130 + break;
131 + }
132 + }
133 +
134 + skb_out = nlmsg_new(4, 0);
135 + nlh_tx = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, 4, 0);
136 + NETLINK_CB(skb_out).dst_group = 0; /* not in mcast group */
137 + memcpy(nlmsg_data(nlh_tx), "ACK", 4);
138 + nlmsg_unicast(nl_sock, skb_out, nlh->nlmsg_pid);
139 + } else {
140 + brcmf_err("NEXMON: %s: calling brcmf_fil_cmd_data_get, cmd: %d\n", __FUNCTION__, frame->cmd);
141 + brcmf_fil_cmd_data_get(ifp, frame->cmd, frame->payload, nlmsg_len(nlh) - sizeof(struct nexudp_ioctl_header) + sizeof(char));
142 +
143 + skb_out = nlmsg_new(nlmsg_len(nlh), 0);
144 + nlh_tx = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, nlmsg_len(nlh), 0);
145 + NETLINK_CB(skb_out).dst_group = 0; /* not in mcast group */
146 + memcpy(nlmsg_data(nlh_tx), frame, nlmsg_len(nlh));
147 + nlmsg_unicast(nl_sock, skb_out, nlh->nlmsg_pid);
148 + }
149 +
150 + brcmf_err("NEXMON: %s: Exit\n", __FUNCTION__);
151 +}
152 +
153 char *brcmf_ifname(struct brcmf_if *ifp)
154 {
155 if (!ifp)
156 @@ -501,6 +614,9 @@ int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
157 ifp->mac_addr);
158 ndev = ifp->ndev;
159  
160 + /* NEXMON */
161 + ndev_global = ndev;
162 +
163 /* set appropriate operations */
164 ndev->netdev_ops = &brcmf_netdev_ops_pri;
165  
166 @@ -1197,9 +1313,20 @@ static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register);
167  
168 int __init brcmf_core_init(void)
169 {
170 + /* NEXMON procfs */
171 + proc_create("nexmon_consoledump", 0, NULL, &rom_proc_dump_fops);
172 +
173 if (!schedule_work(&brcmf_driver_work))
174 return -EBUSY;
175  
176 + /* NEXMON netlink init */
177 + cfg.input = nexmon_nl_ioctl_handler;
178 + nl_sock = netlink_kernel_create(&init_net, NETLINK_USER, &cfg);
179 + if (!nl_sock) {
180 + brcmf_err("NEXMON: %s: Error creating netlink socket, &init_net: 0x%x, &cfg: 0x%x\n", __FUNCTION__, &init_net, &cfg);
181 + return -1;
182 + }
183 +
184 return 0;
185 }
186  
187 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcm_hw_ids.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcm_hw_ids.h
188 new file mode 100644
189 index 0000000..f1fb8a3
190 --- /dev/null
191 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcm_hw_ids.h
192 @@ -0,0 +1,102 @@
193 +/*
194 + * Copyright (c) 2010 Broadcom Corporation
195 + *
196 + * Permission to use, copy, modify, and/or distribute this software for any
197 + * purpose with or without fee is hereby granted, provided that the above
198 + * copyright notice and this permission notice appear in all copies.
199 + *
200 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
201 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
202 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
203 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
204 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
205 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
206 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
207 + */
208 +
209 +#ifndef _BRCM_HW_IDS_H_
210 +#define _BRCM_HW_IDS_H_
211 +
212 +#include <linux/pci_ids.h>
213 +#include <linux/mmc/sdio_ids.h>
214 +
215 +#define BRCM_USB_VENDOR_ID_BROADCOM 0x0a5c
216 +#define BRCM_USB_VENDOR_ID_LG 0x043e
217 +#define BRCM_USB_VENDOR_ID_LINKSYS 0x13b1
218 +#define BRCM_PCIE_VENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
219 +
220 +/* Chipcommon Core Chip IDs */
221 +#define BRCM_CC_43143_CHIP_ID 43143
222 +#define BRCM_CC_43235_CHIP_ID 43235
223 +#define BRCM_CC_43236_CHIP_ID 43236
224 +#define BRCM_CC_43238_CHIP_ID 43238
225 +#define BRCM_CC_43241_CHIP_ID 0x4324
226 +#define BRCM_CC_43242_CHIP_ID 43242
227 +#define BRCM_CC_4329_CHIP_ID 0x4329
228 +#define BRCM_CC_4330_CHIP_ID 0x4330
229 +#define BRCM_CC_4334_CHIP_ID 0x4334
230 +#define BRCM_CC_43340_CHIP_ID 43340
231 +#define BRCM_CC_43341_CHIP_ID 43341
232 +#define BRCM_CC_43362_CHIP_ID 43362
233 +#define BRCM_CC_4335_CHIP_ID 0x4335
234 +#define BRCM_CC_4339_CHIP_ID 0x4339
235 +#define BRCM_CC_43430_CHIP_ID 43430
236 +#define BRCM_CC_4345_CHIP_ID 0x4345
237 +#define BRCM_CC_43465_CHIP_ID 43465
238 +#define BRCM_CC_4350_CHIP_ID 0x4350
239 +#define BRCM_CC_43525_CHIP_ID 43525
240 +#define BRCM_CC_4354_CHIP_ID 0x4354
241 +#define BRCM_CC_4356_CHIP_ID 0x4356
242 +#define BRCM_CC_43566_CHIP_ID 43566
243 +#define BRCM_CC_43567_CHIP_ID 43567
244 +#define BRCM_CC_43569_CHIP_ID 43569
245 +#define BRCM_CC_43570_CHIP_ID 43570
246 +#define BRCM_CC_4358_CHIP_ID 0x4358
247 +#define BRCM_CC_4359_CHIP_ID 0x4359
248 +#define BRCM_CC_43602_CHIP_ID 43602
249 +#define BRCM_CC_4365_CHIP_ID 0x4365
250 +#define BRCM_CC_4366_CHIP_ID 0x4366
251 +#define BRCM_CC_4371_CHIP_ID 0x4371
252 +
253 +/* USB Device IDs */
254 +#define BRCM_USB_43143_DEVICE_ID 0xbd1e
255 +#define BRCM_USB_43235_LINKSYS_DEVICE_ID 0x0039
256 +#define BRCM_USB_43236_DEVICE_ID 0xbd17
257 +#define BRCM_USB_43242_DEVICE_ID 0xbd1f
258 +#define BRCM_USB_43242_LG_DEVICE_ID 0x3101
259 +#define BRCM_USB_43569_DEVICE_ID 0xbd27
260 +#define BRCM_USB_BCMFW_DEVICE_ID 0x0bdc
261 +
262 +/* PCIE Device IDs */
263 +#define BRCM_PCIE_4350_DEVICE_ID 0x43a3
264 +#define BRCM_PCIE_4354_DEVICE_ID 0x43df
265 +#define BRCM_PCIE_4356_DEVICE_ID 0x43ec
266 +#define BRCM_PCIE_43567_DEVICE_ID 0x43d3
267 +#define BRCM_PCIE_43570_DEVICE_ID 0x43d9
268 +#define BRCM_PCIE_4358_DEVICE_ID 0x43e9
269 +#define BRCM_PCIE_4359_DEVICE_ID 0x43ef
270 +#define BRCM_PCIE_43602_DEVICE_ID 0x43ba
271 +#define BRCM_PCIE_43602_2G_DEVICE_ID 0x43bb
272 +#define BRCM_PCIE_43602_5G_DEVICE_ID 0x43bc
273 +#define BRCM_PCIE_43602_RAW_DEVICE_ID 43602
274 +#define BRCM_PCIE_4365_DEVICE_ID 0x43ca
275 +#define BRCM_PCIE_4365_2G_DEVICE_ID 0x43cb
276 +#define BRCM_PCIE_4365_5G_DEVICE_ID 0x43cc
277 +#define BRCM_PCIE_4366_DEVICE_ID 0x43c3
278 +#define BRCM_PCIE_4366_2G_DEVICE_ID 0x43c4
279 +#define BRCM_PCIE_4366_5G_DEVICE_ID 0x43c5
280 +#define BRCM_PCIE_4371_DEVICE_ID 0x440d
281 +
282 +
283 +/* brcmsmac IDs */
284 +#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
285 +#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
286 +#define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
287 +#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
288 +#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
289 +#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
290 +
291 +#define BCM4313_CHIP_ID 0x4313
292 +#define BCM43224_CHIP_ID 43224
293 +
294 +#endif /* _BRCM_HW_IDS_H_ */
295 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_d11.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_d11.h
296 new file mode 100644
297 index 0000000..8b8b2ec
298 --- /dev/null
299 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_d11.h
300 @@ -0,0 +1,167 @@
301 +/*
302 + * Copyright (c) 2010 Broadcom Corporation
303 + *
304 + * Permission to use, copy, modify, and/or distribute this software for any
305 + * purpose with or without fee is hereby granted, provided that the above
306 + * copyright notice and this permission notice appear in all copies.
307 + *
308 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
309 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
310 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
311 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
312 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
313 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
314 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
315 + */
316 +
317 +#ifndef _BRCMU_D11_H_
318 +#define _BRCMU_D11_H_
319 +
320 +/* d11 io type */
321 +#define BRCMU_D11N_IOTYPE 1
322 +#define BRCMU_D11AC_IOTYPE 2
323 +
324 +/* A chanspec (channel specification) holds the channel number, band,
325 + * bandwidth and control sideband
326 + */
327 +
328 +/* chanspec binary format */
329 +
330 +#define BRCMU_CHSPEC_INVALID 255
331 +/* bit 0~7 channel number
332 + * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
333 + */
334 +#define BRCMU_CHSPEC_CH_MASK 0x00ff
335 +#define BRCMU_CHSPEC_CH_SHIFT 0
336 +#define BRCMU_CHSPEC_CHL_MASK 0x000f
337 +#define BRCMU_CHSPEC_CHL_SHIFT 0
338 +#define BRCMU_CHSPEC_CHH_MASK 0x00f0
339 +#define BRCMU_CHSPEC_CHH_SHIFT 4
340 +
341 +/* bit 8~16 for dot 11n IO types
342 + * bit 8~9 sideband
343 + * bit 10~11 bandwidth
344 + * bit 12~13 spectral band
345 + * bit 14~15 not used
346 + */
347 +#define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
348 +#define BRCMU_CHSPEC_D11N_SB_SHIFT 8
349 +#define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
350 +#define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
351 +#define BRCMU_CHSPEC_D11N_SB_N 0x0300 /* none */
352 +#define BRCMU_CHSPEC_D11N_BW_MASK 0x0c00
353 +#define BRCMU_CHSPEC_D11N_BW_SHIFT 10
354 +#define BRCMU_CHSPEC_D11N_BW_10 0x0400
355 +#define BRCMU_CHSPEC_D11N_BW_20 0x0800
356 +#define BRCMU_CHSPEC_D11N_BW_40 0x0c00
357 +#define BRCMU_CHSPEC_D11N_BND_MASK 0x3000
358 +#define BRCMU_CHSPEC_D11N_BND_SHIFT 12
359 +#define BRCMU_CHSPEC_D11N_BND_5G 0x1000
360 +#define BRCMU_CHSPEC_D11N_BND_2G 0x2000
361 +
362 +/* bit 8~16 for dot 11ac IO types
363 + * bit 8~10 sideband
364 + * bit 11~13 bandwidth
365 + * bit 14~15 spectral band
366 + */
367 +#define BRCMU_CHSPEC_D11AC_SB_MASK 0x0700
368 +#define BRCMU_CHSPEC_D11AC_SB_SHIFT 8
369 +#define BRCMU_CHSPEC_D11AC_SB_LLL 0x0000
370 +#define BRCMU_CHSPEC_D11AC_SB_LLU 0x0100
371 +#define BRCMU_CHSPEC_D11AC_SB_LUL 0x0200
372 +#define BRCMU_CHSPEC_D11AC_SB_LUU 0x0300
373 +#define BRCMU_CHSPEC_D11AC_SB_ULL 0x0400
374 +#define BRCMU_CHSPEC_D11AC_SB_ULU 0x0500
375 +#define BRCMU_CHSPEC_D11AC_SB_UUL 0x0600
376 +#define BRCMU_CHSPEC_D11AC_SB_UUU 0x0700
377 +#define BRCMU_CHSPEC_D11AC_SB_LL BRCMU_CHSPEC_D11AC_SB_LLL
378 +#define BRCMU_CHSPEC_D11AC_SB_LU BRCMU_CHSPEC_D11AC_SB_LLU
379 +#define BRCMU_CHSPEC_D11AC_SB_UL BRCMU_CHSPEC_D11AC_SB_LUL
380 +#define BRCMU_CHSPEC_D11AC_SB_UU BRCMU_CHSPEC_D11AC_SB_LUU
381 +#define BRCMU_CHSPEC_D11AC_SB_L BRCMU_CHSPEC_D11AC_SB_LLL
382 +#define BRCMU_CHSPEC_D11AC_SB_U BRCMU_CHSPEC_D11AC_SB_LLU
383 +#define BRCMU_CHSPEC_D11AC_BW_MASK 0x3800
384 +#define BRCMU_CHSPEC_D11AC_BW_SHIFT 11
385 +#define BRCMU_CHSPEC_D11AC_BW_5 0x0000
386 +#define BRCMU_CHSPEC_D11AC_BW_10 0x0800
387 +#define BRCMU_CHSPEC_D11AC_BW_20 0x1000
388 +#define BRCMU_CHSPEC_D11AC_BW_40 0x1800
389 +#define BRCMU_CHSPEC_D11AC_BW_80 0x2000
390 +#define BRCMU_CHSPEC_D11AC_BW_160 0x2800
391 +#define BRCMU_CHSPEC_D11AC_BW_8080 0x3000
392 +#define BRCMU_CHSPEC_D11AC_BND_MASK 0xc000
393 +#define BRCMU_CHSPEC_D11AC_BND_SHIFT 14
394 +#define BRCMU_CHSPEC_D11AC_BND_2G 0x0000
395 +#define BRCMU_CHSPEC_D11AC_BND_3G 0x4000
396 +#define BRCMU_CHSPEC_D11AC_BND_4G 0x8000
397 +#define BRCMU_CHSPEC_D11AC_BND_5G 0xc000
398 +
399 +#define BRCMU_CHAN_BAND_2G 0
400 +#define BRCMU_CHAN_BAND_5G 1
401 +
402 +enum brcmu_chan_bw {
403 + BRCMU_CHAN_BW_20,
404 + BRCMU_CHAN_BW_40,
405 + BRCMU_CHAN_BW_80,
406 + BRCMU_CHAN_BW_80P80,
407 + BRCMU_CHAN_BW_160,
408 +};
409 +
410 +enum brcmu_chan_sb {
411 + BRCMU_CHAN_SB_NONE = -1,
412 + BRCMU_CHAN_SB_LLL,
413 + BRCMU_CHAN_SB_LLU,
414 + BRCMU_CHAN_SB_LUL,
415 + BRCMU_CHAN_SB_LUU,
416 + BRCMU_CHAN_SB_ULL,
417 + BRCMU_CHAN_SB_ULU,
418 + BRCMU_CHAN_SB_UUL,
419 + BRCMU_CHAN_SB_UUU,
420 + BRCMU_CHAN_SB_L = BRCMU_CHAN_SB_LLL,
421 + BRCMU_CHAN_SB_U = BRCMU_CHAN_SB_LLU,
422 + BRCMU_CHAN_SB_LL = BRCMU_CHAN_SB_LLL,
423 + BRCMU_CHAN_SB_LU = BRCMU_CHAN_SB_LLU,
424 + BRCMU_CHAN_SB_UL = BRCMU_CHAN_SB_LUL,
425 + BRCMU_CHAN_SB_UU = BRCMU_CHAN_SB_LUU,
426 +};
427 +
428 +/**
429 + * struct brcmu_chan - stores channel formats
430 + *
431 + * This structure can be used with functions translating chanspec into generic
432 + * channel info and the other way.
433 + *
434 + * @chspec: firmware specific format
435 + * @chnum: center channel number
436 + * @control_ch_num: control channel number
437 + * @band: frequency band
438 + * @bw: channel width
439 + * @sb: control sideband (location of control channel against the center one)
440 + */
441 +struct brcmu_chan {
442 + u16 chspec;
443 + u8 chnum;
444 + u8 control_ch_num;
445 + u8 band;
446 + enum brcmu_chan_bw bw;
447 + enum brcmu_chan_sb sb;
448 +};
449 +
450 +/**
451 + * struct brcmu_d11inf - provides functions translating channel format
452 + *
453 + * @io_type: determines version of channel format used by firmware
454 + * @encchspec: encodes channel info into a chanspec, requires center channel
455 + * number, ignores control one
456 + * @decchspec: decodes chanspec into generic info
457 + */
458 +struct brcmu_d11inf {
459 + u8 io_type;
460 +
461 + void (*encchspec)(struct brcmu_chan *ch);
462 + void (*decchspec)(struct brcmu_chan *ch);
463 +};
464 +
465 +void brcmu_d11_attach(struct brcmu_d11inf *d11inf);
466 +
467 +#endif /* _BRCMU_CHANNELS_H_ */
468 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_utils.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_utils.h
469 new file mode 100644
470 index 0000000..4196952
471 --- /dev/null
472 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_utils.h
473 @@ -0,0 +1,227 @@
474 +/*
475 + * Copyright (c) 2010 Broadcom Corporation
476 + *
477 + * Permission to use, copy, modify, and/or distribute this software for any
478 + * purpose with or without fee is hereby granted, provided that the above
479 + * copyright notice and this permission notice appear in all copies.
480 + *
481 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
482 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
483 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
484 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
485 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
486 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
487 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
488 + */
489 +
490 +#ifndef _BRCMU_UTILS_H_
491 +#define _BRCMU_UTILS_H_
492 +
493 +#include <linux/skbuff.h>
494 +
495 +/*
496 + * Spin at most 'us' microseconds while 'exp' is true.
497 + * Caller should explicitly test 'exp' when this completes
498 + * and take appropriate error action if 'exp' is still true.
499 + */
500 +#define SPINWAIT(exp, us) { \
501 + uint countdown = (us) + 9; \
502 + while ((exp) && (countdown >= 10)) {\
503 + udelay(10); \
504 + countdown -= 10; \
505 + } \
506 +}
507 +
508 +/* osl multi-precedence packet queue */
509 +#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
510 +#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
511 +
512 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
513 +
514 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
515 +#define PKTBUFSZ 2048
516 +
517 +#ifndef setbit
518 +#ifndef NBBY /* the BSD family defines NBBY */
519 +#define NBBY 8 /* 8 bits per byte */
520 +#endif /* #ifndef NBBY */
521 +#define setbit(a, i) (((u8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
522 +#define clrbit(a, i) (((u8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
523 +#define isset(a, i) (((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
524 +#define isclr(a, i) ((((const u8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
525 +#endif /* setbit */
526 +
527 +#define NBITS(type) (sizeof(type) * 8)
528 +#define NBITVAL(nbits) (1 << (nbits))
529 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
530 +#define NBITMASK(nbits) MAXBITVAL(nbits)
531 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
532 +
533 +/* crc defines */
534 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
535 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
536 +
537 +/* 18-bytes of Ethernet address buffer length */
538 +#define ETHER_ADDR_STR_LEN 18
539 +
540 +struct pktq_prec {
541 + struct sk_buff_head skblist;
542 + u16 max; /* maximum number of queued packets */
543 +};
544 +
545 +/* multi-priority pkt queue */
546 +struct pktq {
547 + u16 num_prec; /* number of precedences in use */
548 + u16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
549 + u16 max; /* total max packets */
550 + u16 len; /* total number of packets */
551 + /*
552 + * q array must be last since # of elements can be either
553 + * PKTQ_MAX_PREC or 1
554 + */
555 + struct pktq_prec q[PKTQ_MAX_PREC];
556 +};
557 +
558 +/* operations on a specific precedence in packet queue */
559 +
560 +static inline int pktq_plen(struct pktq *pq, int prec)
561 +{
562 + return pq->q[prec].skblist.qlen;
563 +}
564 +
565 +static inline int pktq_pavail(struct pktq *pq, int prec)
566 +{
567 + return pq->q[prec].max - pq->q[prec].skblist.qlen;
568 +}
569 +
570 +static inline bool pktq_pfull(struct pktq *pq, int prec)
571 +{
572 + return pq->q[prec].skblist.qlen >= pq->q[prec].max;
573 +}
574 +
575 +static inline bool pktq_pempty(struct pktq *pq, int prec)
576 +{
577 + return skb_queue_empty(&pq->q[prec].skblist);
578 +}
579 +
580 +static inline struct sk_buff *pktq_ppeek(struct pktq *pq, int prec)
581 +{
582 + return skb_peek(&pq->q[prec].skblist);
583 +}
584 +
585 +static inline struct sk_buff *pktq_ppeek_tail(struct pktq *pq, int prec)
586 +{
587 + return skb_peek_tail(&pq->q[prec].skblist);
588 +}
589 +
590 +struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec, struct sk_buff *p);
591 +struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
592 + struct sk_buff *p);
593 +struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
594 +struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
595 +struct sk_buff *brcmu_pktq_pdeq_match(struct pktq *pq, int prec,
596 + bool (*match_fn)(struct sk_buff *p,
597 + void *arg),
598 + void *arg);
599 +
600 +/* packet primitives */
601 +struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
602 +void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
603 +
604 +/* Empty the queue at particular precedence level */
605 +/* callback function fn(pkt, arg) returns true if pkt belongs to if */
606 +void brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir,
607 + bool (*fn)(struct sk_buff *, void *), void *arg);
608 +
609 +/* operations on a set of precedences in packet queue */
610 +
611 +int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
612 +struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
613 +
614 +/* operations on packet queue as a whole */
615 +
616 +static inline int pktq_len(struct pktq *pq)
617 +{
618 + return (int)pq->len;
619 +}
620 +
621 +static inline int pktq_max(struct pktq *pq)
622 +{
623 + return (int)pq->max;
624 +}
625 +
626 +static inline int pktq_avail(struct pktq *pq)
627 +{
628 + return (int)(pq->max - pq->len);
629 +}
630 +
631 +static inline bool pktq_full(struct pktq *pq)
632 +{
633 + return pq->len >= pq->max;
634 +}
635 +
636 +static inline bool pktq_empty(struct pktq *pq)
637 +{
638 + return pq->len == 0;
639 +}
640 +
641 +void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
642 +/* prec_out may be NULL if caller is not interested in return value */
643 +struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
644 +void brcmu_pktq_flush(struct pktq *pq, bool dir,
645 + bool (*fn)(struct sk_buff *, void *), void *arg);
646 +
647 +/* externs */
648 +/* ip address */
649 +struct ipv4_addr;
650 +
651 +/*
652 + * bitfield macros using masking and shift
653 + *
654 + * remark: the mask parameter should be a shifted mask.
655 + */
656 +static inline void brcmu_maskset32(u32 *var, u32 mask, u8 shift, u32 value)
657 +{
658 + value = (value << shift) & mask;
659 + *var = (*var & ~mask) | value;
660 +}
661 +static inline u32 brcmu_maskget32(u32 var, u32 mask, u8 shift)
662 +{
663 + return (var & mask) >> shift;
664 +}
665 +static inline void brcmu_maskset16(u16 *var, u16 mask, u8 shift, u16 value)
666 +{
667 + value = (value << shift) & mask;
668 + *var = (*var & ~mask) | value;
669 +}
670 +static inline u16 brcmu_maskget16(u16 var, u16 mask, u8 shift)
671 +{
672 + return (var & mask) >> shift;
673 +}
674 +
675 +/* externs */
676 +/* format/print */
677 +#ifdef DEBUG
678 +void brcmu_prpkt(const char *msg, struct sk_buff *p0);
679 +#else
680 +#define brcmu_prpkt(a, b)
681 +#endif /* DEBUG */
682 +
683 +#ifdef DEBUG
684 +__printf(3, 4)
685 +void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...);
686 +#else
687 +__printf(3, 4)
688 +static inline
689 +void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...)
690 +{
691 +}
692 +#endif
693 +
694 +#define BRCMU_BOARDREV_LEN 8
695 +#define BRCMU_DOTREV_LEN 16
696 +
697 +char *brcmu_boardrev_str(u32 brev, char *buf);
698 +char *brcmu_dotrev_str(u32 dotrev, char *buf);
699 +
700 +#endif /* _BRCMU_UTILS_H_ */
701 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_wifi.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_wifi.h
702 new file mode 100644
703 index 0000000..7b9a779
704 --- /dev/null
705 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/brcmu_wifi.h
706 @@ -0,0 +1,253 @@
707 +/*
708 + * Copyright (c) 2010 Broadcom Corporation
709 + *
710 + * Permission to use, copy, modify, and/or distribute this software for any
711 + * purpose with or without fee is hereby granted, provided that the above
712 + * copyright notice and this permission notice appear in all copies.
713 + *
714 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
715 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
716 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
717 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
718 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
719 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
720 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
721 + */
722 +
723 +#ifndef _BRCMU_WIFI_H_
724 +#define _BRCMU_WIFI_H_
725 +
726 +#include <linux/if_ether.h> /* for ETH_ALEN */
727 +#include <linux/ieee80211.h> /* for WLAN_PMKID_LEN */
728 +
729 +/*
730 + * A chanspec (u16) holds the channel number, band, bandwidth and control
731 + * sideband
732 + */
733 +
734 +/* channel defines */
735 +#define CH_UPPER_SB 0x01
736 +#define CH_LOWER_SB 0x02
737 +#define CH_EWA_VALID 0x04
738 +#define CH_30MHZ_APART 6
739 +#define CH_20MHZ_APART 4
740 +#define CH_10MHZ_APART 2
741 +#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
742 +#define CH_MIN_2G_CHANNEL 1
743 +#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
744 +#define CH_MIN_5G_CHANNEL 34
745 +
746 +/* bandstate array indices */
747 +#define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
748 +#define BAND_5G_INDEX 1 /* wlc->bandstate[x] index */
749 +
750 +/*
751 + * max # supported channels. The max channel no is 216, this is that + 1
752 + * rounded up to a multiple of NBBY (8). DO NOT MAKE it > 255: channels are
753 + * u8's all over
754 +*/
755 +#define MAXCHANNEL 224
756 +
757 +#define WL_CHANSPEC_CHAN_MASK 0x00ff
758 +#define WL_CHANSPEC_CHAN_SHIFT 0
759 +
760 +#define WL_CHANSPEC_CTL_SB_MASK 0x0300
761 +#define WL_CHANSPEC_CTL_SB_SHIFT 8
762 +#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
763 +#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
764 +#define WL_CHANSPEC_CTL_SB_NONE 0x0300
765 +
766 +#define WL_CHANSPEC_BW_MASK 0x0C00
767 +#define WL_CHANSPEC_BW_SHIFT 10
768 +#define WL_CHANSPEC_BW_10 0x0400
769 +#define WL_CHANSPEC_BW_20 0x0800
770 +#define WL_CHANSPEC_BW_40 0x0C00
771 +#define WL_CHANSPEC_BW_80 0x2000
772 +
773 +#define WL_CHANSPEC_BAND_MASK 0xf000
774 +#define WL_CHANSPEC_BAND_SHIFT 12
775 +#define WL_CHANSPEC_BAND_5G 0x1000
776 +#define WL_CHANSPEC_BAND_2G 0x2000
777 +#define INVCHANSPEC 255
778 +
779 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
780 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with country sett. */
781 +#define WL_CHAN_BAND_5G (1 << 2) /* 5GHz-band channel */
782 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
783 +#define WL_CHAN_INACTIVE (1 << 4) /* inactive due to radar */
784 +#define WL_CHAN_PASSIVE (1 << 5) /* channel in passive mode */
785 +#define WL_CHAN_RESTRICTED (1 << 6) /* restricted use channel */
786 +
787 +/* values for band specific 40MHz capabilities */
788 +#define WLC_N_BW_20ALL 0
789 +#define WLC_N_BW_40ALL 1
790 +#define WLC_N_BW_20IN2G_40IN5G 2
791 +
792 +#define WLC_BW_20MHZ_BIT BIT(0)
793 +#define WLC_BW_40MHZ_BIT BIT(1)
794 +#define WLC_BW_80MHZ_BIT BIT(2)
795 +#define WLC_BW_160MHZ_BIT BIT(3)
796 +
797 +/* Bandwidth capabilities */
798 +#define WLC_BW_CAP_20MHZ (WLC_BW_20MHZ_BIT)
799 +#define WLC_BW_CAP_40MHZ (WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
800 +#define WLC_BW_CAP_80MHZ (WLC_BW_80MHZ_BIT|WLC_BW_40MHZ_BIT| \
801 + WLC_BW_20MHZ_BIT)
802 +#define WLC_BW_CAP_160MHZ (WLC_BW_160MHZ_BIT|WLC_BW_80MHZ_BIT| \
803 + WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
804 +#define WLC_BW_CAP_UNRESTRICTED 0xFF
805 +
806 +/* band types */
807 +#define WLC_BAND_AUTO 0 /* auto-select */
808 +#define WLC_BAND_5G 1 /* 5 Ghz */
809 +#define WLC_BAND_2G 2 /* 2.4 Ghz */
810 +#define WLC_BAND_ALL 3 /* all bands */
811 +
812 +#define CHSPEC_CHANNEL(chspec) ((u8)((chspec) & WL_CHANSPEC_CHAN_MASK))
813 +#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
814 +
815 +#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
816 +#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
817 +
818 +#define CHSPEC_IS10(chspec) \
819 + (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
820 +
821 +#define CHSPEC_IS20(chspec) \
822 + (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
823 +
824 +#define CHSPEC_IS40(chspec) \
825 + (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
826 +
827 +#define CHSPEC_IS80(chspec) \
828 + (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_80)
829 +
830 +#define CHSPEC_IS5G(chspec) \
831 + (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
832 +
833 +#define CHSPEC_IS2G(chspec) \
834 + (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
835 +
836 +#define CHSPEC_SB_NONE(chspec) \
837 + (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
838 +
839 +#define CHSPEC_SB_UPPER(chspec) \
840 + (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
841 +
842 +#define CHSPEC_SB_LOWER(chspec) \
843 + (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
844 +
845 +#define CHSPEC_CTL_CHAN(chspec) \
846 + ((CHSPEC_SB_LOWER(chspec)) ? \
847 + (lower_20_sb(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
848 + (upper_20_sb(((chspec) & WL_CHANSPEC_CHAN_MASK))))
849 +
850 +#define CHSPEC2BAND(chspec) (CHSPEC_IS5G(chspec) ? BRCM_BAND_5G : BRCM_BAND_2G)
851 +
852 +#define CHANSPEC_STR_LEN 8
853 +
854 +static inline int lower_20_sb(int channel)
855 +{
856 + return channel > CH_10MHZ_APART ? (channel - CH_10MHZ_APART) : 0;
857 +}
858 +
859 +static inline int upper_20_sb(int channel)
860 +{
861 + return (channel < (MAXCHANNEL - CH_10MHZ_APART)) ?
862 + channel + CH_10MHZ_APART : 0;
863 +}
864 +
865 +static inline int chspec_bandunit(u16 chspec)
866 +{
867 + return CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX;
868 +}
869 +
870 +static inline u16 ch20mhz_chspec(int channel)
871 +{
872 + u16 rc = channel <= CH_MAX_2G_CHANNEL ?
873 + WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G;
874 +
875 + return (u16)((u16)channel | WL_CHANSPEC_BW_20 |
876 + WL_CHANSPEC_CTL_SB_NONE | rc);
877 +}
878 +
879 +static inline int next_20mhz_chan(int channel)
880 +{
881 + return channel < (MAXCHANNEL - CH_20MHZ_APART) ?
882 + channel + CH_20MHZ_APART : 0;
883 +}
884 +
885 +/* defined rate in 500kbps */
886 +#define BRCM_MAXRATE 108 /* in 500kbps units */
887 +#define BRCM_RATE_1M 2 /* in 500kbps units */
888 +#define BRCM_RATE_2M 4 /* in 500kbps units */
889 +#define BRCM_RATE_5M5 11 /* in 500kbps units */
890 +#define BRCM_RATE_11M 22 /* in 500kbps units */
891 +#define BRCM_RATE_6M 12 /* in 500kbps units */
892 +#define BRCM_RATE_9M 18 /* in 500kbps units */
893 +#define BRCM_RATE_12M 24 /* in 500kbps units */
894 +#define BRCM_RATE_18M 36 /* in 500kbps units */
895 +#define BRCM_RATE_24M 48 /* in 500kbps units */
896 +#define BRCM_RATE_36M 72 /* in 500kbps units */
897 +#define BRCM_RATE_48M 96 /* in 500kbps units */
898 +#define BRCM_RATE_54M 108 /* in 500kbps units */
899 +
900 +#define BRCM_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
901 +
902 +#define MCSSET_LEN 16
903 +
904 +static inline bool ac_bitmap_tst(u8 bitmap, int prec)
905 +{
906 + return (bitmap & (1 << (prec))) != 0;
907 +}
908 +
909 +/* Enumerate crypto algorithms */
910 +#define CRYPTO_ALGO_OFF 0
911 +#define CRYPTO_ALGO_WEP1 1
912 +#define CRYPTO_ALGO_TKIP 2
913 +#define CRYPTO_ALGO_WEP128 3
914 +#define CRYPTO_ALGO_AES_CCM 4
915 +#define CRYPTO_ALGO_AES_RESERVED1 5
916 +#define CRYPTO_ALGO_AES_RESERVED2 6
917 +#define CRYPTO_ALGO_NALG 7
918 +
919 +/* wireless security bitvec */
920 +
921 +#define WEP_ENABLED 0x0001
922 +#define TKIP_ENABLED 0x0002
923 +#define AES_ENABLED 0x0004
924 +#define WSEC_SWFLAG 0x0008
925 +/* to go into transition mode without setting wep */
926 +#define SES_OW_ENABLED 0x0040
927 +/* MFP */
928 +#define MFP_CAPABLE 0x0200
929 +#define MFP_REQUIRED 0x0400
930 +
931 +/* WPA authentication mode bitvec */
932 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
933 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
934 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
935 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
936 +#define WPA_AUTH_RESERVED1 0x0008
937 +#define WPA_AUTH_RESERVED2 0x0010
938 +
939 +#define WPA2_AUTH_RESERVED1 0x0020
940 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
941 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
942 +#define WPA2_AUTH_RESERVED3 0x0200
943 +#define WPA2_AUTH_RESERVED4 0x0400
944 +#define WPA2_AUTH_RESERVED5 0x0800
945 +#define WPA2_AUTH_1X_SHA256 0x1000 /* 1X with SHA256 key derivation */
946 +#define WPA2_AUTH_PSK_SHA256 0x8000 /* PSK with SHA256 key derivation */
947 +
948 +#define DOT11_DEFAULT_RTS_LEN 2347
949 +#define DOT11_DEFAULT_FRAG_LEN 2346
950 +
951 +#define DOT11_ICV_AES_LEN 8
952 +#define DOT11_QOS_LEN 2
953 +#define DOT11_IV_MAX_LEN 8
954 +#define DOT11_A4_HDR_LEN 30
955 +
956 +#define HT_CAP_RX_STBC_NO 0x0
957 +#define HT_CAP_RX_STBC_ONE_STREAM 0x1
958 +
959 +#endif /* _BRCMU_WIFI_H_ */
960 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/chipcommon.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/chipcommon.h
961 new file mode 100644
962 index 0000000..e1fd499
963 --- /dev/null
964 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/chipcommon.h
965 @@ -0,0 +1,303 @@
966 +/*
967 + * Copyright (c) 2010 Broadcom Corporation
968 + *
969 + * Permission to use, copy, modify, and/or distribute this software for any
970 + * purpose with or without fee is hereby granted, provided that the above
971 + * copyright notice and this permission notice appear in all copies.
972 + *
973 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
974 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
975 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
976 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
977 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
978 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
979 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
980 + */
981 +
982 +#ifndef _SBCHIPC_H
983 +#define _SBCHIPC_H
984 +
985 +#include "defs.h" /* for PAD macro */
986 +
987 +#define CHIPCREGOFFS(field) offsetof(struct chipcregs, field)
988 +
989 +struct chipcregs {
990 + u32 chipid; /* 0x0 */
991 + u32 capabilities;
992 + u32 corecontrol; /* corerev >= 1 */
993 + u32 bist;
994 +
995 + /* OTP */
996 + u32 otpstatus; /* 0x10, corerev >= 10 */
997 + u32 otpcontrol;
998 + u32 otpprog;
999 + u32 otplayout; /* corerev >= 23 */
1000 +
1001 + /* Interrupt control */
1002 + u32 intstatus; /* 0x20 */
1003 + u32 intmask;
1004 +
1005 + /* Chip specific regs */
1006 + u32 chipcontrol; /* 0x28, rev >= 11 */
1007 + u32 chipstatus; /* 0x2c, rev >= 11 */
1008 +
1009 + /* Jtag Master */
1010 + u32 jtagcmd; /* 0x30, rev >= 10 */
1011 + u32 jtagir;
1012 + u32 jtagdr;
1013 + u32 jtagctrl;
1014 +
1015 + /* serial flash interface registers */
1016 + u32 flashcontrol; /* 0x40 */
1017 + u32 flashaddress;
1018 + u32 flashdata;
1019 + u32 PAD[1];
1020 +
1021 + /* Silicon backplane configuration broadcast control */
1022 + u32 broadcastaddress; /* 0x50 */
1023 + u32 broadcastdata;
1024 +
1025 + /* gpio - cleared only by power-on-reset */
1026 + u32 gpiopullup; /* 0x58, corerev >= 20 */
1027 + u32 gpiopulldown; /* 0x5c, corerev >= 20 */
1028 + u32 gpioin; /* 0x60 */
1029 + u32 gpioout; /* 0x64 */
1030 + u32 gpioouten; /* 0x68 */
1031 + u32 gpiocontrol; /* 0x6C */
1032 + u32 gpiointpolarity; /* 0x70 */
1033 + u32 gpiointmask; /* 0x74 */
1034 +
1035 + /* GPIO events corerev >= 11 */
1036 + u32 gpioevent;
1037 + u32 gpioeventintmask;
1038 +
1039 + /* Watchdog timer */
1040 + u32 watchdog; /* 0x80 */
1041 +
1042 + /* GPIO events corerev >= 11 */
1043 + u32 gpioeventintpolarity;
1044 +
1045 + /* GPIO based LED powersave registers corerev >= 16 */
1046 + u32 gpiotimerval; /* 0x88 */
1047 + u32 gpiotimeroutmask;
1048 +
1049 + /* clock control */
1050 + u32 clockcontrol_n; /* 0x90 */
1051 + u32 clockcontrol_sb; /* aka m0 */
1052 + u32 clockcontrol_pci; /* aka m1 */
1053 + u32 clockcontrol_m2; /* mii/uart/mipsref */
1054 + u32 clockcontrol_m3; /* cpu */
1055 + u32 clkdiv; /* corerev >= 3 */
1056 + u32 gpiodebugsel; /* corerev >= 28 */
1057 + u32 capabilities_ext; /* 0xac */
1058 +
1059 + /* pll delay registers (corerev >= 4) */
1060 + u32 pll_on_delay; /* 0xb0 */
1061 + u32 fref_sel_delay;
1062 + u32 slow_clk_ctl; /* 5 < corerev < 10 */
1063 + u32 PAD;
1064 +
1065 + /* Instaclock registers (corerev >= 10) */
1066 + u32 system_clk_ctl; /* 0xc0 */
1067 + u32 clkstatestretch;
1068 + u32 PAD[2];
1069 +
1070 + /* Indirect backplane access (corerev >= 22) */
1071 + u32 bp_addrlow; /* 0xd0 */
1072 + u32 bp_addrhigh;
1073 + u32 bp_data;
1074 + u32 PAD;
1075 + u32 bp_indaccess;
1076 + u32 PAD[3];
1077 +
1078 + /* More clock dividers (corerev >= 32) */
1079 + u32 clkdiv2;
1080 + u32 PAD[2];
1081 +
1082 + /* In AI chips, pointer to erom */
1083 + u32 eromptr; /* 0xfc */
1084 +
1085 + /* ExtBus control registers (corerev >= 3) */
1086 + u32 pcmcia_config; /* 0x100 */
1087 + u32 pcmcia_memwait;
1088 + u32 pcmcia_attrwait;
1089 + u32 pcmcia_iowait;
1090 + u32 ide_config;
1091 + u32 ide_memwait;
1092 + u32 ide_attrwait;
1093 + u32 ide_iowait;
1094 + u32 prog_config;
1095 + u32 prog_waitcount;
1096 + u32 flash_config;
1097 + u32 flash_waitcount;
1098 + u32 SECI_config; /* 0x130 SECI configuration */
1099 + u32 PAD[3];
1100 +
1101 + /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
1102 + u32 eci_output; /* 0x140 */
1103 + u32 eci_control;
1104 + u32 eci_inputlo;
1105 + u32 eci_inputmi;
1106 + u32 eci_inputhi;
1107 + u32 eci_inputintpolaritylo;
1108 + u32 eci_inputintpolaritymi;
1109 + u32 eci_inputintpolarityhi;
1110 + u32 eci_intmasklo;
1111 + u32 eci_intmaskmi;
1112 + u32 eci_intmaskhi;
1113 + u32 eci_eventlo;
1114 + u32 eci_eventmi;
1115 + u32 eci_eventhi;
1116 + u32 eci_eventmasklo;
1117 + u32 eci_eventmaskmi;
1118 + u32 eci_eventmaskhi;
1119 + u32 PAD[3];
1120 +
1121 + /* SROM interface (corerev >= 32) */
1122 + u32 sromcontrol; /* 0x190 */
1123 + u32 sromaddress;
1124 + u32 sromdata;
1125 + u32 PAD[17];
1126 +
1127 + /* Clock control and hardware workarounds (corerev >= 20) */
1128 + u32 clk_ctl_st; /* 0x1e0 */
1129 + u32 hw_war;
1130 + u32 PAD[70];
1131 +
1132 + /* UARTs */
1133 + u8 uart0data; /* 0x300 */
1134 + u8 uart0imr;
1135 + u8 uart0fcr;
1136 + u8 uart0lcr;
1137 + u8 uart0mcr;
1138 + u8 uart0lsr;
1139 + u8 uart0msr;
1140 + u8 uart0scratch;
1141 + u8 PAD[248]; /* corerev >= 1 */
1142 +
1143 + u8 uart1data; /* 0x400 */
1144 + u8 uart1imr;
1145 + u8 uart1fcr;
1146 + u8 uart1lcr;
1147 + u8 uart1mcr;
1148 + u8 uart1lsr;
1149 + u8 uart1msr;
1150 + u8 uart1scratch;
1151 + u32 PAD[62];
1152 +
1153 + /* save/restore, corerev >= 48 */
1154 + u32 sr_capability; /* 0x500 */
1155 + u32 sr_control0; /* 0x504 */
1156 + u32 sr_control1; /* 0x508 */
1157 + u32 gpio_control; /* 0x50C */
1158 + u32 PAD[60];
1159 +
1160 + /* PMU registers (corerev >= 20) */
1161 + u32 pmucontrol; /* 0x600 */
1162 + u32 pmucapabilities;
1163 + u32 pmustatus;
1164 + u32 res_state;
1165 + u32 res_pending;
1166 + u32 pmutimer;
1167 + u32 min_res_mask;
1168 + u32 max_res_mask;
1169 + u32 res_table_sel;
1170 + u32 res_dep_mask;
1171 + u32 res_updn_timer;
1172 + u32 res_timer;
1173 + u32 clkstretch;
1174 + u32 pmuwatchdog;
1175 + u32 gpiosel; /* 0x638, rev >= 1 */
1176 + u32 gpioenable; /* 0x63c, rev >= 1 */
1177 + u32 res_req_timer_sel;
1178 + u32 res_req_timer;
1179 + u32 res_req_mask;
1180 + u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */
1181 + u32 chipcontrol_addr; /* 0x650 */
1182 + u32 chipcontrol_data; /* 0x654 */
1183 + u32 regcontrol_addr;
1184 + u32 regcontrol_data;
1185 + u32 pllcontrol_addr;
1186 + u32 pllcontrol_data;
1187 + u32 pmustrapopt; /* 0x668, corerev >= 28 */
1188 + u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
1189 + u32 retention_ctl; /* 0x670, pmurev >= 15 */
1190 + u32 PAD[3];
1191 + u32 retention_grpidx; /* 0x680 */
1192 + u32 retention_grpctl; /* 0x684 */
1193 + u32 PAD[94];
1194 + u16 sromotp[768];
1195 +};
1196 +
1197 +/* chipid */
1198 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
1199 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
1200 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
1201 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
1202 +#define CID_PKG_SHIFT 20 /* Package Option shift */
1203 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
1204 +#define CID_CC_SHIFT 24
1205 +#define CID_TYPE_MASK 0xf0000000 /* Chip Type */
1206 +#define CID_TYPE_SHIFT 28
1207 +
1208 +/* capabilities */
1209 +#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
1210 +#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
1211 +#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
1212 +/* UARTs are driven by internal divided clock */
1213 +#define CC_CAP_UINTCLK 0x00000008
1214 +#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
1215 +#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
1216 +#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
1217 +#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
1218 +#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
1219 +#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
1220 +#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
1221 +#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
1222 +#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
1223 +#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
1224 +#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
1225 +#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
1226 +#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
1227 +#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
1228 +#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
1229 +#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
1230 +/* Nand flash present, rev >= 35 */
1231 +#define CC_CAP_NFLASH 0x80000000
1232 +
1233 +#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
1234 +/* GSIO (spi/i2c) present, rev >= 37 */
1235 +#define CC_CAP2_GSIO 0x00000002
1236 +
1237 +/* pmucapabilities */
1238 +#define PCAP_REV_MASK 0x000000ff
1239 +#define PCAP_RC_MASK 0x00001f00
1240 +#define PCAP_RC_SHIFT 8
1241 +#define PCAP_TC_MASK 0x0001e000
1242 +#define PCAP_TC_SHIFT 13
1243 +#define PCAP_PC_MASK 0x001e0000
1244 +#define PCAP_PC_SHIFT 17
1245 +#define PCAP_VC_MASK 0x01e00000
1246 +#define PCAP_VC_SHIFT 21
1247 +#define PCAP_CC_MASK 0x1e000000
1248 +#define PCAP_CC_SHIFT 25
1249 +#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
1250 +#define PCAP5_PC_SHIFT 17
1251 +#define PCAP5_VC_MASK 0x07c00000
1252 +#define PCAP5_VC_SHIFT 22
1253 +#define PCAP5_CC_MASK 0xf8000000
1254 +#define PCAP5_CC_SHIFT 27
1255 +/* pmucapabilites_ext PMU rev >= 15 */
1256 +#define PCAPEXT_SR_SUPPORTED_MASK (1 << 1)
1257 +/* retention_ctl PMU rev >= 15 */
1258 +#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26)
1259 +#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
1260 +
1261 +
1262 +/*
1263 +* Maximum delay for the PMU state transition in us.
1264 +* This is an upper bound intended for spinwaits etc.
1265 +*/
1266 +#define PMU_MAX_TRANSITION_DLY 15000
1267 +
1268 +#endif /* _SBCHIPC_H */
1269 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/defs.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/defs.h
1270 new file mode 100644
1271 index 0000000..8d1e85e
1272 --- /dev/null
1273 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/defs.h
1274 @@ -0,0 +1,105 @@
1275 +/*
1276 + * Copyright (c) 2010 Broadcom Corporation
1277 + *
1278 + * Permission to use, copy, modify, and/or distribute this software for any
1279 + * purpose with or without fee is hereby granted, provided that the above
1280 + * copyright notice and this permission notice appear in all copies.
1281 + *
1282 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1283 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1284 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
1285 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1286 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
1287 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
1288 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1289 + */
1290 +
1291 +#ifndef _BRCM_DEFS_H_
1292 +#define _BRCM_DEFS_H_
1293 +
1294 +#include <linux/types.h>
1295 +
1296 +#define SI_BUS 0
1297 +#define PCI_BUS 1
1298 +#define PCMCIA_BUS 2
1299 +#define SDIO_BUS 3
1300 +#define JTAG_BUS 4
1301 +#define USB_BUS 5
1302 +#define SPI_BUS 6
1303 +
1304 +#define OFF 0
1305 +#define ON 1 /* ON = 1 */
1306 +#define AUTO (-1) /* Auto = -1 */
1307 +
1308 +/*
1309 + * Priority definitions according 802.1D
1310 + */
1311 +#define PRIO_8021D_NONE 2
1312 +#define PRIO_8021D_BK 1
1313 +#define PRIO_8021D_BE 0
1314 +#define PRIO_8021D_EE 3
1315 +#define PRIO_8021D_CL 4
1316 +#define PRIO_8021D_VI 5
1317 +#define PRIO_8021D_VO 6
1318 +#define PRIO_8021D_NC 7
1319 +
1320 +#define MAXPRIO 7
1321 +#define NUMPRIO (MAXPRIO + 1)
1322 +
1323 +#define WL_NUMRATES 16 /* max # of rates in a rateset */
1324 +
1325 +#define BRCM_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */
1326 +
1327 +#define BRCM_SET_CHANNEL 30
1328 +#define BRCM_SET_SRL 32
1329 +#define BRCM_SET_LRL 34
1330 +#define BRCM_SET_BCNPRD 76
1331 +
1332 +#define BRCM_GET_CURR_RATESET 114 /* current rateset */
1333 +#define BRCM_GET_PHYLIST 180
1334 +
1335 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
1336 +
1337 +#define WL_RADIO_SW_DISABLE (1<<0)
1338 +#define WL_RADIO_HW_DISABLE (1<<1)
1339 +/* some countries don't support any channel */
1340 +#define WL_RADIO_COUNTRY_DISABLE (1<<3)
1341 +
1342 +/* Override bit for SET_TXPWR. if set, ignore other level limits */
1343 +#define WL_TXPWR_OVERRIDE (1U<<31)
1344 +
1345 +/* band types */
1346 +#define BRCM_BAND_AUTO 0 /* auto-select */
1347 +#define BRCM_BAND_5G 1 /* 5 Ghz */
1348 +#define BRCM_BAND_2G 2 /* 2.4 Ghz */
1349 +#define BRCM_BAND_ALL 3 /* all bands */
1350 +
1351 +/* Debug levels */
1352 +#define BRCM_DL_INFO 0x00000001
1353 +#define BRCM_DL_MAC80211 0x00000002
1354 +#define BRCM_DL_RX 0x00000004
1355 +#define BRCM_DL_TX 0x00000008
1356 +#define BRCM_DL_INT 0x00000010
1357 +#define BRCM_DL_DMA 0x00000020
1358 +#define BRCM_DL_HT 0x00000040
1359 +
1360 +/* Values for PM */
1361 +#define PM_OFF 0
1362 +#define PM_MAX 1
1363 +#define PM_FAST 2
1364 +
1365 +/*
1366 + * Sonics Configuration Space Registers.
1367 + */
1368 +
1369 +/* core sbconfig regs are top 256bytes of regs */
1370 +#define SBCONFIGOFF 0xf00
1371 +
1372 +/* cpp contortions to concatenate w/arg prescan */
1373 +#ifndef PAD
1374 +#define _PADLINE(line) pad ## line
1375 +#define _XSTR(line) _PADLINE(line)
1376 +#define PAD _XSTR(__LINE__)
1377 +#endif
1378 +
1379 +#endif /* _BRCM_DEFS_H_ */
1380 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/soc.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/soc.h
1381 new file mode 100644
1382 index 0000000..123cfa8
1383 --- /dev/null
1384 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/include/soc.h
1385 @@ -0,0 +1,36 @@
1386 +/*
1387 + * Copyright (c) 2010 Broadcom Corporation
1388 + *
1389 + * Permission to use, copy, modify, and/or distribute this software for any
1390 + * purpose with or without fee is hereby granted, provided that the above
1391 + * copyright notice and this permission notice appear in all copies.
1392 + *
1393 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1394 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1395 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
1396 + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1397 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
1398 + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
1399 + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1400 + */
1401 +
1402 +#ifndef _BRCM_SOC_H
1403 +#define _BRCM_SOC_H
1404 +
1405 +#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
1406 +
1407 +/* Common core control flags */
1408 +#define SICF_BIST_EN 0x8000
1409 +#define SICF_PME_EN 0x4000
1410 +#define SICF_CORE_BITS 0x3ffc
1411 +#define SICF_FGC 0x0002
1412 +#define SICF_CLOCK_EN 0x0001
1413 +
1414 +/* Common core status flags */
1415 +#define SISF_BIST_DONE 0x8000
1416 +#define SISF_BIST_ERROR 0x4000
1417 +#define SISF_GATED_CLK 0x2000
1418 +#define SISF_DMA64 0x1000
1419 +#define SISF_CORE_BITS 0x0fff
1420 +
1421 +#endif /* _BRCM_SOC_H */
1422 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_ioctls.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_ioctls.h
1423 new file mode 100644
1424 index 0000000..587b45d
1425 --- /dev/null
1426 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_ioctls.h
1427 @@ -0,0 +1,15 @@
1428 +#ifndef NEXMON_IOCTLS_H
1429 +#define NEXMON_IOCTLS_H
1430 +
1431 +/* see include/dhdioctl.h in bcmdhd driver */
1432 +typedef struct nex_ioctl {
1433 + uint cmd; /* common ioctl definition */
1434 + void *buf; /* pointer to user buffer */
1435 + uint len; /* length of user buffer */
1436 + bool set; /* get or set request (optional) */
1437 + uint used; /* bytes read or written (optional) */
1438 + uint needed; /* bytes needed (optional) */
1439 + uint driver; /* to identify target driver */
1440 +} nex_ioctl_t;
1441 +
1442 +#endif /* NEXMON_IOCTLS_H */
1443 diff --git a/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_procfs.h b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_procfs.h
1444 new file mode 100644
1445 index 0000000..1389bff
1446 --- /dev/null
1447 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/nexmon_procfs.h
1448 @@ -0,0 +1,18 @@
1449 +#ifndef NEXMON_PROCFS_H
1450 +#define NEXMON_PROCFS_H
1451 +
1452 +#include <linux/kernel.h>
1453 +#include <linux/proc_fs.h>
1454 +#include <linux/seq_file.h>
1455 +
1456 +extern int procfs_dump_open(struct inode *inode, struct file *file);
1457 +extern ssize_t procfs_dump_read(struct file *file, char *buffer, size_t len, loff_t * off);
1458 +
1459 +static const struct file_operations
1460 +rom_proc_dump_fops = {
1461 + .owner = THIS_MODULE,
1462 + .open = procfs_dump_open,
1463 + .read = procfs_dump_read,
1464 +};
1465 +
1466 +#endif /* NEXMON_PROCFS_H */
1467 diff --git a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/sdio.c
1468 index d138260..77a3c41 100644
1469 --- a/data/linux-rpi-4.10.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
1470 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/sdio.c
1471 @@ -44,6 +44,8 @@
1472 #include "firmware.h"
1473 #include "core.h"
1474 #include "common.h"
1475 +/* NEXMON */
1476 +#include "nexmon_procfs.h"
1477  
1478 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
1479 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
1480 @@ -2847,6 +2849,13 @@ break2:
1481 }
1482 #endif /* DEBUG */
1483  
1484 +/* NEXMON */
1485 +#define MY_ROM_BUFFER_MAX 0x1fffff
1486 +int my_rom_buffer_len = 0;
1487 +u8 my_rom_buffer[0x1fffff];
1488 +struct brcmf_sdio *my_sdio = NULL;
1489 +struct brcmf_bus *my_bus = NULL;
1490 +
1491 static int
1492 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
1493 {
1494 @@ -3248,6 +3257,8 @@ static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
1495 int err;
1496  
1497 brcmf_dbg(TRACE, "Enter\n");
1498 + /*NEXMON*/
1499 + my_sdio = bus;
1500  
1501 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
1502 (u8 *)fw->data, fw->size);
1503 @@ -3404,6 +3415,9 @@ static int brcmf_sdio_bus_preinit(struct device *dev)
1504 u32 value;
1505 int err;
1506  
1507 + /* NEXMON */
1508 + my_bus = bus_if;
1509 +
1510 /* the commands below use the terms tx and rx from
1511 * a device perspective, ie. bus:txglom affects the
1512 * bus transfers from device to host.
1513 @@ -4305,3 +4319,62 @@ int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
1514 return ret;
1515 }
1516  
1517 +/* NEXMON */
1518 +int
1519 +write_ram_to_buffer(void) {
1520 + //Console start and end, size: 0x400
1521 + u32 start_addr = 0x6dab4;
1522 + u32 end_addr = 0x6deb4;
1523 +
1524 + u32 address = start_addr;
1525 + u32 chunk_sz = 0x100;
1526 + u8 data[0x100];
1527 +
1528 + brcmf_err("NEXMON, enter\n");
1529 +
1530 + my_sdio->alp_only = true;
1531 + //Reset buffer
1532 + my_rom_buffer[0] = 0;
1533 + my_rom_buffer_len = 0;
1534 +
1535 + sdio_claim_host(my_sdio->sdiodev->func[1]);
1536 + brcmf_sdio_bus_sleep(my_sdio, false, false);
1537 + brcmf_sdio_clkctl(my_sdio, CLK_AVAIL, false);
1538 +
1539 + while(address >= start_addr && address < end_addr) {
1540 + brcmf_err("NEXMON rom loop, current address: 0x%x, my_rom_buffer_len: %d\n", address, my_rom_buffer_len);
1541 +
1542 + brcmf_sdiod_ramrw(my_sdio->sdiodev, false, address, data, chunk_sz);
1543 +
1544 + memcpy(&(my_rom_buffer[my_rom_buffer_len]), data, (size_t) chunk_sz);
1545 +
1546 + my_rom_buffer_len += chunk_sz;
1547 + address += chunk_sz;
1548 +
1549 + }
1550 +
1551 + print_hex_dump_bytes("", DUMP_PREFIX_NONE, my_rom_buffer, 0x100);
1552 +
1553 + my_sdio->alp_only = false;
1554 + sdio_release_host(my_sdio->sdiodev->func[1]);
1555 +
1556 + return 0;
1557 +
1558 +}
1559 +
1560 +int
1561 +procfs_dump_open(struct inode *inode, struct file *file) {
1562 + brcmf_err("NEXMON, enter\n");
1563 + if(my_bus != NULL) {
1564 + write_ram_to_buffer();
1565 + } else {
1566 + brcmf_err("NEXMON error, no my_sdio_bus = NULL!\n");
1567 + }
1568 + return 0;
1569 +}
1570 +
1571 +ssize_t
1572 +procfs_dump_read(struct file *filp, char *buffer, size_t length, loff_t *offset) {
1573 + return simple_read_from_buffer(buffer, length, offset, my_rom_buffer, my_rom_buffer_len);
1574 +}
1575 +
1576 diff --git a/data/linux-rpi-4.9.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/cfg80211.c
1577 index e2a459f..64131ac 100644
1578 --- a/data/linux-rpi-4.9.y/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
1579 +++ b/data/nexmon/patches/bcm43438/7_45_41_26/nexmon/brcmfmac/cfg80211.c
1580 @@ -658,6 +658,24 @@ static bool brcmf_is_ibssmode(struct brcmf_cfg80211_vif *vif)
1581 return vif->wdev.iftype == NL80211_IFTYPE_ADHOC;
1582 }
1583  
1584 +/* NEXMON */
1585 +static s32
1586 +brcmf_cfg80211_nexmon_set_channel(struct wiphy *wiphy,struct cfg80211_chan_def *chandef) {
1587 + struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
1588 + struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
1589 + s32 err = 0;
1590 + u16 chanspec;
1591 +
1592 + //brcmf_err("DEBUG NexMon: brcmf_cfg80211_nexmon_set_channel() called!\n");
1593 + chanspec = chandef_to_chanspec(&cfg->d11inf, chandef);
1594 + err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
1595 + if (err < 0) {
1596 + brcmf_err("Set Channel failed: chspec=%d, %d\n",
1597 + chanspec, err);
1598 + }
1599 + return 0;
1600 +}
1601 +
1602 static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
1603 const char *name,
1604 unsigned char name_assign_type,
1605 @@ -917,6 +935,9 @@ brcmf_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
1606 }
1607 switch (type) {
1608 case NL80211_IFTYPE_MONITOR:
1609 + /* NEXMON */
1610 + infra = 1;
1611 + break;
1612 case NL80211_IFTYPE_WDS:
1613 brcmf_err("type (%d) : currently we do not support this type\n",
1614 type);
1615 @@ -5232,6 +5253,7 @@ static struct cfg80211_ops brcmf_cfg80211_ops = {
1616 .crit_proto_start = brcmf_cfg80211_crit_proto_start,
1617 .crit_proto_stop = brcmf_cfg80211_crit_proto_stop,
1618 .tdls_oper = brcmf_cfg80211_tdls_oper,
1619 + .set_monitor_channel = brcmf_cfg80211_nexmon_set_channel,
1620 };
1621  
1622 struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,