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1 office 1 /***************************************************************************
2 * *
3 * ########### ########### ########## ########## *
4 * ############ ############ ############ ############ *
5 * ## ## ## ## ## ## ## *
6 * ## ## ## ## ## ## ## *
7 * ########### #### ###### ## ## ## ## ###### *
8 * ########### #### # ## ## ## ## # # *
9 * ## ## ###### ## ## ## ## # # *
10 * ## ## # ## ## ## ## # # *
11 * ############ ##### ###### ## ## ## ##### ###### *
12 * ########### ########### ## ## ## ########## *
13 * *
14 * S E C U R E M O B I L E N E T W O R K I N G *
15 * *
16 * This file is part of NexMon. *
17 * *
18 * Copyright (c) 2016 NexMon Team *
19 * *
20 * NexMon is free software: you can redistribute it and/or modify *
21 * it under the terms of the GNU General Public License as published by *
22 * the Free Software Foundation, either version 3 of the License, or *
23 * (at your option) any later version. *
24 * *
25 * NexMon is distributed in the hope that it will be useful, *
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
28 * GNU General Public License for more details. *
29 * *
30 * You should have received a copy of the GNU General Public License *
31 * along with NexMon. If not, see <http://www.gnu.org/licenses/>. *
32 * *
33 **************************************************************************/
34  
35 #ifndef STRUCTS_COMMON_H
36 #define STRUCTS_COMMON_H
37  
38 #include <types.h>
39 #include <bcmcdc.h>
40  
41 /* used for PAPD cal */
42 typedef struct _acphy_txgains {
43 uint16 txlpf;
44 uint16 txgm;
45 uint16 pga;
46 uint16 pad;
47 uint16 ipa;
48 } acphy_txgains_t;
49  
50 /* htphy: tx gain settings */
51 typedef struct {
52 uint16 rad_gain; /* Radio gains */
53 uint16 rad_gain_mi; /* Radio gains [16:31] */
54 uint16 rad_gain_hi; /* Radio gains [32:47] */
55 uint16 dac_gain; /* DAC attenuation */
56 uint16 bbmult; /* BBmult */
57 } txgain_setting_t;
58  
59 typedef struct { /* wlc_phy_write_tx_gain_acphy */
60 uint8 txlpf; /* Radio gains */
61 uint8 ipa;
62 uint8 pad; /* Radio gains [16:31] */
63 uint8 pga;
64 uint8 txgm; /* Radio gains [32:47] */
65 uint8 unknown;
66 uint16 dac_gain; /* DAC attenuation */
67 uint16 bbmult; /* BBmult */
68 } ac_txgain_setting_t;
69  
70 struct ratesel_txparams {
71 uint32 rspec[4];
72 uint8 antselid[4];
73 uint8 num;
74 };
75  
76 /* Most of these structs are taken from the bcm4339 includes file and might currently be wrong */
77  
78 struct wlc_hw_info {
79 struct wlc_info *wlc; /* 0x00 */
80 int PAD; /* 0x04 */
81 int PAD; /* 0x08 */
82 int PAD; /* 0x0c */
83 int PAD; /* 0x10 */
84 struct dma_info *di[6]; /* 0x14 - only 4 bytes */
85 int PAD; // 0x2c
86 int PAD; // 0x30
87 int PAD; // 0x34
88 int PAD; // 0x38
89 int PAD; // 0x3c
90 int PAD; // 0x40
91 int PAD; // 0x44
92 int PAD; // 0x48
93 int PAD; // 0x4c
94 int PAD; // 0x50
95 int PAD; // 0x54
96 int PAD; // 0x58
97 int PAD; // 0x5c
98 int PAD; // 0x60
99 int PAD; // 0x64
100 int PAD; // 0x68
101 int PAD; // 0x6c
102 int PAD; // 0x70
103 char PAD; // 0x74
104 char PAD; // 0x75
105 char ucode_loaded; /* 0x76 */
106 char PAD; /* 0x77 */
107 int PAD; /* 0x78 */
108 int sih; /* 0x7c */
109 int vars; /* 0x80 */
110 int vars_size; /* 0x84 */
111 struct d11regs* regs; /* 0x88 */
112 int physhim; /* 0x8c */
113 int phy_sh; /* 0x90 */
114 struct wlc_hwband *band; /* 0x94 */
115 int PAD; // 0x98
116 int PAD; // 0x9c
117 int PAD; // 0xa0
118 int PAD; // 0xa4
119 int PAD; // 0xa8
120 char up; // 0xac verified wl_dpc
121 char PAD;
122 char PAD;
123 char PAD;
124 int PAD; // 0xb0
125 int PAD; // 0xb4
126 int PAD; // 0xb8
127 int PAD; // 0xbc
128 int PAD; // 0xc0
129 int PAD; // 0xc4
130 int PAD; // 0xc8
131 int PAD; // 0xcc
132 int PAD; // 0xd0
133 int PAD; // 0xd4
134 int PAD; // 0xd8
135 int PAD; // 0xdc
136 int PAD; // 0xe0
137 int PAD; // 0xe4
138 int PAD; // 0xe8
139 int PAD; // 0xec
140 int PAD; // 0xf0
141 int PAD; // 0xf4
142 int PAD; // 0xf8
143 int PAD; // 0xfc
144 };
145  
146 struct wl_rxsts {
147 uint32 pkterror; /* error flags per pkt */
148 uint32 phytype; /* 802.11 A/B/G ... */
149 uint16 chanspec; /* channel spec */
150 uint16 datarate; /* rate in 500kbps (0 for HT frame) */
151 uint8 mcs; /* MCS for HT frame */
152 uint8 htflags; /* HT modulation flags */
153 uint32 antenna; /* antenna pkts received on */
154 uint32 pktlength; /* pkt length minus bcm phy hdr */
155 uint32 mactime; /* time stamp from mac, count per 1us */
156 uint32 sq; /* signal quality */
157 int32 signal; /* in dBm */
158 int32 noise; /* in dBm */
159 uint32 preamble; /* Unknown, short, long */
160 uint32 encoding; /* Unknown, CCK, PBCC, OFDM, HT */
161 uint32 nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
162 void *wlif; /* wl interface */
163 uint8 nss; /* Number of spatial streams for VHT frame */
164 uint8 coding;
165 uint16 aid; /* Partial AID for VHT frame */
166 uint8 gid; /* Group ID for VHT frame */
167 uint8 bw; /* Bandwidth for VHT frame */
168 uint16 vhtflags; /* VHT modulation flags */
169 uint8 bw_nonht; /* non-HT bw advertised in rts/cts */
170 uint8 PAD;
171 uint8 PAD;
172 uint8 PAD;
173 uint32 ampdu_counter; /* AMPDU counter for sniffer */
174 } __attribute__((packed));
175  
176 /* status per error RX pkt */
177 #define WL_RXS_CRC_ERROR 0x00000001 /* CRC Error in packet */
178 #define WL_RXS_RUNT_ERROR 0x00000002 /* Runt packet */
179 #define WL_RXS_ALIGN_ERROR 0x00000004 /* Misaligned packet */
180 #define WL_RXS_OVERSIZE_ERROR 0x00000008 /* packet bigger than RX_LENGTH (usually 1518) */
181 #define WL_RXS_WEP_ICV_ERROR 0x00000010 /* Integrity Check Value error */
182 #define WL_RXS_WEP_ENCRYPTED 0x00000020 /* Encrypted with WEP */
183 #define WL_RXS_PLCP_SHORT 0x00000040 /* Short PLCP error */
184 #define WL_RXS_DECRYPT_ERR 0x00000080 /* Decryption error */
185 #define WL_RXS_OTHER_ERR 0x80000000 /* Other errors */
186  
187 /* phy type */
188 #define WL_RXS_PHY_A 0x00000000 /* A phy type */
189 #define WL_RXS_PHY_B 0x00000001 /* B phy type */
190 #define WL_RXS_PHY_G 0x00000002 /* G phy type */
191 #define WL_RXS_PHY_N 0x00000004 /* N phy type */
192  
193 /* encoding */
194 #define WL_RXS_ENCODING_UNKNOWN 0x00000000
195 #define WL_RXS_ENCODING_DSSS_CCK 0x00000001 /* DSSS/CCK encoding (1, 2, 5.5, 11) */
196 #define WL_RXS_ENCODING_OFDM 0x00000002 /* OFDM encoding */
197 #define WL_RXS_ENCODING_HT 0x00000003 /* HT encoding */
198 #define WL_RXS_ENCODING_AC 0x00000004 /* HT encoding */
199  
200 /* preamble */
201 #define WL_RXS_UNUSED_STUB 0x0 /* stub to match with wlc_ethereal.h */
202 #define WL_RXS_PREAMBLE_SHORT 0x00000001 /* Short preamble */
203 #define WL_RXS_PREAMBLE_LONG 0x00000002 /* Long preamble */
204 #define WL_RXS_PREAMBLE_HT_MM 0x00000003 /* HT mixed mode preamble */
205 #define WL_RXS_PREAMBLE_HT_GF 0x00000004 /* HT green field preamble */
206  
207 /* htflags */
208 #define WL_RXS_HTF_40 0x01
209 #define WL_RXS_HTF_20L 0x02
210 #define WL_RXS_HTF_20U 0x04
211 #define WL_RXS_HTF_SGI 0x08
212 #define WL_RXS_HTF_STBC_MASK 0x30
213 #define WL_RXS_HTF_STBC_SHIFT 4
214 #define WL_RXS_HTF_LDPC 0x40
215  
216 #define WL_RXS_NFRM_AMPDU_FIRST 0x00000001 /* first MPDU in A-MPDU */
217 #define WL_RXS_NFRM_AMPDU_SUB 0x00000002 /* subsequent MPDU(s) in A-MPDU */
218 #define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
219 #define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
220  
221 struct osl_info {
222 unsigned int pktalloced;
223 int PAD[1];
224 void *callback_when_dropped;
225 unsigned int bustype;
226 } __attribute__((packed));
227  
228 typedef struct sk_buff {
229 int field0; /* 0x00 */
230 int field4; /* 0x04 */
231 void *data; /* 0x08 */
232 short len; /* 0x0C */
233 short fieldE; // 0x0E
234 int field10; // 0x10
235 unsigned short next; // 0x14
236 unsigned short prev; // 0x16
237 unsigned short prev2; // 0x18
238 unsigned short prev3; // 0x1A
239 int PAD; // 0x1C
240 char byte20; // 0x20
241 char PAD; // 0x21
242 char PAD; // 0x22
243 char byte23; // 0x23
244 int PAD; // 0x24
245 int PAD; // 0x28
246 int dword2C; // 0x2C
247 } __attribute__((packed)) sk_buff;
248  
249 #define HNDRTE_DEV_NAME_MAX 16
250  
251 typedef struct hndrte_dev {
252 char name[HNDRTE_DEV_NAME_MAX];
253 struct hndrte_devfuncs *funcs;
254 uint32 devid;
255 void *softc; /* Software context */
256 uint32 flags; /* RTEDEVFLAG_XXXX */
257 struct hndrte_dev *next;
258 struct hndrte_dev *chained;
259 void *pdev;
260 } hndrte_dev;
261  
262 struct hndrte_devfuncs {
263 void *(*probe)(struct hndrte_dev *dev, void *regs, uint bus,
264 uint16 device, uint coreid, uint unit);
265 int (*open)(struct hndrte_dev *dev);
266 int (*close)(struct hndrte_dev *dev);
267 int (*xmit)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb);
268 int (*recv)(struct hndrte_dev *src, struct hndrte_dev *dev, void *pkt);
269 int (*ioctl)(struct hndrte_dev *dev, uint32 cmd, void *buffer, int len,
270 int *used, int *needed, int set);
271 void (*txflowcontrol) (struct hndrte_dev *dev, bool state, int prio);
272 void (*poll)(struct hndrte_dev *dev);
273 int (*xmit_ctl)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb);
274 int (*xmit2)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb, int8 ch);
275 };
276  
277 struct tunables {
278 char gap[62];
279 short somebnd; // @ 0x38
280 short rxbnd; // @ 0x40
281 };
282  
283 struct wlc_hwband {
284 int bandtype; /* 0x00 */
285 int bandunit; /* 0x04 */
286 char mhfs; /* 0x05 */
287 char PAD[10]; /* 0x06 */
288 char bandhw_stf_ss_mode; /* 0x13 */
289 short CWmin; /* 0x14 */
290 short CWmax; /* 0x16 */
291 int core_flags; /* 0x18 */
292 short phytype; /* 0x1C */
293 short phyrev; /* 0x1E */
294 short radioid; /* 0x20 */
295 short radiorev; /* 0x22 */
296 struct phy_info *pi; /* 0x24 */
297 char abgphy_encore; /* 0x25 */
298 };
299  
300 /**
301 * Name might be inaccurate
302 */
303 struct device {
304 char name[16];
305 void *init_function;
306 int PAD;
307 void *some_device_info;
308 int PAD;
309 int PAD;
310 struct device *bound_device;
311 };
312  
313 /**
314 * Name might be inaccurate
315 */
316 struct wl_info {
317 int unit;
318 struct wlc_pub *pub;
319 struct wlc_info *wlc;
320 struct wlc_hw_info *wlc_hw;
321 struct hndrte_dev *dev; // 0x10
322 };
323  
324 /**
325 * Name might be inaccurate
326 */
327 struct sdiox_info {
328 int unit;
329 void *something;
330 void *sdio; // sdio_info struct
331 void *osh;
332 void *device_address;
333 } __attribute__((packed));
334  
335 struct shared_phy {
336 struct phy_info *phy_head; // 0x000 /* head of phy list */
337 uint unit; // 0x004 /* device instance number */
338 struct osl_info *osh; // 0x008 /* pointer to os handle */
339 void *sih; // 0x00c /* si handle (cookie for siutils calls) */
340 void *physhim; // 0x010 /* phy <-> wl shim layer for wlapi */
341 uint corerev; // 0x014 /* d11corerev, shadow of wlc_hw->corerev */
342 uint32 machwcap; // 0x018 /* mac hw capability */
343 bool up; // 0x01c /* main driver is up and running */
344 bool clk; // 0x01d /* main driver make the clk available */
345 uint8 PAD; // 0x01e
346 uint8 PAD; // 0x01f
347 uint32 PAD; // 0x020
348 uint32 PAD; // 0x024
349 uint32 PAD; // 0x028
350 uint32 PAD; // 0x02C
351 uint32 PAD; // 0x030
352 uint32 PAD; // 0x034
353 uint32 PAD; // 0x038
354 uint32 PAD; // 0x03C
355 uint32 PAD; // 0x040
356 uint32 PAD; // 0x044
357 uint32 PAD; // 0x048
358 uint32 PAD; // 0x04C
359 uint32 PAD; // 0x050
360 uint32 PAD; // 0x054
361 uint32 PAD; // 0x058
362 uint32 PAD; // 0x05C
363 uint32 PAD; // 0x060
364 uint32 PAD; // 0x064
365 uint32 PAD; // 0x068
366 uint32 PAD; // 0x06C
367 uint32 PAD; // 0x070
368 uint32 PAD; // 0x074
369 uint32 PAD; // 0x078
370 uint32 PAD; // 0x07C
371 uint32 PAD; // 0x080
372 uint32 PAD; // 0x084
373 uint32 PAD; // 0x088
374 uint32 PAD; // 0x08C
375 uint8 PAD; // 0x090
376 uint8 hw_phyrxchain; // 0x091
377 uint8 PAD; // 0x092
378 uint8 PAD; // 0x093
379 uint32 PAD; // 0x094
380 uint32 PAD; // 0x098
381 uint32 PAD; // 0x09C
382 } __attribute__((packed));
383  
384 struct phy_pub {
385 uint phy_type; /* PHY_TYPE_XX */
386 uint phy_rev; /* phy revision */
387 uint8 phy_corenum; /* number of cores */
388 uint16 radioid; /* radio id */
389 uint8 radiorev; /* radio revision */
390 uint8 radiover; /* radio version */
391 uint8 radiomajorrev; /* radio major revision */
392 uint8 radiominorrev; /* radio minor revision */
393 uint coreflags; /* sbtml core/phy specific flags */
394 uint ana_rev; /* analog core revision */
395 bool abgphy_encore; /* true if chipset is encore enabled */
396 };
397  
398 struct phy_info_acphy {
399 uint8 dac_mode; // 0x000
400 uint8 PAD; // 0x001
401 uint16 bb_mult_save[1]; // 0x002
402 uint8 bb_mult_save_valid; // 0x004
403 uint8 PAD; // 0x005
404 uint16 deaf_count; // 0x006
405 uint32 PAD; // 0x008
406 uint32 PAD; // 0x00C
407 uint32 PAD; // 0x010
408 uint32 PAD; // 0x014
409 uint32 PAD; // 0x018
410 uint32 PAD; // 0x01C
411 int PAD; // 0x020
412 int PAD; // 0x024
413 int PAD; // 0x028
414 int PAD; // 0x02c
415 int PAD; // 0x030
416 int PAD; // 0x034
417 int PAD; // 0x038
418 int PAD; // 0x03c
419 int PAD; // 0x040
420 int PAD; // 0x044
421 int PAD; // 0x048
422 int PAD; // 0x04c
423 int PAD; // 0x050
424 int PAD; // 0x054
425 int PAD; // 0x058
426 int PAD; // 0x05c
427 int PAD; // 0x060
428 int PAD; // 0x064
429 int PAD; // 0x068
430 int PAD; // 0x06c
431 int PAD; // 0x070
432 int PAD; // 0x074
433 int PAD; // 0x078
434 int PAD; // 0x07c
435 int PAD; // 0x080
436 int PAD; // 0x084
437 int PAD; // 0x088
438 int PAD; // 0x08c
439 int PAD; // 0x090
440 int PAD; // 0x094
441 int PAD; // 0x098
442 int PAD; // 0x09c
443 int PAD; // 0x0a0
444 int PAD; // 0x0a4
445 int PAD; // 0x0a8
446 int PAD; // 0x0ac
447 int PAD; // 0x0b0
448 int PAD; // 0x0b4
449 int PAD; // 0x0b8
450 int PAD; // 0x0bc
451 int PAD; // 0x0c0
452 int PAD; // 0x0c4
453 int PAD; // 0x0c8
454 int PAD; // 0x0cc
455 int PAD; // 0x0d0
456 int PAD; // 0x0d4
457 int PAD; // 0x0d8
458 int PAD; // 0x0dc
459 int PAD; // 0x0e0
460 int PAD; // 0x0e4
461 int PAD; // 0x0e8
462 int PAD; // 0x0ec
463 int PAD; // 0x0f0
464 int PAD; // 0x0f4
465 int PAD; // 0x0f8
466 int PAD; // 0x0fc
467 int PAD; // 0x100
468 int PAD; // 0x104
469 int PAD; // 0x108
470 int PAD; // 0x10c
471 uint32 pstart; // 0x110
472 uint32 pstop; // 0x114
473 uint32 pfirst; // 0x118
474 uint32 plast; // 0x11c
475 int PAD; // 0x120
476 int PAD; // 0x124
477 int PAD; // 0x128
478 int PAD; // 0x12c
479 int PAD; // 0x130
480 int PAD; // 0x134
481 int PAD; // 0x138
482 int PAD; // 0x13c
483 int PAD; // 0x140
484 int PAD; // 0x144
485 int PAD; // 0x148
486 int PAD; // 0x14c
487 int PAD; // 0x150
488 int PAD; // 0x154
489 int PAD; // 0x158
490 int PAD; // 0x15c
491 int PAD; // 0x160
492 int PAD; // 0x164
493 int PAD; // 0x168
494 int PAD; // 0x16c
495 int PAD; // 0x170
496 int PAD; // 0x174
497 int PAD; // 0x178
498 int PAD; // 0x17c
499 int PAD; // 0x180
500 int PAD; // 0x184
501 int PAD; // 0x188
502 int PAD; // 0x18c
503 int PAD; // 0x190
504 int PAD; // 0x194
505 int PAD; // 0x198
506 int PAD; // 0x19c
507 int PAD; // 0x1a0
508 int PAD; // 0x1a4
509 int PAD; // 0x1a8
510 int PAD; // 0x1ac
511 int PAD; // 0x1b0
512 int PAD; // 0x1b4
513 int PAD; // 0x1b8
514 int PAD; // 0x1bc
515 int PAD; // 0x1c0
516 int PAD; // 0x1c4
517 int PAD; // 0x1c8
518 int PAD; // 0x1cc
519 int PAD; // 0x1d0
520 int PAD; // 0x1d4
521 int PAD; // 0x1d8
522 int PAD; // 0x1dc
523 int PAD; // 0x1e0
524 int PAD; // 0x1e4
525 int PAD; // 0x1e8
526 int16 idle_tssi[1]; // 0x1ec
527 } __attribute__((packed));
528  
529 struct phy_info {
530 struct phy_pub pubpi_ro; // 0x000
531 struct shared_phy *sh; // 0x01c
532 void (*fn_init)(void *); // 0x020
533 void (*fn_calinit)(void *); // 0x024
534 void (*fn_chanset)(void *, uint16); // 0x028
535 void (*fn_txpwrrecalc)(void *); // 0x02c
536 int (*fn_longtrn)(void *, int); // 0x030
537 void (*fn_txiqccget)(void *, uint16 *, uint16 *); // 0x034
538 void (*fn_txiqccmimoget)(void *, uint16 *, uint16 *, uint16 *, uint16 *); // 0x038
539 void (*fn_txiqccset)(void *, uint16, uint16); // 0x03c
540 void (*fn_txiqccmimoset)(void *, uint16, uint16, uint16, uint16); // 0x040
541 uint16 (*fn_txloccget)(void *); // 0x044
542 void (*fn_txloccset)(void *pi, uint16 didq); // 0x048
543 int PAD; // 0x04c
544 int PAD; // 0x050
545 int PAD; // 0x054
546 int PAD; // 0x058
547 int PAD; // 0x05c
548 int PAD; // 0x060
549 int PAD; // 0x064
550 int PAD; // 0x068
551 int PAD; // 0x06c
552 int PAD; // 0x070
553 int PAD; // 0x074
554 int PAD; // 0x078
555 int PAD; // 0x07c
556 int PAD; // 0x080
557 int PAD; // 0x084
558 int PAD; // 0x088
559 int PAD; // 0x08c
560 int PAD; // 0x090
561 int PAD; // 0x094
562 int PAD; // 0x098
563 int PAD; // 0x09c
564 int PAD; // 0x0a0
565 int PAD; // 0x0a4
566 int PAD; // 0x0a8
567 int PAD; // 0x0ac
568 int PAD; // 0x0b0
569 int PAD; // 0x0b4
570 int PAD; // 0x0b8
571 // struct phy_info_acphy *pi_ac; // 0x0bc
572 int PAD; // 0x0bc
573 int PAD; // 0x0c0
574 // struct d11regs *regs; // 0x0c4
575 int PAD; // 0x0c4
576 int PAD; // 0x0c8
577 int PAD; // 0x0cc
578 // struct phy_pub pubpi; // 0x0d0
579 int PAD; // 0x0d0
580 int PAD; // 0x0d4
581 int PAD; // 0x0d8
582 int PAD; // 0x0dc
583 int PAD; // 0x0e0
584 int PAD; // 0x0e4
585 struct d11regs *regs; // 0x0e8
586 short PAD; // 0x0ec
587 short radio_chanspec; // 0x0ee
588 short PAD; // 0x0f0
589 short bw; // 0x0f2
590 int PAD; // 0x0f4
591 int PAD; // 0x0f8
592 int PAD; // 0x0fc
593 int PAD; // 0x100
594 int PAD; // 0x104
595 int PAD; // 0x108
596 int PAD; // 0x10c
597 int PAD; // 0x110
598 int PAD; // 0x114
599 int PAD; // 0x118
600 int PAD; // 0x11c
601 int PAD; // 0x120
602 } __attribute__((packed));
603  
604 struct wlcband {
605 int bandtype; /* 0x000 */
606 int bandunit; /* 0x004 */
607 short phytype; /* 0x008 */
608 short phyrev; /* 0x00A */
609 short radioid; /* 0x00C */
610 short radiorev; /* 0x00E */
611 struct phy_info *pi; /* 0x010 */
612 char abgphy_encore; /* 0x014 */
613 char gmode; /* 0x015 */
614 char PAD; /* 0x016 */
615 char PAD; /* 0x017 */
616 void *hwrs_scb; /* 0x018 */
617 int defrateset; /* 0x01C */
618 int rspec_override; /* 0x020 */
619 int mrspec_override; /* 0x024 */
620 char band_stf_ss_mode; /* 0x028 */
621 char band_stf_stbc_tx; /* 0x029 */
622 int hw_rateset; /* 0x030 */
623 char basic_rate; /* 0x034 */
624 } __attribute__((packed));
625  
626 /* per interface counters */
627 struct wlc_if_stats {
628 /* transmit stat counters */
629 uint32 txframe; /* tx data frames */
630 uint32 txbyte; /* tx data bytes */
631 uint32 txerror; /* tx data errors (derived: sum of others) */
632 uint32 txnobuf; /* tx out of buffer errors */
633 uint32 txrunt; /* tx runt frames */
634 uint32 txfail; /* tx failed frames */
635 uint32 rxframe; /* rx data frames */
636 uint32 rxbyte; /* rx data bytes */
637 uint32 rxerror; /* rx data errors (derived: sum of others) */
638 uint32 rxnobuf; /* rx out of buffer errors */
639 uint32 rxrunt; /* rx runt frames */
640 uint32 rxfragerr; /* rx fragment errors */
641 uint32 txretry; /* tx retry frames */
642 uint32 txretrie; /* tx multiple retry frames */
643 uint32 txfrmsnt; /* tx sent frames */
644 uint32 txmulti; /* tx mulitcast sent frames */
645 uint32 txfrag; /* tx fragments sent */
646 uint32 rxmulti; /* rx multicast frames */
647 };
648  
649 struct wl_if {
650 struct wlc_if *wlcif;
651 struct hndrte_dev *dev;
652 };
653  
654 struct wlc_if {
655 struct wlc_if *next;
656 uint8 type;
657 uint8 index;
658 uint8 flags;
659 struct wl_if *wlif;
660 void *qi;
661 union {
662 struct scb *scb;
663 struct wlc_bsscfg *bsscfg;
664 } u;
665 struct wlc_if_stats _cnt;
666 };
667  
668 struct wlc_info {
669 struct wlc_pub *pub; /* 0x000 */
670 struct osl_info *osh; /* 0x004 */
671 void *wl; /* 0x008 */
672 volatile struct d11regs *regs; /* 0x00C */
673 struct wlc_hw_info *hw; /* 0x010 */
674 int PAD; /* 0x014 */
675 int PAD; /* 0x018 */
676 void *core; /* 0x01C */
677 struct wlcband *band; /* 0x020 verified */
678 int PAD; /* 0x024 */
679 struct wlcband *bandstate[2]; /* 0x028 */
680 int PAD; /* 0x030 */
681 int PAD; /* 0x034 */
682 int PAD; /* 0x038 */
683 int PAD; /* 0x03C */
684 int PAD; /* 0x040 */
685 int PAD; /* 0x044 */
686 int PAD; /* 0x048 */
687 int PAD; /* 0x04C */
688 int PAD; /* 0x050 */
689 int PAD; /* 0x054 */
690 int PAD; /* 0x058 */
691 int PAD; /* 0x05C */
692 int PAD; /* 0x060 */
693 int PAD; /* 0x064 */
694 int PAD; /* 0x068 */
695 int PAD; /* 0x06C */
696 int PAD; /* 0x070 */
697 int PAD; /* 0x074 */
698 int PAD; /* 0x078 */
699 int PAD; /* 0x07C */
700 int PAD; /* 0x080 */
701 int PAD; /* 0x084 */
702 int PAD; /* 0x088 */
703 int PAD; /* 0x08C */
704 int PAD; /* 0x090 */
705 int PAD; /* 0x094 */
706 int PAD; /* 0x098 */
707 int PAD; /* 0x09C */
708 int PAD; /* 0x0A0 */
709 int PAD; /* 0x0A4 */
710 int PAD; /* 0x0A8 */
711 int PAD; /* 0x0AC */
712 int PAD; /* 0x0B0 */
713 int PAD; /* 0x0B4 */
714 int PAD; /* 0x0B8 */
715 int PAD; /* 0x0BC */
716 int PAD; /* 0x0C0 */
717 int PAD; /* 0x0C4 */
718 int PAD; /* 0x0C8 */
719 int PAD; /* 0x0CC */
720 int PAD; /* 0x0D0 */
721 int PAD; /* 0x0D4 */
722 int PAD; /* 0x0D8 */
723 int PAD; /* 0x0DC */
724 int PAD; /* 0x0E0 */
725 int PAD; /* 0x0E4 */
726 int PAD; /* 0x0E8 */
727 int PAD; /* 0x0EC */
728 int PAD; /* 0x0F0 */
729 int PAD; /* 0x0F4 */
730 int PAD; /* 0x0F8 */
731 int PAD; /* 0x0FC */
732 int PAD; /* 0x100 */
733 int PAD; /* 0x104 */
734 int PAD; /* 0x108 */
735 int PAD; /* 0x10C */
736 int PAD; /* 0x110 */
737 int PAD; /* 0x114 */
738 int PAD; /* 0x118 */
739 int PAD; /* 0x11C */
740 int PAD; /* 0x120 */
741 int PAD; /* 0x124 */
742 int PAD; /* 0x128 */
743 int PAD; /* 0x12C */
744 int PAD; /* 0x130 */
745 int PAD; /* 0x134 */
746 int PAD; /* 0x138 */
747 int PAD; /* 0x13C */
748 int PAD; /* 0x140 */
749 int PAD; /* 0x144 */
750 int PAD; /* 0x148 */
751 int PAD; /* 0x14C */
752 int PAD; /* 0x150 */
753 int PAD; /* 0x154 */
754 int PAD; /* 0x158 */
755 void *cmi; /* 0x15C */
756 int PAD; /* 0x160 */
757 int PAD; /* 0x164 */
758 void *scan; /* 0x168 */
759 int PAD; /* 0x16C */
760 int PAD; /* 0x170 */
761 int PAD; /* 0x174 */
762 int PAD; /* 0x178 */
763 int PAD; /* 0x17C */
764 int PAD; /* 0x180 */
765 int PAD; /* 0x184 */
766 int PAD; /* 0x188 */
767 int PAD; /* 0x18C */
768 int PAD; /* 0x190 */
769 int PAD; /* 0x194 */
770 int PAD; /* 0x198 */
771 int PAD; /* 0x19C */
772 int PAD; /* 0x1A0 */
773 int PAD; /* 0x1A4 */
774 int PAD; /* 0x1A8 */
775 int PAD; /* 0x1AC */
776 int PAD; /* 0x1B0 */
777 int PAD; /* 0x1B4 */
778 int PAD; /* 0x1B8 */
779 int PAD; /* 0x1BC */
780 int PAD; /* 0x1C0 */
781 int PAD; /* 0x1C4 */
782 short PAD; /* 0x1C8 */
783 char bandlocked; /* 0x1CA */
784 char field_1CB; /* 0x1CB */
785 int PAD; /* 0x1CC */
786 int PAD; /* 0x1D0 */
787 int PAD; /* 0x1D4 */
788 int PAD; /* 0x1D8 */
789 int PAD; /* 0x1DC */
790 int PAD; /* 0x1E0 */
791 int PAD; /* 0x1E4 */
792 int PAD; /* 0x1E8 */
793 int PAD; /* 0x1EC */
794 int PAD; /* 0x1F0 */
795 int PAD; /* 0x1F4 */
796 int PAD; /* 0x1F8 */
797 int PAD; /* 0x1FC */
798 int PAD; /* 0x200 */
799 int PAD; /* 0x204 */
800 int PAD; /* 0x208 */
801 int monitor; /* 0x20C */
802 int bcnmisc_ibss; /* 0x210 */
803 int bcnmisc_scan; /* 0x214 */
804 int bcnmisc_monitor; /* 0x218 */
805 int PAD; /* 0x21C */
806 int PAD; /* 0x220 */
807 int PAD; /* 0x224 */
808 short PAD; /* 0x228 */
809 short wme_dp; /* 0x22A */
810 int PAD; /* 0x22C */
811 int PAD; /* 0x230 */
812 int PAD; /* 0x234 */
813 int PAD; /* 0x238 */
814 int PAD; /* 0x23C */
815 int PAD; /* 0x240 */
816 int PAD; /* 0x244 */
817 int PAD; /* 0x248 */
818 unsigned short tx_prec_map; /* 0x24C */
819 short PAD; /* 0x24E */
820 int PAD; /* 0x250 */
821 int PAD; /* 0x254 */
822 int PAD; /* 0x258 */
823 int PAD; /* 0x25C */
824 int PAD; /* 0x260 */
825 int PAD; /* 0x264 */
826 int PAD; /* 0x268 */
827 int PAD; /* 0x26C */
828 int PAD; /* 0x270 */
829 int PAD; /* 0x274 */
830 int PAD; /* 0x278 */
831 int PAD; /* 0x27C */
832 int PAD; /* 0x280 */
833 int PAD; /* 0x284 */
834 int PAD; /* 0x288 */
835 int PAD; /* 0x28C */
836 int PAD; /* 0x290 */
837 int PAD; /* 0x294 */
838 int PAD; /* 0x298 */
839 int PAD; /* 0x29C */
840 int PAD; /* 0x2A0 */
841 int PAD; /* 0x2A4 */
842 int PAD; /* 0x2A8 */
843 int PAD; /* 0x2AC */
844 int PAD; /* 0x2B0 */
845 int PAD; /* 0x2B4 */
846 int PAD; /* 0x2B8 */
847 int PAD; /* 0x2BC */
848 int PAD; /* 0x2C0 */
849 int PAD; /* 0x2C4 */
850 int PAD; /* 0x2C8 */
851 int PAD; /* 0x2CC */
852 int PAD; /* 0x2D0 */
853 int PAD; /* 0x2D4 */
854 int PAD; /* 0x2D8 */
855 int PAD; /* 0x2DC */
856 int PAD; /* 0x2E0 */
857 int PAD; /* 0x2E4 */
858 int PAD; /* 0x2E8 */
859 int PAD; /* 0x2EC */
860 int PAD; /* 0x2F0 */
861 int PAD; /* 0x2F4 */
862 int PAD; /* 0x2F8 */
863 int PAD; /* 0x2FC */
864 int PAD; /* 0X300 */
865 int PAD; /* 0X304 */
866 int PAD; /* 0X308 */
867 int PAD; /* 0X30C */
868 int PAD; /* 0X310 */
869 int PAD; /* 0X314 */
870 int PAD; /* 0X318 */
871 int PAD; /* 0X31C */
872 int PAD; /* 0X320 */
873 int PAD; /* 0X324 */
874 int PAD; /* 0X328 */
875 int PAD; /* 0X32C */
876 int PAD; /* 0X330 */
877 int PAD; /* 0X334 */
878 int PAD; /* 0X338 */
879 void *scan_results; /* 0X33C */
880 int PAD; /* 0X340 */
881 void *custom_scan_results; /* 0X344 */
882 int PAD; /* 0X348 */
883 int PAD; /* 0X34C */
884 int PAD; /* 0X350 */
885 int PAD; /* 0X354 */
886 int PAD; /* 0X358 */
887 int PAD; /* 0X35C */
888 int PAD; /* 0X360 */
889 short *field_364; /* 0X364 */
890 int PAD; /* 0X368 */
891 int PAD; /* 0X36C */
892 int PAD; /* 0X370 */
893 int PAD; /* 0X374 */
894 int PAD; /* 0X378 */
895 int PAD; /* 0X37C */
896 int PAD; /* 0X380 */
897 int PAD; /* 0X384 */
898 int PAD; /* 0X388 */
899 int PAD; /* 0X38C */
900 int PAD; /* 0X390 */
901 int PAD; /* 0X394 */
902 int PAD; /* 0X398 */
903 int PAD; /* 0X39C */
904 int PAD; /* 0X3A0 */
905 int PAD; /* 0X3A4 */
906 int PAD; /* 0X3A8 */
907 int PAD; /* 0X3AC */
908 int PAD; /* 0X3B0 */
909 int PAD; /* 0X3B4 */
910 int PAD; /* 0X3B8 */
911 int PAD; /* 0X3BC */
912 int PAD; /* 0X3C0 */
913 int PAD; /* 0X3C4 */
914 int PAD; /* 0X3C8 */
915 int PAD; /* 0X3CC */
916 int PAD; /* 0X3D0 */
917 int PAD; /* 0X3D4 */
918 int PAD; /* 0X3D8 */
919 int PAD; /* 0X3DC */
920 int PAD; /* 0X3E0 */
921 int PAD; /* 0X3E4 */
922 int PAD; /* 0X3E8 */
923 int PAD; /* 0X3EC */
924 int PAD; /* 0X3F0 */
925 int PAD; /* 0X3F4 */
926 int PAD; /* 0X3F8 */
927 int PAD; /* 0X3FC */
928 int PAD; /* 0X400 */
929 int PAD; /* 0X404 */
930 int PAD; /* 0X408 */
931 int PAD; /* 0X40C */
932 int PAD; /* 0X410 */
933 int PAD; /* 0X414 */
934 int PAD; /* 0X418 */
935 int PAD; /* 0X41C */
936 int PAD; /* 0X420 */
937 int PAD; /* 0X424 */
938 int PAD; /* 0X428 */
939 int PAD; /* 0X42C */
940 int PAD; /* 0X430 */
941 int PAD; /* 0X434 */
942 int PAD; /* 0X438 */
943 int PAD; /* 0X43C */
944 int PAD; /* 0X440 */
945 int PAD; /* 0X444 */
946 int PAD; /* 0X448 */
947 int PAD; /* 0X44C */
948 int PAD; /* 0X450 */
949 int PAD; /* 0X454 */
950 int PAD; /* 0X458 */
951 int PAD; /* 0X45C */
952 int PAD; /* 0X460 */
953 int PAD; /* 0X464 */
954 int PAD; /* 0X468 */
955 int PAD; /* 0X46C */
956 int PAD; /* 0X470 */
957 int PAD; /* 0X474 */
958 int PAD; /* 0X478 */
959 int PAD; /* 0X47C */
960 int PAD; /* 0X480 */
961 int PAD; /* 0X484 */
962 int PAD; /* 0X488 */
963 int PAD; /* 0X48C */
964 int PAD; /* 0X490 */
965 int PAD; /* 0X494 */
966 int PAD; /* 0X498 */
967 int PAD; /* 0X49C */
968 int PAD; /* 0X4A0 */
969 int PAD; /* 0X4A4 */
970 int PAD; /* 0X4A8 */
971 int PAD; /* 0X4AC */
972 int PAD; /* 0X4B0 */
973 int PAD; /* 0X4B4 */
974 int PAD; /* 0X4B8 */
975 int PAD; /* 0X4BC */
976 int PAD; /* 0X4C0 */
977 int PAD; /* 0X4C4 */
978 int PAD; /* 0X4C8 */
979 int PAD; /* 0X4CC */
980 int PAD; /* 0X4D0 */
981 int PAD; /* 0X4D4 */
982 int PAD; /* 0X4D8 */
983 int PAD; /* 0X4DC */
984 int PAD; /* 0X4E0 */
985 int PAD; /* 0X4E4 */
986 int PAD; /* 0X4E8 */
987 int PAD; /* 0X4EC */
988 int PAD; /* 0X4F0 */
989 int PAD; /* 0X4F4 */
990 int PAD; /* 0X4F8 */
991 int PAD; /* 0X4FC */
992 int PAD; /* 0X500 */
993 int PAD; /* 0X504 */
994 int PAD; /* 0X508 */
995 int PAD; /* 0X50C */
996 short some_chanspec; /* 0X510 */
997 short PAD; /* 0X512 */
998 int PAD; /* 0X514 */
999 int PAD; /* 0X518 */
1000 int PAD; /* 0X51C */
1001 int PAD; /* 0X520 */
1002 int PAD; /* 0X524 */
1003 int PAD; /* 0X528 */
1004 int PAD; /* 0X52C */
1005 int PAD; /* 0X530 */
1006 int PAD; /* 0X534 */
1007 int PAD; /* 0X538 */
1008 int PAD; /* 0X53C */
1009 int PAD; /* 0X540 */
1010 int PAD; /* 0X544 */
1011 int PAD; /* 0X548 */
1012 int PAD; /* 0X54C */
1013 int PAD; /* 0X550 */
1014 int PAD; /* 0X554 */
1015 int PAD; /* 0X558 */
1016 int PAD; /* 0X55C */
1017 int PAD; /* 0X560 */
1018 int PAD; /* 0X564 */
1019 int PAD; /* 0X568 */
1020 int PAD; /* 0X56C */
1021 int PAD; /* 0X570 */
1022 int PAD; /* 0X574 */
1023 int PAD; /* 0X578 */
1024 int PAD; /* 0X57C */
1025 int PAD; /* 0X580 */
1026 int PAD; /* 0X584 */
1027 int PAD; /* 0X588 */
1028 int PAD; /* 0X58C */
1029 int PAD; /* 0X590 */
1030 int PAD; /* 0X594 */
1031 int PAD; /* 0X598 */
1032 int PAD; /* 0X59C */
1033 int PAD; /* 0X5A0 */
1034 int PAD; /* 0X5A4 */
1035 int PAD; /* 0X5A8 */
1036 int PAD; /* 0X5AC */
1037 int PAD; /* 0X5B0 */
1038 int PAD; /* 0X5B4 */
1039 int PAD; /* 0X5B8 */
1040 int PAD; /* 0X5BC */
1041 int PAD; /* 0X5C0 */
1042 int PAD; /* 0X5C4 */
1043 int PAD; /* 0X5C8 */
1044 struct wlc_if *wlcif_list; /* 0X5CC NOT CHECKED for 7.45.154 */
1045 void *active_queue; /* 0X5D0 */
1046 int PAD; /* 0X5D4 */ //active_queue duplicate
1047 int PAD; /* 0X5D8 */
1048 int PAD; /* 0X5DC */
1049 int PAD; /* 0X5E0 */
1050 int PAD; /* 0X5E4 */
1051 int PAD; /* 0X5E8 */
1052 int PAD; /* 0X5EC */
1053 int PAD; /* 0X5F0 */
1054 int PAD; /* 0X5F4 */
1055 int PAD; /* 0X5F8 */
1056 int PAD; /* 0X5FC */
1057 };
1058  
1059 struct wlc_pub {
1060 struct wlc_info *wlc; /* 0x000 */
1061 int PAD; /* 0x004 */
1062 int PAD; /* 0x008 */
1063 int PAD; /* 0x00C */
1064 int PAD; /* 0x010 */
1065 void *osh; /* 0x014 */
1066 int PAD; /* 0x018 */
1067 int PAD; /* 0x01C */
1068 int PAD; /* 0x020 */
1069 char up_maybe; /* 0x024 */
1070 char field_25; /* 0x025 */
1071 char field_26; /* 0x026 */
1072 char field_27; /* 0x027 */
1073 struct tunables *tunables; /* 0x028 */
1074 int PAD; /* 0x02C */
1075 int field_30; /* 0x030 */
1076 int PAD; /* 0x034 */
1077 int PAD; /* 0x038 */
1078 int PAD; /* 0x03C */
1079 int PAD; /* 0x040 */
1080 char PAD; /* 0x044 */
1081 char PAD; /* 0x045 */
1082 char field_46; /* 0x046 */
1083 char PAD; /* 0x047 */
1084 int PAD; /* 0x048 */
1085 char associated; /* 0x04C */
1086 char PAD; /* 0x04D */
1087 char PAD; /* 0x04E */
1088 char PAD; /* 0x04F */
1089 int PAD; /* 0x050 */
1090 char gap2[147];
1091 char is_amsdu; // @ 0xe7
1092 } __attribute__((packed));
1093  
1094 struct wlc_bsscfg {
1095 void *wlc; /* 0x000 */
1096 char associated; /* 0x004 */
1097 char PAD; /* 0x005 */
1098 char PAD; /* 0x006 */
1099 char PAD; /* 0x007 */
1100 int PAD; /* 0x008 */
1101 int PAD; /* 0x00C */
1102 int PAD; /* 0x010 */
1103 int PAD; /* 0x014 */
1104 int PAD; /* 0x018 */
1105 int PAD; /* 0x01C */
1106 int PAD; /* 0x020 */
1107 int PAD; /* 0x024 */
1108 int PAD; /* 0x028 */
1109 int PAD; /* 0x02C */
1110 int PAD; /* 0x030 */
1111 int PAD; /* 0x034 */
1112 int PAD; /* 0x038 */
1113 int PAD; /* 0x03C */
1114 int PAD; /* 0x040 */
1115 int PAD; /* 0x044 */
1116 int PAD; /* 0x048 */
1117 int PAD; /* 0x04C */
1118 int PAD; /* 0x050 */
1119 int PAD; /* 0x054 */
1120 int PAD; /* 0x058 */
1121 int PAD; /* 0x05C */
1122 int PAD; /* 0x060 */
1123 int PAD; /* 0x064 */
1124 int PAD; /* 0x068 */
1125 int PAD; /* 0x06C */
1126 int PAD; /* 0x070 */
1127 int PAD; /* 0x074 */
1128 int PAD; /* 0x078 */
1129 int PAD; /* 0x07C */
1130 int PAD; /* 0x080 */
1131 int PAD; /* 0x084 */
1132 int PAD; /* 0x088 */
1133 int PAD; /* 0x08C */
1134 int PAD; /* 0x090 */
1135 int PAD; /* 0x094 */
1136 int PAD; /* 0x098 */
1137 int PAD; /* 0x09C */
1138 int PAD; /* 0x0A0 */
1139 int PAD; /* 0x0A4 */
1140 int PAD; /* 0x0A8 */
1141 int PAD; /* 0x0AC */
1142 int PAD; /* 0x0B0 */
1143 int PAD; /* 0x0B4 */
1144 int PAD; /* 0x0B8 */
1145 int PAD; /* 0x0BC */
1146 int PAD; /* 0x0C0 */
1147 int PAD; /* 0x0C4 */
1148 int PAD; /* 0x0C8 */
1149 int PAD; /* 0x0CC */
1150 int PAD; /* 0x0D0 */
1151 int PAD; /* 0x0D4 */
1152 int PAD; /* 0x0D8 */
1153 int PAD; /* 0x0DC */
1154 int PAD; /* 0x0E0 */
1155 int PAD; /* 0x0E4 */
1156 int PAD; /* 0x0E8 */
1157 int PAD; /* 0x0EC */
1158 int PAD; /* 0x0F0 */
1159 int PAD; /* 0x0F4 */
1160 int PAD; /* 0x0F8 */
1161 int PAD; /* 0x0FC */
1162 int PAD; /* 0x100 */
1163 int PAD; /* 0x104 */
1164 int PAD; /* 0x108 */
1165 int PAD; /* 0x10C */
1166 int PAD; /* 0x110 */
1167 int PAD; /* 0x114 */
1168 int PAD; /* 0x118 */
1169 int PAD; /* 0x11C */
1170 int PAD; /* 0x120 */
1171 int PAD; /* 0x124 */
1172 int PAD; /* 0x128 */
1173 int PAD; /* 0x12C */
1174 int PAD; /* 0x130 */
1175 int PAD; /* 0x134 */
1176 int PAD; /* 0x138 */
1177 int PAD; /* 0x13C */
1178 int PAD; /* 0x140 */
1179 int PAD; /* 0x144 */
1180 int PAD; /* 0x148 */
1181 int PAD; /* 0x14C */
1182 int PAD; /* 0x150 */
1183 int PAD; /* 0x154 */
1184 int PAD; /* 0x158 */
1185 int PAD; /* 0x15C */
1186 int PAD; /* 0x160 */
1187 int PAD; /* 0x164 */
1188 int PAD; /* 0x168 */
1189 int PAD; /* 0x16C */
1190 int PAD; /* 0x170 */
1191 int PAD; /* 0x174 */
1192 int PAD; /* 0x178 */
1193 int PAD; /* 0x17C */
1194 int PAD; /* 0x180 */
1195 int PAD; /* 0x184 */
1196 int PAD; /* 0x188 */
1197 int PAD; /* 0x18C */
1198 int PAD; /* 0x190 */
1199 int PAD; /* 0x194 */
1200 int PAD; /* 0x198 */
1201 int PAD; /* 0x19C */
1202 int PAD; /* 0x1A0 */
1203 int PAD; /* 0x1A4 */
1204 int PAD; /* 0x1A8 */
1205 int PAD; /* 0x1AC */
1206 int PAD; /* 0x1B0 */
1207 int PAD; /* 0x1B4 */
1208 int PAD; /* 0x1B8 */
1209 int PAD; /* 0x1BC */
1210 int PAD; /* 0x1C0 */
1211 int PAD; /* 0x1C4 */
1212 int PAD; /* 0x1C8 */
1213 int PAD; /* 0x1CC */
1214 int PAD; /* 0x1D0 */
1215 int PAD; /* 0x1D4 */
1216 int PAD; /* 0x1D8 */
1217 int PAD; /* 0x1DC */
1218 int PAD; /* 0x1E0 */
1219 int PAD; /* 0x1E4 */
1220 int PAD; /* 0x1E8 */
1221 int PAD; /* 0x1EC */
1222 int PAD; /* 0x1F0 */
1223 int PAD; /* 0x1F4 */
1224 int PAD; /* 0x1F8 */
1225 int PAD; /* 0x1FC */
1226 int PAD; /* 0x200 */
1227 int PAD; /* 0x204 */
1228 int PAD; /* 0x208 */
1229 int PAD; /* 0x20C */
1230 int PAD; /* 0x210 */
1231 int PAD; /* 0x214 */
1232 int PAD; /* 0x218 */
1233 int PAD; /* 0x21C */
1234 int PAD; /* 0x220 */
1235 int PAD; /* 0x224 */
1236 int PAD; /* 0x228 */
1237 int PAD; /* 0x22C */
1238 int PAD; /* 0x230 */
1239 int PAD; /* 0x234 */
1240 int PAD; /* 0x238 */
1241 int PAD; /* 0x23C */
1242 int PAD; /* 0x240 */
1243 int PAD; /* 0x244 */
1244 int PAD; /* 0x248 */
1245 int PAD; /* 0x24C */
1246 int PAD; /* 0x250 */
1247 int PAD; /* 0x254 */
1248 int PAD; /* 0x258 */
1249 int PAD; /* 0x25C */
1250 int PAD; /* 0x260 */
1251 int PAD; /* 0x264 */
1252 int PAD; /* 0x268 */
1253 int PAD; /* 0x26C */
1254 int PAD; /* 0x270 */
1255 int PAD; /* 0x274 */
1256 int PAD; /* 0x278 */
1257 int PAD; /* 0x27C */
1258 int PAD; /* 0x280 */
1259 int PAD; /* 0x284 */
1260 int PAD; /* 0x288 */
1261 int PAD; /* 0x28C */
1262 int PAD; /* 0x290 */
1263 int PAD; /* 0x294 */
1264 int PAD; /* 0x298 */
1265 int PAD; /* 0x29C */
1266 int PAD; /* 0x2A0 */
1267 int PAD; /* 0x2A4 */
1268 int PAD; /* 0x2A8 */
1269 int PAD; /* 0x2AC */
1270 int PAD; /* 0x2B0 */
1271 int PAD; /* 0x2B4 */
1272 int PAD; /* 0x2B8 */
1273 int PAD; /* 0x2BC */
1274 int PAD; /* 0x2C0 */
1275 int PAD; /* 0x2C4 */
1276 int PAD; /* 0x2C8 */
1277 int PAD; /* 0x2CC */
1278 int PAD; /* 0x2D0 */
1279 int PAD; /* 0x2D4 */
1280 int PAD; /* 0x2D8 */
1281 int PAD; /* 0x2DC */
1282 int PAD; /* 0x2E0 */
1283 int PAD; /* 0x2E4 */
1284 int PAD; /* 0x2E8 */
1285 int PAD; /* 0x2EC */
1286 int PAD; /* 0x2F0 */
1287 int PAD; /* 0x2F4 */
1288 int PAD; /* 0x2F8 */
1289 int PAD; /* 0x2FC */
1290 int PAD; /* 0X300 */
1291 int PAD; /* 0X304 */
1292 int PAD; /* 0X308 */
1293 int PAD; /* 0X30C */
1294 int PAD; /* 0X310 */
1295 int PAD; /* 0X314 */
1296 int PAD; /* 0X318 */
1297 int PAD; /* 0X31C */
1298 int PAD; /* 0X320 */
1299 int PAD; /* 0X324 */
1300 int PAD; /* 0X328 */
1301 int PAD; /* 0X32C */
1302 int PAD; /* 0X330 */
1303 int PAD; /* 0X334 */
1304 int PAD; /* 0X338 */
1305 int PAD; /* 0X33C */
1306 int PAD; /* 0X340 */
1307 int PAD; /* 0X344 */
1308 int PAD; /* 0X348 */
1309 int PAD; /* 0X34C */
1310 int PAD; /* 0X350 */
1311 int PAD; /* 0X354 */
1312 int PAD; /* 0X358 */
1313 int PAD; /* 0X35C */
1314 int PAD; /* 0X360 */
1315 int PAD; /* 0X364 */
1316 int PAD; /* 0X368 */
1317 int PAD; /* 0X36C */
1318 int PAD; /* 0X370 */
1319 int PAD; /* 0X374 */
1320 int PAD; /* 0X378 */
1321 int PAD; /* 0X37C */
1322 int PAD; /* 0X380 */
1323 int PAD; /* 0X384 */
1324 int PAD; /* 0X388 */
1325 int PAD; /* 0X38C */
1326 int PAD; /* 0X390 */
1327 int PAD; /* 0X394 */
1328 int PAD; /* 0X398 */
1329 int PAD; /* 0X39C */
1330 int PAD; /* 0X3A0 */
1331 int PAD; /* 0X3A4 */
1332 int PAD; /* 0X3A8 */
1333 int PAD; /* 0X3AC */
1334 int PAD; /* 0X3B0 */
1335 int PAD; /* 0X3B4 */
1336 int PAD; /* 0X3B8 */
1337 int PAD; /* 0X3BC */
1338 int PAD; /* 0X3C0 */
1339 int PAD; /* 0X3C4 */
1340 int PAD; /* 0X3C8 */
1341 int PAD; /* 0X3CC */
1342 int PAD; /* 0X3D0 */
1343 int PAD; /* 0X3D4 */
1344 int PAD; /* 0X3D8 */
1345 int PAD; /* 0X3DC */
1346 int PAD; /* 0X3E0 */
1347 int PAD; /* 0X3E4 */
1348 int PAD; /* 0X3E8 */
1349 int PAD; /* 0X3EC */
1350 int PAD; /* 0X3F0 */
1351 int PAD; /* 0X3F4 */
1352 int PAD; /* 0X3F8 */
1353 int PAD; /* 0X3FC */
1354 int PAD; /* 0X400 */
1355 int PAD; /* 0X404 */
1356 int PAD; /* 0X408 */
1357 int PAD; /* 0X40C */
1358 int PAD; /* 0X410 */
1359 int PAD; /* 0X414 */
1360 int PAD; /* 0X418 */
1361 int PAD; /* 0X41C */
1362 int PAD; /* 0X420 */
1363 int PAD; /* 0X424 */
1364 int PAD; /* 0X428 */
1365 int PAD; /* 0X42C */
1366 int PAD; /* 0X430 */
1367 int PAD; /* 0X434 */
1368 int PAD; /* 0X438 */
1369 int PAD; /* 0X43C */
1370 int PAD; /* 0X440 */
1371 int PAD; /* 0X444 */
1372 int PAD; /* 0X448 */
1373 int PAD; /* 0X44C */
1374 int PAD; /* 0X450 */
1375 int PAD; /* 0X454 */
1376 int PAD; /* 0X458 */
1377 int PAD; /* 0X45C */
1378 int PAD; /* 0X460 */
1379 int PAD; /* 0X464 */
1380 int PAD; /* 0X468 */
1381 int PAD; /* 0X46C */
1382 int PAD; /* 0X470 */
1383 int PAD; /* 0X474 */
1384 int PAD; /* 0X478 */
1385 int PAD; /* 0X47C */
1386 int PAD; /* 0X480 */
1387 int PAD; /* 0X484 */
1388 int PAD; /* 0X488 */
1389 int PAD; /* 0X48C */
1390 int PAD; /* 0X490 */
1391 int PAD; /* 0X494 */
1392 int PAD; /* 0X498 */
1393 int PAD; /* 0X49C */
1394 int PAD; /* 0X4A0 */
1395 int PAD; /* 0X4A4 */
1396 int PAD; /* 0X4A8 */
1397 int PAD; /* 0X4AC */
1398 int PAD; /* 0X4B0 */
1399 int PAD; /* 0X4B4 */
1400 int PAD; /* 0X4B8 */
1401 int PAD; /* 0X4BC */
1402 int PAD; /* 0X4C0 */
1403 int PAD; /* 0X4C4 */
1404 int PAD; /* 0X4C8 */
1405 int PAD; /* 0X4CC */
1406 int PAD; /* 0X4D0 */
1407 int PAD; /* 0X4D4 */
1408 int PAD; /* 0X4D8 */
1409 int PAD; /* 0X4DC */
1410 int PAD; /* 0X4E0 */
1411 int PAD; /* 0X4E4 */
1412 int PAD; /* 0X4E8 */
1413 int PAD; /* 0X4EC */
1414 int PAD; /* 0X4F0 */
1415 int PAD; /* 0X4F4 */
1416 int PAD; /* 0X4F8 */
1417 int PAD; /* 0X4FC */
1418 int PAD; /* 0X500 */
1419 int PAD; /* 0X504 */
1420 int PAD; /* 0X508 */
1421 int PAD; /* 0X50C */
1422 int PAD; /* 0X510 */
1423 int PAD; /* 0X514 */
1424 int PAD; /* 0X518 */
1425 int PAD; /* 0X51C */
1426 int PAD; /* 0X520 */
1427 int PAD; /* 0X524 */
1428 int PAD; /* 0X528 */
1429 int PAD; /* 0X52C */
1430 int PAD; /* 0X530 */
1431 int PAD; /* 0X534 */
1432 int PAD; /* 0X538 */
1433 int PAD; /* 0X53C */
1434 int PAD; /* 0X540 */
1435 short PAD; /* 0X544 */
1436 short field_546; /* 0X546 */
1437 int PAD; /* 0X548 */
1438 int PAD; /* 0X54C */
1439 int PAD; /* 0X550 */
1440 int PAD; /* 0X554 */
1441 int PAD; /* 0X558 */
1442 int PAD; /* 0X55C */
1443 int PAD; /* 0X560 */
1444 int PAD; /* 0X564 */
1445 int PAD; /* 0X568 */
1446 int PAD; /* 0X56C */
1447 int PAD; /* 0X570 */
1448 int PAD; /* 0X574 */
1449 int PAD; /* 0X578 */
1450 int PAD; /* 0X57C */
1451 int PAD; /* 0X580 */
1452 int PAD; /* 0X584 */
1453 } __attribute__((packed));
1454  
1455 struct hnddma_pub {
1456 void *di_fn; /* DMA function pointers */
1457 unsigned int txavail; /* # free tx descriptors */
1458 unsigned int dmactrlflags; /* dma control flags */
1459 /* rx error counters */
1460 unsigned int rxgiants; /* rx giant frames */
1461 unsigned int rxnobuf; /* rx out of dma descriptors */
1462 /* tx error counters */
1463 unsigned int txnobuf; /* tx out of dma descriptors */
1464 } __attribute__((packed));
1465  
1466 struct dma_info {
1467 struct hnddma_pub hnddma; /* exported structure */
1468 int msg_level; /* message level pointer */
1469 int something;
1470 char name[8]; /* callers name for diag msgs */
1471 void *osh;
1472 void *sih;
1473 bool dma64; /* this dma engine is operating in 64-bit mode */
1474 bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
1475 char gap2[2];
1476 void *txregs; /* 64-bit dma tx engine registers */
1477 void *rxregs; /* 64-bit dma rx engine registers */
1478 void *txd; /* pointer to dma64 tx descriptor ring */
1479 void *rxd; /* pointer to dma64 rx descriptor ring */
1480 short dmadesc_align; /* alignment requirement for dma descriptors */
1481 short ntxd; /* # tx descriptors tunable */
1482 short txin; /* index of next descriptor to reclaim */
1483 short txout; /* index of next descriptor to post */
1484 void **txp; /* pointer to parallel array of pointers to packets */
1485 void *tx_dmah; /* DMA MAP meta-data handle */
1486 int txp_dmah;
1487 int txdpa; /* Aligned physical address of descriptor ring */
1488 int txdpaorig; /* Original physical address of descriptor ring */
1489 short txdalign; /* #bytes added to alloc'd mem to align txd */
1490 int txdalloc; /* #bytes allocated for the ring */
1491 int xmtptrbase; /* When using unaligned descriptors, the ptr register
1492 * is not just an index, it needs all 13 bits to be
1493 * an offset from the addr register.
1494 */
1495 short PAD;
1496 short nrxd;
1497 short rxin;
1498 short rxout;
1499 short PAD;
1500 void **rxp;
1501 int PAD;
1502 int PAD;
1503 int rxdpa;
1504 short rxdalign;
1505 short PAD;
1506 int PAD;
1507 int PAD;
1508 int PAD;
1509 int rxbufsize; /* rx buffer size in bytes, not including the extra headroom */
1510 int rxextrahdrroom; /* extra rx headroom. */
1511  
1512 } __attribute__((packed));
1513  
1514 struct intctrlregs {
1515 unsigned int intstatus;
1516 unsigned int intmask;
1517 };
1518  
1519 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
1520 * write: only low 16b-it half can be written
1521 */
1522 union pmqreg {
1523 unsigned int pmqhostdata; /* read only! */
1524 struct {
1525 unsigned short pmqctrlstatus; /* read/write */
1526 unsigned short PAD;
1527 } w;
1528 };
1529  
1530 /* dma registers per channel(xmt or rcv) */
1531 struct dma64regs {
1532 unsigned int control; /* enable, et al */
1533 unsigned int ptr; /* last descriptor posted to chip */
1534 unsigned int addrlow; /* desc ring base address low 32-bits (8K aligned) */
1535 unsigned int addrhigh; /* desc ring base address bits 63:32 (8K aligned) */
1536 unsigned int status0; /* current descriptor, xmt state */
1537 unsigned int status1; /* active descriptor, xmt error */
1538 };
1539  
1540 /* 4byte-wide pio register set per channel(xmt or rcv) */
1541 struct pio4regs {
1542 unsigned int fifocontrol;
1543 unsigned int fifodata;
1544 };
1545  
1546 struct fifo64 {
1547 struct dma64regs dmaxmt; /* dma tx */
1548 struct pio4regs piotx; /* pio tx */
1549 struct dma64regs dmarcv; /* dma rx */
1550 struct pio4regs piorx; /* pio rx */
1551 };
1552  
1553 struct dma32diag { /* diag access */
1554 unsigned int fifoaddr; /* diag address */
1555 unsigned int fifodatalow; /* low 32bits of data */
1556 unsigned int fifodatahigh; /* high 32bits of data */
1557 unsigned int pad; /* reserved */
1558 };
1559  
1560 /*
1561 * Host Interface Registers
1562 */
1563 struct d11regs {
1564 /* Device Control ("semi-standard host registers") */
1565 unsigned int PAD[3]; /* 0x0 - 0x8 */
1566 unsigned int biststatus; /* 0xC */
1567 unsigned int biststatus2; /* 0x10 */
1568 unsigned int PAD; /* 0x14 */
1569 unsigned int gptimer; /* 0x18 */
1570 unsigned int usectimer; /* 0x1c *//* for corerev >= 26 */
1571  
1572 /* Interrupt Control *//* 0x20 */
1573 struct intctrlregs intctrlregs[8];
1574  
1575 unsigned int PAD[40]; /* 0x60 - 0xFC */
1576  
1577 unsigned int intrcvlazy[4]; /* 0x100 - 0x10C */
1578  
1579 unsigned int PAD[4]; /* 0x110 - 0x11c */
1580  
1581 unsigned int maccontrol; /* 0x120 */
1582 unsigned int maccommand; /* 0x124 */
1583 unsigned int macintstatus; /* 0x128 */
1584 unsigned int macintmask; /* 0x12C */
1585  
1586 /* Transmit Template Access */
1587 unsigned int tplatewrptr; /* 0x130 */
1588 unsigned int tplatewrdata; /* 0x134 */
1589 unsigned int PAD[2]; /* 0x138 - 0x13C */
1590  
1591 /* Power Management Queue (PMQ) registers */
1592 union pmqreg pmqreg; /* 0x140 */
1593 unsigned int pmqpatl; /* 0x144 */
1594 unsigned int pmqpath; /* 0x148 */
1595 unsigned int PAD; /* 0x14C */
1596  
1597 unsigned int chnstatus; /* 0x150 */
1598 unsigned int psmdebug; /* 0x154 */
1599 unsigned int phydebug; /* 0x158 */
1600 unsigned int machwcap; /* 0x15C */
1601  
1602 /* Extended Internal Objects */
1603 unsigned int objaddr; /* 0x160 */
1604 unsigned int objdata; /* 0x164 */
1605 unsigned int PAD[2]; /* 0x168 - 0x16c */
1606  
1607 unsigned int frmtxstatus; /* 0x170 */
1608 unsigned int frmtxstatus2; /* 0x174 */
1609 unsigned int PAD[2]; /* 0x178 - 0x17c */
1610  
1611 /* TSF host access */
1612 unsigned int tsf_timerlow; /* 0x180 */
1613 unsigned int tsf_timerhigh; /* 0x184 */
1614 unsigned int tsf_cfprep; /* 0x188 */
1615 unsigned int tsf_cfpstart; /* 0x18c */
1616 unsigned int tsf_cfpmaxdur32; /* 0x190 */
1617 unsigned int PAD[3]; /* 0x194 - 0x19c */
1618  
1619 unsigned int maccontrol1; /* 0x1a0 */
1620 unsigned int machwcap1; /* 0x1a4 */
1621 unsigned int PAD[14]; /* 0x1a8 - 0x1dc */
1622  
1623 /* Clock control and hardware workarounds*/
1624 unsigned int clk_ctl_st; /* 0x1e0 */
1625 unsigned int hw_war;
1626 unsigned int d11_phypllctl; /* the phypll request/avail bits are
1627 * moved to clk_ctl_st
1628 */
1629 unsigned int PAD[5]; /* 0x1ec - 0x1fc */
1630  
1631 /* 0x200-0x37F dma/pio registers */
1632 struct fifo64 fifo64regs[6];
1633  
1634 /* FIFO diagnostic port access */
1635 struct dma32diag dmafifo; /* 0x380 - 0x38C */
1636  
1637 unsigned int aggfifocnt; /* 0x390 */
1638 unsigned int aggfifodata; /* 0x394 */
1639 unsigned int PAD[16]; /* 0x398 - 0x3d4 */
1640 unsigned short radioregaddr; /* 0x3d8 */
1641 unsigned short radioregdata; /* 0x3da */
1642  
1643 /*
1644 * time delay between the change on rf disable input and
1645 * radio shutdown
1646 */
1647 unsigned int rfdisabledly; /* 0x3DC */
1648  
1649 /* PHY register access */
1650 unsigned short phyversion; /* 0x3e0 - 0x0 */
1651 unsigned short phybbconfig; /* 0x3e2 - 0x1 */
1652 unsigned short phyadcbias; /* 0x3e4 - 0x2 Bphy only */
1653 unsigned short phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
1654 unsigned short phyrxstatus0; /* 0x3e8 - 0x4 */
1655 unsigned short phyrxstatus1; /* 0x3ea - 0x5 */
1656 unsigned short phycrsth; /* 0x3ec - 0x6 */
1657 unsigned short phytxerror; /* 0x3ee - 0x7 */
1658 unsigned short phychannel; /* 0x3f0 - 0x8 */
1659 unsigned short PAD[1]; /* 0x3f2 - 0x9 */
1660 unsigned short phytest; /* 0x3f4 - 0xa */
1661 unsigned short phy4waddr; /* 0x3f6 - 0xb */
1662 unsigned short phy4wdatahi; /* 0x3f8 - 0xc */
1663 unsigned short phy4wdatalo; /* 0x3fa - 0xd */
1664 unsigned short phyregaddr; /* 0x3fc - 0xe */
1665 unsigned short phyregdata; /* 0x3fe - 0xf */
1666  
1667 /* IHR *//* 0x400 - 0x7FE */
1668  
1669 /* RXE Block */
1670 unsigned short PAD; /* SPR_RXE_0x00 0x400 */
1671 unsigned short PAD; /* SPR_RXE_Copy_Offset 0x402 */
1672 unsigned short PAD; /* SPR_RXE_Copy_Length 0x404 */
1673 unsigned short rcv_fifo_ctl; /* SPR_RXE_FIFOCTL0 0x406 */
1674 unsigned short PAD; /* SPR_RXE_FIFOCTL1 0x408 */
1675 unsigned short rcv_frm_cnt; /* SPR_Received_Frame_Count 0x40a */
1676 unsigned short PAD; /* SPR_RXE_0x0c 0x40c */
1677 unsigned short PAD; /* SPR_RXE_RXHDR_OFFSET 0x40e */
1678 unsigned short PAD; /* SPR_RXE_RXHDR_LEN 0x410 */
1679 unsigned short PAD; /* SPR_RXE_PHYRXSTAT0 0x412 */
1680 unsigned short rssi; /* SPR_RXE_PHYRXSTAT1 0x414 */
1681 unsigned short PAD; /* SPR_RXE_0x16 0x416 */
1682 unsigned short PAD; /* SPR_RXE_FRAMELEN 0x418 */
1683 unsigned short PAD; /* SPR_RXE_0x1a 0x41a */
1684 unsigned short PAD; /* SPR_RXE_ENCODING 0x41c */
1685 unsigned short PAD; /* SPR_RXE_0x1e 0x41e */
1686 unsigned short rcm_ctl; /* SPR_RCM_Control 0x420 */
1687 unsigned short rcm_mat_data; /* SPR_RCM_Match_Data 0x422 */
1688 unsigned short rcm_mat_mask; /* SPR_RCM_Match_Mask 0x424 */
1689 unsigned short rcm_mat_dly; /* SPR_RCM_Match_Delay 0x426 */
1690 unsigned short rcm_cond_mask_l; /* SPR_RCM_Condition_Mask_Low 0x428 */
1691 unsigned short rcm_cond_mask_h; /* SPR_RCM_Condition_Mask_High 0x42A */
1692 unsigned short rcm_cond_dly; /* SPR_RCM_Condition_Delay 0x42C */
1693 unsigned short PAD; /* SPR_RXE_0x2e 0x42E */
1694 unsigned short ext_ihr_addr; /* SPR_Ext_IHR_Address 0x430 */
1695 unsigned short ext_ihr_data; /* SPR_Ext_IHR_Data 0x432 */
1696 unsigned short rxe_phyrs_2; /* SPR_RXE_PHYRXSTAT2 0x434 */
1697 unsigned short rxe_phyrs_3; /* SPR_RXE_PHYRXSTAT3 0x436 */
1698 unsigned short phy_mode; /* SPR_PHY_Mode 0x438 */
1699 unsigned short rcmta_ctl; /* SPR_RCM_TA_Control 0x43a */
1700 unsigned short rcmta_size; /* SPR_RCM_TA_Size 0x43c */
1701 unsigned short rcmta_addr0; /* SPR_RCM_TA_Address_0 0x43e */
1702 unsigned short rcmta_addr1; /* SPR_RCM_TA_Address_1 0x440 */
1703 unsigned short rcmta_addr2; /* SPR_RCM_TA_Address_2 0x442 */
1704 unsigned short PAD[30]; /* SPR_RXE_0x44 ... 0x7e 0x444 */
1705  
1706  
1707 /* PSM Block *//* 0x480 - 0x500 */
1708  
1709 unsigned short PAD; /* SPR_MAC_MAX_NAP 0x480 */
1710 unsigned short psm_maccontrol_h; /* SPR_MAC_CTLHI 0x482 */
1711 unsigned short psm_macintstatus_l; /* SPR_MAC_IRQLO 0x484 */
1712 unsigned short psm_macintstatus_h; /* SPR_MAC_IRQHI 0x486 */
1713 unsigned short psm_macintmask_l; /* SPR_MAC_IRQMASKLO 0x488 */
1714 unsigned short psm_macintmask_h; /* SPR_MAC_IRQMASKHI 0x48A */
1715 unsigned short psm_0x0c; /* SPR_PSM_0x0c 0x48C */
1716 unsigned short psm_maccommand; /* SPR_MAC_CMD 0x48E */
1717 unsigned short psm_brc; /* SPR_BRC 0x490 */
1718 unsigned short psm_phy_hdr_param; /* SPR_PHY_HDR_Parameter 0x492 */
1719 unsigned short psm_postcard; /* SPR_Postcard 0x494 */
1720 unsigned short psm_pcard_loc_l; /* SPR_Postcard_Location_Low 0x496 */
1721 unsigned short psm_pcard_loc_h; /* SPR_Postcard_Location_High 0x498 */
1722 unsigned short psm_gpio_in; /* SPR_GPIO_IN 0x49A */
1723 unsigned short psm_gpio_out; /* SPR_GPIO_OUT 0x49C */
1724 unsigned short psm_gpio_oe; /* SPR_GPIO_OUTEN 0x49E */
1725  
1726 unsigned short psm_bred_0; /* SPR_BRED0 0x4A0 */
1727 unsigned short psm_bred_1; /* SPR_BRED1 0x4A2 */
1728 unsigned short psm_bred_2; /* SPR_BRED2 0x4A4 */
1729 unsigned short psm_bred_3; /* SPR_BRED3 0x4A6 */
1730 unsigned short psm_brcl_0; /* SPR_BRCL0 0x4A8 */
1731 unsigned short psm_brcl_1; /* SPR_BRCL1 0x4AA */
1732 unsigned short psm_brcl_2; /* SPR_BRCL2 0x4AC */
1733 unsigned short psm_brcl_3; /* SPR_BRCL3 0x4AE */
1734 unsigned short psm_brpo_0; /* SPR_BRPO0 0x4B0 */
1735 unsigned short psm_brpo_1; /* SPR_BRPO1 0x4B2 */
1736 unsigned short psm_brpo_2; /* SPR_BRPO2 0x4B4 */
1737 unsigned short psm_brpo_3; /* SPR_BRPO3 0x4B6 */
1738 unsigned short psm_brwk_0; /* SPR_BRWK0 0x4B8 */
1739 unsigned short psm_brwk_1; /* SPR_BRWK1 0x4BA */
1740 unsigned short psm_brwk_2; /* SPR_BRWK2 0x4BC */
1741 unsigned short psm_brwk_3; /* SPR_BRWK3 0x4BE */
1742  
1743 unsigned short psm_base_0; /* SPR_BASE0 - Offset Register 0 0x4C0 */
1744 unsigned short psm_base_1; /* SPR_BASE1 - Offset Register 1 0x4C2 */
1745 unsigned short psm_base_2; /* SPR_BASE2 - Offset Register 2 0x4C4 */
1746 unsigned short psm_base_3; /* SPR_BASE3 - Offset Register 3 0x4C6 */
1747 unsigned short psm_base_4; /* SPR_BASE4 - Offset Register 4 0x4C8 */
1748 unsigned short psm_base_5; /* SPR_BASE5 - Offset Register 5 0x4CA */
1749 unsigned short psm_base_6; /* SPR_BASE6 - Do not use (broken) 0x4CC */
1750 unsigned short psm_ihr_err; /* SPR_PSM_0x4e 0x4CE */
1751 unsigned short psm_pc_reg_0; /* SPR_PC0 - Link Register 0 0x4D0 */
1752 unsigned short psm_pc_reg_1; /* SPR_PC1 - Link Register 1 0x4D2 */
1753 unsigned short psm_pc_reg_2; /* SPR_PC2 - Link Register 2 0x4D4 */
1754 unsigned short psm_pc_reg_3; /* SPR_PC2 - Link Register 6 0x4D6 */
1755 unsigned short psm_brc_1; /* SPR_PSM_COND - PSM external condition bits 0x4D8 */
1756 unsigned short PAD; /* SPR_PSM_0x5a ... 0x7e 0x4DA */
1757 unsigned short PAD; /* SPR_PSM_0x5c 0x4DC */
1758 unsigned short PAD; /* SPR_PSM_0x5e 0x4DE */
1759 unsigned short PAD; /* SPR_PSM_0x60 0x4E0 */
1760 unsigned short PAD; /* SPR_PSM_0x62 0x4E2 */
1761 unsigned short PAD; /* SPR_PSM_0x64 0x4E4 */
1762 unsigned short PAD; /* SPR_PSM_0x66 0x4E6 */
1763 unsigned short PAD; /* SPR_PSM_0x68 0x4E8 */
1764 unsigned short PAD; /* SPR_PSM_0x6a 0x4EA */
1765 unsigned short PAD; /* SPR_PSM_0x6c 0x4EC */
1766 unsigned short PAD; /* SPR_PSM_0x6e 0x4EE */
1767 unsigned short psm_corectlsts; /* SPR_PSM_0x70 0x4F0 *//* Corerev >= 13 */
1768 unsigned short PAD; /* SPR_PSM_0x72 0x4F2 */
1769 unsigned short PAD; /* SPR_PSM_0x74 0x4F4 */
1770 unsigned short PAD; /* SPR_PSM_0x76 0x4F6 */
1771 unsigned short PAD; /* SPR_PSM_0x78 0x4F8 */
1772 unsigned short PAD; /* SPR_PSM_0x7a 0x4FA */
1773 unsigned short PAD; /* SPR_PSM_0x7c 0x4FC */
1774 unsigned short PAD; /* SPR_PSM_0x7e 0x4FE */
1775  
1776 /* TXE0 Block *//* 0x500 - 0x580 */
1777 unsigned short txe_ctl; /* SPR_TXE0_CTL 0x500 */
1778 unsigned short txe_aux; /* SPR_TXE0_AUX 0x502 */
1779 unsigned short txe_ts_loc; /* SPR_TXE0_TS_LOC 0x504 */
1780 unsigned short txe_time_out; /* SPR_TXE0_TIMEOUT 0x506 */
1781 unsigned short txe_wm_0; /* SPR_TXE0_WM0 0x508 */
1782 unsigned short txe_wm_1; /* SPR_TXE0_WM1 0x50A */
1783 unsigned short txe_phyctl; /* SPR_TXE0_PHY_CTL 0x50C */
1784 unsigned short txe_status; /* SPR_TXE0_STATUS 0x50E */
1785 unsigned short txe_mmplcp0; /* SPR_TXE0_0x10 0x510 */
1786 unsigned short txe_mmplcp1; /* SPR_TXE0_0x12 0x512 */
1787 unsigned short txe_phyctl1; /* SPR_TXE0_0x14 0x514 */
1788  
1789 unsigned short PAD; /* SPR_TXE0_0x16 0x516 */
1790 unsigned short PAD; /* SPR_TX_STATUS0 0x518 */
1791 unsigned short PAD; /* SPR_TX_STATUS1 0x51a */
1792 unsigned short PAD; /* SPR_TX_STATUS2 0x51c */
1793 unsigned short PAD; /* SPR_TX_STATUS3 0x51e */
1794  
1795 union {
1796 struct { // d11regs
1797 /* Transmit control */
1798 uint16 xmtfifodef; /* 0x520 */
1799 uint16 xmtfifo_frame_cnt; /* 0x522 */ /* Corerev >= 16 */
1800 uint16 xmtfifo_byte_cnt; /* 0x524 */ /* Corerev >= 16 */
1801 uint16 xmtfifo_head; /* 0x526 */ /* Corerev >= 16 */
1802 uint16 xmtfifo_rd_ptr; /* 0x528 */ /* Corerev >= 16 */
1803 uint16 xmtfifo_wr_ptr; /* 0x52A */ /* Corerev >= 16 */
1804 uint16 xmtfifodef1; /* 0x52C */ /* Corerev >= 16 */
1805  
1806 /* AggFifo */
1807 uint16 aggfifo_cmd; /* 0x52e */
1808 uint16 aggfifo_stat; /* 0x530 */
1809 uint16 aggfifo_cfgctl; /* 0x532 */
1810 uint16 aggfifo_cfgdata; /* 0x534 */
1811 uint16 aggfifo_mpdunum; /* 0x536 */
1812 uint16 aggfifo_len; /* 0x538 */
1813 uint16 aggfifo_bmp; /* 0x53A */
1814 uint16 aggfifo_ackedcnt; /* 0x53C */
1815 uint16 aggfifo_sel; /* 0x53E */
1816  
1817 uint16 xmtfifocmd; /* 0x540 */
1818 uint16 xmtfifoflush; /* 0x542 */
1819 uint16 xmtfifothresh; /* 0x544 */
1820 uint16 xmtfifordy; /* 0x546 */
1821 uint16 xmtfifoprirdy; /* 0x548 */
1822 uint16 xmtfiforqpri; /* 0x54A */
1823 uint16 xmttplatetxptr; /* 0x54C */
1824 uint16 PAD; /* 0x54E */
1825 uint16 xmttplateptr; /* 0x550 */
1826 uint16 smpl_clct_strptr; /* 0x552 */ /* Corerev >= 22 */
1827 uint16 smpl_clct_stpptr; /* 0x554 */ /* Corerev >= 22 */
1828 uint16 smpl_clct_curptr; /* 0x556 */ /* Corerev >= 22 */
1829 uint16 aggfifo_data; /* 0x558 */
1830 uint16 PAD[0x03]; /* 0x55A - 0x55E */
1831 uint16 xmttplatedatalo; /* 0x560 */
1832 uint16 xmttplatedatahi; /* 0x562 */
1833  
1834 uint16 PAD[2]; /* 0x564 - 0x566 */
1835  
1836 uint16 xmtsel; /* 0x568 */
1837 uint16 xmttxcnt; /* 0x56A */
1838 uint16 xmttxshmaddr; /* 0x56C */
1839  
1840 uint16 PAD[0x09]; /* 0x56E - 0x57E */
1841  
1842 /* TXE1 Block */
1843 uint16 PAD[0x40]; /* 0x580 - 0x5FE */
1844  
1845 /* TSF Block */
1846 uint16 PAD[0X02]; /* 0x600 - 0x602 */
1847 uint16 tsf_cfpstrt_l; /* 0x604 */
1848 uint16 tsf_cfpstrt_h; /* 0x606 */
1849 uint16 PAD[0X05]; /* 0x608 - 0x610 */
1850 uint16 tsf_cfppretbtt; /* 0x612 */
1851 uint16 PAD[0XD]; /* 0x614 - 0x62C */
1852 uint16 tsf_clk_frac_l; /* 0x62E */
1853 uint16 tsf_clk_frac_h; /* 0x630 */
1854 uint16 PAD[0X14]; /* 0x632 - 0x658 */
1855 uint16 tsf_random; /* 0x65A */
1856 uint16 PAD[0x05]; /* 0x65C - 0x664 */
1857 /* GPTimer 2 registers are corerev >= 3 */
1858 uint16 tsf_gpt2_stat; /* 0x666 */
1859 uint16 tsf_gpt2_ctr_l; /* 0x668 */
1860 uint16 tsf_gpt2_ctr_h; /* 0x66A */
1861 uint16 tsf_gpt2_val_l; /* 0x66C */
1862 uint16 tsf_gpt2_val_h; /* 0x66E */
1863 uint16 tsf_gptall_stat; /* 0x670 */
1864 uint16 PAD[0x07]; /* 0x672 - 0x67E */
1865  
1866 /* IFS Block */
1867 uint16 ifs_sifs_rx_tx_tx; /* 0x680 */
1868 uint16 ifs_sifs_nav_tx; /* 0x682 */
1869 uint16 ifs_slot; /* 0x684 */
1870 uint16 PAD; /* 0x686 */
1871 uint16 ifs_ctl; /* 0x688 */
1872 uint16 ifs_boff; /* 0x68a */
1873 uint16 PAD[0x2]; /* 0x68c - 0x68F */
1874 uint16 ifsstat; /* 0x690 */
1875 uint16 ifsmedbusyctl; /* 0x692 */
1876 uint16 iftxdur; /* 0x694 */
1877 uint16 PAD[0x3]; /* 0x696 - 0x69b */
1878 /* EDCF support in dot11macs with corerevs >= 16 */
1879 uint16 ifs_aifsn; /* 0x69c */
1880 uint16 ifs_ctl1; /* 0x69e */
1881  
1882 /* New slow clock registers on corerev >= 5 */
1883 uint16 scc_ctl; /* 0x6a0 */
1884 uint16 scc_timer_l; /* 0x6a2 */
1885 uint16 scc_timer_h; /* 0x6a4 */
1886 uint16 scc_frac; /* 0x6a6 */
1887 uint16 scc_fastpwrup_dly; /* 0x6a8 */
1888 uint16 scc_per; /* 0x6aa */
1889 uint16 scc_per_frac; /* 0x6ac */
1890 uint16 scc_cal_timer_l; /* 0x6ae */
1891 uint16 scc_cal_timer_h; /* 0x6b0 */
1892 uint16 PAD; /* 0x6b2 */
1893  
1894 /* BTCX block on corerev >=13 */
1895 uint16 btcx_ctrl; /* 0x6b4 */
1896 uint16 btcx_stat; /* 0x6b6 */
1897 uint16 btcx_trans_ctrl; /* 0x6b8 */
1898 uint16 btcx_pri_win; /* 0x6ba */
1899 uint16 btcx_tx_conf_timer; /* 0x6bc */
1900 uint16 btcx_ant_sw_timer; /* 0x6be */
1901  
1902 uint16 btcx_prv_rfact_timer; /* 0x6c0 */
1903 uint16 btcx_cur_rfact_timer; /* 0x6c2 */
1904 uint16 btcx_rfact_dur_timer; /* 0x6c4 */
1905  
1906 uint16 ifs_ctl_sel_pricrs; /* 0x6c6 */
1907 uint16 ifs_ctl_sel_seccrs; /* 0x6c8 */
1908 uint16 PAD[19]; /* 0x6ca - 0x6ee */
1909  
1910 /* ECI regs on corerev >=14 */
1911 uint16 btcx_eci_addr; /* 0x6f0 */
1912 uint16 btcx_eci_data; /* 0x6f2 */
1913  
1914 uint16 PAD[6];
1915  
1916 /* NAV Block */
1917 uint16 nav_ctl; /* 0x700 */
1918 uint16 navstat; /* 0x702 */
1919 uint16 PAD[0x3e]; /* 0x702 - 0x77E */
1920  
1921 /* WEP/PMQ Block */ /* 0x780 - 0x7FE */
1922 uint16 PAD[0x20]; /* 0x780 - 0x7BE */
1923  
1924 uint16 wepctl; /* 0x7C0 */
1925 uint16 wepivloc; /* 0x7C2 */
1926 uint16 wepivkey; /* 0x7C4 */
1927 uint16 wepwkey; /* 0x7C6 */
1928  
1929 uint16 PAD[4]; /* 0x7C8 - 0x7CE */
1930 uint16 pcmctl; /* 0X7D0 */
1931 uint16 pcmstat; /* 0X7D2 */
1932 uint16 PAD[6]; /* 0x7D4 - 0x7DE */
1933  
1934 uint16 pmqctl; /* 0x7E0 */
1935 uint16 pmqstatus; /* 0x7E2 */
1936 uint16 pmqpat0; /* 0x7E4 */
1937 uint16 pmqpat1; /* 0x7E6 */
1938 uint16 pmqpat2; /* 0x7E8 */
1939  
1940 uint16 pmqdat; /* 0x7EA */
1941 uint16 pmqdator; /* 0x7EC */
1942 uint16 pmqhst; /* 0x7EE */
1943 uint16 pmqpath0; /* 0x7F0 */
1944 uint16 pmqpath1; /* 0x7F2 */
1945 uint16 pmqpath2; /* 0x7F4 */
1946 uint16 pmqdath; /* 0x7F6 */
1947  
1948 uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */
1949 /* SHM */ /* 0x800 - 0xEFE */
1950 uint16 PAD[0x380]; /* 0x800 - 0xEFE */
1951 } d11regs;
1952  
1953 struct { // d11regs_nexmon_old
1954 /* Transmit control */
1955 unsigned short xmtfifodef; /* SPR_TXE0_FIFO_Def 0x520 */
1956 unsigned short xmtfifo_frame_cnt; /* SPR_TXE0_0x22 0x522 *//* Corerev >= 16 */
1957 unsigned short xmtfifo_byte_cnt; /* SPR_TXE0_0x24 0x524 *//* Corerev >= 16 */
1958 unsigned short xmtfifo_head; /* SPR_TXE0_0x26 0x526 *//* Corerev >= 16 */
1959 unsigned short xmtfifo_rd_ptr; /* SPR_TXE0_0x28 0x528 *//* Corerev >= 16 */
1960 unsigned short xmtfifo_wr_ptr; /* SPR_TXE0_0x2a 0x52A *//* Corerev >= 16 */
1961 unsigned short xmtfifodef1; /* SPR_TXE0_0x2c 0x52C *//* Corerev >= 16 */
1962  
1963 unsigned short PAD; /* SPR_TXE0_0x2e 0x52E */
1964 unsigned short PAD; /* SPR_TXE0_0x30 0x530 */
1965 unsigned short PAD; /* SPR_TXE0_0x32 0x532 */
1966 unsigned short PAD; /* SPR_TXE0_0x34 0x534 */
1967 unsigned short PAD; /* SPR_TXE0_0x36 0x536 */
1968 unsigned short PAD; /* SPR_TXE0_0x38 0x538 */
1969 unsigned short PAD; /* SPR_TXE0_0x3a 0x53A */
1970 unsigned short PAD; /* SPR_TXE0_0x3c 0x53C */
1971 unsigned short PAD; /* SPR_TXE0_0x3e 0x53E */
1972  
1973 unsigned short xmtfifocmd; /* SPR_TXE0_FIFO_CMD 0x540 */
1974 unsigned short xmtfifoflush; /* SPR_TXE0_FIFO_FLUSH 0x542 */
1975 unsigned short xmtfifothresh; /* SPR_TXE0_FIFO_THRES 0x544 */
1976 unsigned short xmtfifordy; /* SPR_TXE0_FIFO_RDY 0x546 */
1977 unsigned short xmtfifoprirdy; /* SPR_TXE0_FIFO_PRI_RDY 0x548 */
1978 unsigned short xmtfiforqpri; /* SPR_TXE0_FIFO_RQ_PRI 0x54A */
1979 unsigned short xmttplatetxptr; /* SPR_TXE0_Template_TX_Pointer 0x54C */
1980 unsigned short PAD; /* SPR_TXE0_0x4e 0x54E */
1981 unsigned short xmttplateptr; /* SPR_TXE0_Template_Pointer 0x550 */
1982 unsigned short smpl_clct_strptr; /* SPR_TXE0_0x52 0x552 *//* Corerev >= 22 */
1983 unsigned short smpl_clct_stpptr; /* SPR_TXE0_0x54 0x554 *//* Corerev >= 22 */
1984 unsigned short smpl_clct_curptr; /* SPR_TXE0_0x56 0x556 *//* Corerev >= 22 */
1985 unsigned short PAD; /* SPR_TXE0_0x58 0x558 */
1986 unsigned short PAD; /* SPR_TXE0_0x5a 0x55A */
1987 unsigned short PAD; /* SPR_TXE0_0x5c 0x55C */
1988 unsigned short PAD; /* SPR_TXE0_0x5e 0x55E */
1989 unsigned short xmttplatedatalo; /* SPR_TXE0_Template_Data_Low 0x560 */
1990 unsigned short xmttplatedatahi; /* SPR_TXE0_Template_Data_High 0x562 */
1991  
1992 unsigned short PAD; /* SPR_TXE0_0x64 0x564 */
1993 unsigned short PAD; /* SPR_TXE0_0x66 0x566 */
1994  
1995 unsigned short xmtsel; /* SPR_TXE0_SELECT 0x568 */
1996 unsigned short xmttxcnt; /* 0x56A */
1997 unsigned short xmttxshmaddr; /* 0x56C */
1998  
1999 unsigned short PAD[0x09]; /* 0x56E - 0x57E */
2000  
2001 /* TXE1 Block */
2002 unsigned short PAD[0x40]; /* 0x580 - 0x5FE */
2003  
2004 /* TSF Block */
2005 unsigned short PAD[0X02]; /* 0x600 - 0x602 */
2006 unsigned short tsf_cfpstrt_l; /* 0x604 */
2007 unsigned short tsf_cfpstrt_h; /* 0x606 */
2008 unsigned short PAD[0X05]; /* 0x608 - 0x610 */
2009 unsigned short tsf_cfppretbtt; /* 0x612 */
2010 unsigned short PAD[0XD]; /* 0x614 - 0x62C */
2011 unsigned short tsf_clk_frac_l; /* 0x62E */
2012 unsigned short tsf_clk_frac_h; /* 0x630 */
2013 unsigned short PAD[0X14]; /* 0x632 - 0x658 */
2014 unsigned short tsf_random; /* 0x65A */
2015 unsigned short PAD[0x05]; /* 0x65C - 0x664 */
2016 /* GPTimer 2 registers */
2017 unsigned short tsf_gpt2_stat; /* 0x666 */
2018 unsigned short tsf_gpt2_ctr_l; /* 0x668 */
2019 unsigned short tsf_gpt2_ctr_h; /* 0x66A */
2020 unsigned short tsf_gpt2_val_l; /* 0x66C */
2021 unsigned short tsf_gpt2_val_h; /* 0x66E */
2022 unsigned short tsf_gptall_stat; /* 0x670 */
2023 unsigned short PAD[0x07]; /* 0x672 - 0x67E */
2024  
2025 /* IFS Block */
2026 unsigned short ifs_sifs_rx_tx_tx; /* 0x680 */
2027 unsigned short ifs_sifs_nav_tx; /* 0x682 */
2028 unsigned short ifs_slot; /* 0x684 */
2029 unsigned short PAD; /* 0x686 */
2030 unsigned short ifs_ctl; /* 0x688 */
2031 unsigned short PAD[0x3]; /* 0x68a - 0x68F */
2032 unsigned short ifsstat; /* 0x690 */
2033 unsigned short ifsmedbusyctl; /* 0x692 */
2034 unsigned short iftxdur; /* 0x694 */
2035 unsigned short PAD[0x3]; /* 0x696 - 0x69b */
2036 /* EDCF support in dot11macs */
2037 unsigned short ifs_aifsn; /* 0x69c */
2038 unsigned short ifs_ctl1; /* 0x69e */
2039  
2040 /* slow clock registers */
2041 unsigned short scc_ctl; /* 0x6a0 */
2042 unsigned short scc_timer_l; /* 0x6a2 */
2043 unsigned short scc_timer_h; /* 0x6a4 */
2044 unsigned short scc_frac; /* 0x6a6 */
2045 unsigned short scc_fastpwrup_dly; /* 0x6a8 */
2046 unsigned short scc_per; /* 0x6aa */
2047 unsigned short scc_per_frac; /* 0x6ac */
2048 unsigned short scc_cal_timer_l; /* 0x6ae */
2049 unsigned short scc_cal_timer_h; /* 0x6b0 */
2050 unsigned short PAD; /* 0x6b2 */
2051  
2052 unsigned short PAD[0x26];
2053  
2054 /* NAV Block */
2055 unsigned short nav_ctl; /* 0x700 */
2056 unsigned short navstat; /* 0x702 */
2057 unsigned short PAD[0x3e]; /* 0x702 - 0x77E */
2058  
2059 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
2060 unsigned short PAD[0x20]; /* 0x780 - 0x7BE */
2061  
2062 unsigned short wepctl; /* 0x7C0 */
2063 unsigned short wepivloc; /* 0x7C2 */
2064 unsigned short wepivkey; /* 0x7C4 */
2065 unsigned short wepwkey; /* 0x7C6 */
2066  
2067 unsigned short PAD[4]; /* 0x7C8 - 0x7CE */
2068 unsigned short pcmctl; /* 0X7D0 */
2069 unsigned short pcmstat; /* 0X7D2 */
2070 unsigned short PAD[6]; /* 0x7D4 - 0x7DE */
2071  
2072 unsigned short pmqctl; /* 0x7E0 */
2073 unsigned short pmqstatus; /* 0x7E2 */
2074 unsigned short pmqpat0; /* 0x7E4 */
2075 unsigned short pmqpat1; /* 0x7E6 */
2076 unsigned short pmqpat2; /* 0x7E8 */
2077  
2078 unsigned short pmqdat; /* 0x7EA */
2079 unsigned short pmqdator; /* 0x7EC */
2080 unsigned short pmqhst; /* 0x7EE */
2081 unsigned short pmqpath0; /* 0x7F0 */
2082 unsigned short pmqpath1; /* 0x7F2 */
2083 unsigned short pmqpath2; /* 0x7F4 */
2084 unsigned short pmqdath; /* 0x7F6 */
2085  
2086 unsigned short PAD[0x04]; /* 0x7F8 - 0x7FE */
2087  
2088 /* SHM *//* 0x800 - 0xEFE */
2089 unsigned short PAD[0x380]; /* 0x800 - 0xEFE */
2090 } d11regs_nexmon_old;
2091  
2092 struct { // d11acregs
2093 uint16 XmtFIFOFullThreshold; /* 0x520 */
2094 uint16 XmtFifoFrameCnt; /* 0x522 */
2095 uint16 PAD[1];
2096 uint16 BMCReadReq; /* 0x526 */
2097 uint16 BMCReadOffset; /* 0x528 */
2098 uint16 BMCReadLength; /* 0x52a */
2099 uint16 BMCReadStatus; /* 0x52c */
2100 uint16 XmtShmAddr; /* 0x52e */
2101 uint16 PsmMSDUAccess; /* 0x530 */
2102 uint16 MSDUEntryBufCnt; /* 0x532 */
2103 uint16 MSDUEntryStartIdx; /* 0x534 */
2104 uint16 MSDUEntryEndIdx; /* 0x536 */
2105 uint16 SampleCollectPlayPtrHigh; /* 0x538 */
2106 uint16 SampleCollectCurPtrHigh; /* 0x53a */
2107 uint16 BMCCmd1; /* 0x53c */
2108 uint16 PAD[1];
2109 uint16 BMCCTL; /* 0x540 */
2110 uint16 BMCConfig; /* 0x542 */
2111 uint16 BMCStartAddr; /* 0x544 */
2112 uint16 BMCSize; /* 0x546 */
2113 uint16 BMCCmd; /* 0x548 */
2114 uint16 BMCMaxBuffers; /* 0x54a */
2115 uint16 BMCMinBuffers; /* 0x54c */
2116 uint16 BMCAllocCtl; /* 0x54e */
2117 uint16 BMCDescrLen; /* 0x550 */
2118 uint16 SampleCollectStartPtr; /* 0x552 */
2119 uint16 SampleCollectStopPtr; /* 0x554 */
2120 uint16 SampleCollectCurPtr; /* 0x556 */
2121 uint16 SaveRestoreStartPtr; /* 0x558 */
2122 uint16 SamplePlayStartPtr; /* 0x55a */
2123 uint16 SamplePlayStopPtr; /* 0x55c */
2124 uint16 XmtDMABusy; /* 0x55e */
2125 uint16 XmtTemplateDataLo; /* 0x560 */
2126 uint16 XmtTemplateDataHi; /* 0x562 */
2127 uint16 XmtTemplatePtr; /* 0x564 */
2128 uint16 XmtSuspFlush; /* 0x566 */
2129 uint16 XmtFifoRqPrio; /* 0x568 */
2130 uint16 BMCStatCtl; /* 0x56a */
2131 uint16 BMCStatData; /* 0x56c */
2132 uint16 BMCMSDUFifoStat; /* 0x56e */
2133 uint16 PAD[4]; /* 0x570-576 */
2134 uint16 txe_status1; /* 0x578 */
2135 uint16 PAD[323]; /* 0x57a - 0x800 */
2136  
2137 /* AQM */
2138 uint16 AQMConfig; /* 0x800 */
2139 uint16 AQMFifoDef; /* 0x802 */
2140 uint16 AQMMaxIdx; /* 0x804 */
2141 uint16 AQMRcvdBA0; /* 0x806 */
2142 uint16 AQMRcvdBA1; /* 0x808 */
2143 uint16 AQMRcvdBA2; /* 0x80a */
2144 uint16 AQMRcvdBA3; /* 0x80c */
2145 uint16 AQMBaSSN; /* 0x80e */
2146 uint16 AQMRefSN; /* 0x810 */
2147 uint16 AQMMaxAggLenLow; /* 0x812 */
2148 uint16 AQMMaxAggLenHi; /* 0x814 */
2149 uint16 AQMAggParams; /* 0x816 */
2150 uint16 AQMMinMpduLen; /* 0x818 */
2151 uint16 AQMMacAdjLen; /* 0x81a */
2152 uint16 DebugBusCtrl; /* 0x81c */
2153 uint16 PAD[1];
2154 uint16 AQMAggStats; /* 0x820 */
2155 uint16 AQMAggLenLow; /* 0x822 */
2156 uint16 AQMAggLenHi; /* 0x824 */
2157 uint16 AQMIdxFifo; /* 0x826 */
2158 uint16 AQMMpduLenFifo; /* 0x828 */
2159 uint16 AQMTxCntFifo; /* 0x82a */
2160 uint16 AQMUpdBA0; /* 0x82c */
2161 uint16 AQMUpdBA1; /* 0x82e */
2162 uint16 AQMUpdBA2; /* 0x830 */
2163 uint16 AQMUpdBA3; /* 0x832 */
2164 uint16 AQMAckCnt; /* 0x834 */
2165 uint16 AQMConsCnt; /* 0x836 */
2166 uint16 AQMFifoReady; /* 0x838 */
2167 uint16 AQMStartLoc; /* 0x83a */
2168 uint16 PAD[2];
2169 uint16 TDCCTL; /* 0x840 */
2170 uint16 TDC_Plcp0; /* 0x842 */
2171 uint16 TDC_Plcp1; /* 0x844 */
2172 uint16 TDC_FrmLen0; /* 0x846 */
2173 uint16 TDC_FrmLen1; /* 0x848 */
2174 uint16 TDC_Txtime; /* 0x84a */
2175 uint16 TDC_VhtSigB0; /* 0x84c */
2176 uint16 TDC_VhtSigB1; /* 0x84e */
2177 uint16 TDC_LSigLen; /* 0x850 */
2178 uint16 TDC_NSym0; /* 0x852 */
2179 uint16 TDC_NSym1; /* 0x854 */
2180 uint16 TDC_VhtPsduLen0; /* 0x856 */
2181 uint16 TDC_VhtPsduLen1; /* 0x858 */
2182 uint16 TDC_VhtMacPad; /* 0x85a */
2183 uint16 PAD[2];
2184 uint16 ShmDma_Ctl; /* 0x860 */
2185 uint16 ShmDma_TxdcAddr; /* 0x862 */
2186 uint16 ShmDma_ShmAddr; /* 0x864 */
2187 uint16 ShmDma_XferCnt; /* 0x866 */
2188 uint16 Txdc_Addr; /* 0x868 */
2189 uint16 Txdc_Data; /* 0x86a */
2190 uint16 PAD[10]; /* 0x86c - 0x880 */
2191  
2192 /* RXE Register */
2193 uint16 MHP_Status; /* 0x880 */
2194 uint16 MHP_FC; /* 0x882 */
2195 uint16 MHP_DUR; /* 0x884 */
2196 uint16 MHP_SC; /* 0x886 */
2197 uint16 MHP_QOS; /* 0x888 */
2198 uint16 MHP_HTC_H; /* 0x88a */
2199 uint16 MHP_HTC_L; /* 0x88c */
2200 uint16 MHP_Addr1_H; /* 0x88e */
2201 uint16 MHP_Addr1_M; /* 0x890 */
2202 uint16 MHP_Addr1_L; /* 0x892 */
2203 uint16 PAD[6]; /* 0x894 - 0x8a0 */
2204 uint16 MHP_Addr2_H; /* 0x8a0 */
2205 uint16 MHP_Addr2_M; /* 0x8a2 */
2206 uint16 MHP_Addr2_L; /* 0x8a4 */
2207 uint16 MHP_Addr3_H; /* 0x8a6 */
2208 uint16 MHP_Addr3_M; /* 0x8a8 */
2209 uint16 MHP_Addr3_L; /* 0x8aa */
2210 uint16 MHP_Addr4_H; /* 0x8ac */
2211 uint16 MHP_Addr4_M; /* 0x8ae */
2212 uint16 MHP_Addr4_L; /* 0x8b0 */
2213 uint16 MHP_CFC; /* 0x8b2 */
2214 uint16 PAD[6]; /* 0x8b4 - 0x8c0 */
2215 uint16 DAGG_CTL2; /* 0x8c0 */
2216 uint16 DAGG_BYTESLEFT; /* 0x8c2 */
2217 uint16 DAGG_SH_OFFSET; /* 0x8c4 */
2218 uint16 DAGG_STAT; /* 0x8c6 */
2219 uint16 DAGG_LEN; /* 0x8c8 */
2220 uint16 TXBA_CTL; /* 0x8ca */
2221 uint16 TXBA_DataSel; /* 0x8cc */
2222 uint16 TXBA_Data; /* 0x8ce */
2223 uint16 PAD[8]; /* 0x8d0 - 0x8e0 */
2224 uint16 AMT_CTL; /* 0x8e0 */
2225 uint16 AMT_Status; /* 0x8e2 */
2226 uint16 AMT_Limit; /* 0x8e4 */
2227 uint16 AMT_Attr; /* 0x8e6 */
2228 uint16 AMT_Match1; /* 0x8e8 */
2229 uint16 AMT_Match2; /* 0x8ea */
2230 uint16 AMT_Table_Addr; /* 0x8ec */
2231 uint16 AMT_Table_Data; /* 0x8ee */
2232 uint16 AMT_Table_Val; /* 0x8f0 */
2233 uint16 AMT_DBG_SEL; /* 0x8f2 */
2234 uint16 PAD[6]; /* 0x8f4 - 0x900 */
2235 uint16 RoeCtrl; /* 0x900 */
2236 uint16 RoeStatus; /* 0x902 */
2237 uint16 RoeIPChkSum; /* 0x904 */
2238 uint16 RoeTCPUDPChkSum; /* 0x906 */
2239 uint16 PAD[12]; /* 0x908 - 0x920 */
2240 uint16 PSOCtl; /* 0x920 */
2241 uint16 PSORxWordsWatermark; /* 0x922 */
2242 uint16 PSORxCntWatermark; /* 0x924 */
2243 uint16 PAD[5]; /* 0x926 - 0x930 */
2244 uint16 OBFFCtl; /* 0x930 */
2245 uint16 OBFFRxWordsWatermark; /* 0x932 */
2246 uint16 OBFFRxCntWatermark; /* 0x934 */
2247 uint16 PAD[101]; /* 0x936 - 0xa00 */
2248  
2249 /* TOE */
2250 uint16 ToECTL; /* 0xa00 */
2251 uint16 ToERst; /* 0xa02 */
2252 uint16 ToECSumNZ; /* 0xa04 */
2253 uint16 PAD[29]; /* 0xa06 - 0xa40 */
2254  
2255 uint16 TxSerialCtl; /* 0xa40 */
2256 uint16 TxPlcpLSig0; /* 0xa42 */
2257 uint16 TxPlcpLSig1; /* 0xa44 */
2258 uint16 TxPlcpHtSig0; /* 0xa46 */
2259 uint16 TxPlcpHtSig1; /* 0xa48 */
2260 uint16 TxPlcpHtSig2; /* 0xa4a */
2261 uint16 TxPlcpVhtSigB0; /* 0xa4c */
2262 uint16 TxPlcpVhtSigB1; /* 0xa4e */
2263 uint16 PAD[1];
2264  
2265 uint16 MacHdrFromShmLen; /* 0xa52 */
2266 uint16 TxPlcpLen; /* 0xa54 */
2267 uint16 PAD[1];
2268  
2269 uint16 TxBFRptLen; /* 0xa58 */
2270 uint16 PAD[3];
2271  
2272 uint16 TXBFCtl; /* 0xa60 */
2273 uint16 BfmRptOffset; /* 0xa62 */
2274 uint16 BfmRptLen; /* 0xa64 */
2275 uint16 TXBFBfeRptRdCnt; /* 0xa66 */
2276 uint16 PAD[20]; /* 0xa68 - 0xa8e */
2277 uint16 psm_reg_mux; /* 0xa90 */
2278 uint16 PAD[7]; /* 0xa92 - 0xa9e */
2279 uint16 psm_base[14]; /* 0xaa0 - 0xaba */
2280 uint16 psm_base_x; /* 0xabc */
2281 uint16 PAD[33]; /* 0xabe - 0xafe */
2282 uint16 RXMapFifoSize; /* 0xb00 */
2283 uint16 RXMapStatus; /* 0xb02 */
2284 uint16 MsduThreshold; /* 0xb04 */
2285 uint16 PAD[4]; /* 0xb06 - 0xb0c */
2286 uint16 BMCCore0TXAllMaxBuffers; /* 0xb0e */
2287 uint16 BMCCore1TXAllMaxBuffers; /* 0xb10 */
2288 uint16 BMCDynAllocStatus1; /* 0xb12 */
2289  
2290 /* Corerev >= 50, empty otherwise */
2291 uint16 TXE_DMAMaxOutStBuffers; /* 0xb14 */
2292 uint16 TXE_SCS_MASK_L; /* 0xb16 - SampleCollectStoreMaskLo */
2293 uint16 TXE_SCS_MASK_H; /* 0xb18 - SampleCollectStoreMaskHi */
2294 uint16 TXE_SCM_MASK_L; /* 0xb1a - SampleCollectMatchMaskLo */
2295 uint16 TXE_SCM_MASK_H; /* 0xb1c - SampleCollectMatchMaskHi */
2296 uint16 TXE_SCM_VAL_L; /* 0xb1e - SampleCollectMatchValueLo */
2297 uint16 TXE_SCM_VAL_H; /* 0xb20 - SampleCollectMatchValueHi */
2298 uint16 TXE_SCT_MASK_L; /* 0xb22 - SampleCollectTriggerMaskLo */
2299 uint16 TXE_SCT_MASK_H; /* 0xb24 - SampleCollectTriggerMaskHi */
2300 uint16 TXE_SCT_VAL_L; /* 0xb26 - SampleCollectTriggerValueLo */
2301 uint16 TXE_SCT_VAL_H; /* 0xb28 - SampleCollectTriggerValueHi */
2302 uint16 TXE_SCX_MASK_L; /* 0xb2a - SampleCollectTransMaskLo */
2303 uint16 TXE_SCX_MASK_H; /* 0xb2c - SampleCollectTransMaskHi */
2304 /* End CoreRev >= 50 Block */
2305  
2306 uint16 SampleCollectPlayCtrl; /* 0xb2e */
2307 uint16 Core0BMCAllocStatusTID7; /* b30 */
2308 uint16 Core1BMCAllocStatusTID7; /* b32 */
2309 uint16 PAD[10]; /* 0xb34 - 0xb46 */
2310 uint16 SysMStartAddrHi; /* 0xb48 */
2311 uint16 SysMStartAddrLo; /* 0xb4a */
2312 uint16 PAD[12]; /* 0xb4c - 0xb62 */
2313  
2314 /* AQM block for corerev >= 64, empty otherwise */
2315 uint16 PAD[462]; /* 0xbfe b64 - 0xEFE */
2316 } d11acregs;
2317 } u;
2318 } __attribute__((packed));
2319  
2320 /* 11AC TX DMA buffer header */
2321 #define D11_PHY_HDR_LEN 6
2322 #define D11AC_TXH_NUM_RATES 4
2323 /* per rate info */
2324 typedef struct d11actxh_rate d11actxh_rate_t;
2325 struct d11actxh_rate {
2326 uint16 PhyTxControlWord_0; /* 0 - 1 */
2327 uint16 PhyTxControlWord_1; /* 2 - 3 */
2328 uint16 PhyTxControlWord_2; /* 4 - 5 */
2329 uint8 plcp[D11_PHY_HDR_LEN]; /* 6 - 11 */
2330 uint16 FbwInfo; /* 12 -13 */
2331 uint16 TxRate; /* 14 */
2332 uint16 RtsCtsControl; /* 16 */
2333 uint16 Bfm0; /* 18 */
2334 } __attribute__((packed));
2335  
2336 /* per packet info */
2337 typedef struct d11actxh_pkt d11actxh_pkt_t;
2338 struct d11actxh_pkt {
2339 /* Per pkt info */
2340 uint16 TSOInfo; /* 0 */
2341 uint16 MacTxControlLow; /* 2 */
2342 uint16 MacTxControlHigh; /* 4 */
2343 uint16 Chanspec; /* 6 */
2344 uint8 IVOffset; /* 8 */
2345 uint8 PktCacheLen; /* 9 */
2346 uint16 FrameLen; /* 10 */
2347 uint16 TxFrameID; /* 12 */
2348 uint16 Seq; /* 14 */
2349 uint16 Tstamp; /* 16 */
2350 uint16 TxStatus; /* 18 */
2351 } __attribute__((packed));
2352  
2353 /* Per cache info */
2354 typedef struct d11actxh_cache d11actxh_cache_t;
2355 struct d11actxh_cache {
2356 uint8 BssIdEncAlg; /* 0 */
2357 uint8 KeyIdx; /* 1 */
2358 uint8 PrimeMpduMax; /* 2 */
2359 uint8 FallbackMpduMax; /* 3 */
2360 uint16 AmpduDur; /* 4 - 5 */
2361 uint8 BAWin; /* 6 */
2362 uint8 MaxAggLen; /* 7 */
2363 uint8 TkipPH1Key[10]; /* 8 - 17 */
2364 uint8 TSCPN[6]; /* 18 - 23 */
2365 } __attribute__((packed));
2366  
2367 /* Long format tx descriptor */
2368 typedef struct d11actxh d11actxh_t;
2369 struct d11actxh {
2370 /* Per pkt info */
2371 d11actxh_pkt_t PktInfo; /* 0 - 19 */
2372 /* Per rate info */
2373 d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 20 - 99 */
2374 /* Per cache info */
2375 d11actxh_cache_t CacheInfo; /* 100 - 123 */
2376 } __attribute__((packed));
2377  
2378 typedef void (*to_fun_t)(void *arg);
2379  
2380 typedef struct _ctimeout {
2381 struct _ctimeout *next;
2382 uint32 ms;
2383 to_fun_t fun;
2384 void *arg;
2385 bool expired;
2386 } ctimeout_t;
2387  
2388 struct hndrte_timer
2389 {
2390 uint32 *context; /* first field so address of context is timer struct ptr */
2391 void *data;
2392 void (*mainfn)(struct hndrte_timer *);
2393 void (*auxfn)(void *context);
2394 ctimeout_t t;
2395 int interval;
2396 int set;
2397 int periodic;
2398 bool _freedone;
2399 } __attribute__((packed));
2400  
2401 /*== maccontrol register ==*/
2402 #define MCTL_GMODE (1U << 31)
2403 #define MCTL_DISCARD_PMQ (1 << 30)
2404 #define MCTL_WAKE (1 << 26)
2405 #define MCTL_HPS (1 << 25)
2406 #define MCTL_PROMISC (1 << 24)
2407 #define MCTL_KEEPBADFCS (1 << 23)
2408 #define MCTL_KEEPCONTROL (1 << 22)
2409 #define MCTL_PHYLOCK (1 << 21)
2410 #define MCTL_BCNS_PROMISC (1 << 20)
2411 #define MCTL_LOCK_RADIO (1 << 19)
2412 #define MCTL_AP (1 << 18)
2413 #define MCTL_INFRA (1 << 17)
2414 #define MCTL_BIGEND (1 << 16)
2415 #define MCTL_GPOUT_SEL_MASK (3 << 14)
2416 #define MCTL_GPOUT_SEL_SHIFT 14
2417 #define MCTL_EN_PSMDBG (1 << 13)
2418 #define MCTL_IHR_EN (1 << 10)
2419 #define MCTL_SHM_UPPER (1 << 9)
2420 #define MCTL_SHM_EN (1 << 8)
2421 #define MCTL_PSM_JMP_0 (1 << 2)
2422 #define MCTL_PSM_RUN (1 << 1)
2423 #define MCTL_EN_MAC (1 << 0)
2424  
2425 struct ethernet_header {
2426 uint8 dst[6];
2427 uint8 src[6];
2428 uint16 type;
2429 } __attribute__((packed));
2430  
2431 struct ipv6_header {
2432 uint32 version_traffic_class_flow_label;
2433 uint16 payload_length;
2434 uint8 next_header;
2435 uint8 hop_limit;
2436 uint8 src_ip[16];
2437 uint8 dst_ip[16];
2438 } __attribute__((packed));
2439  
2440 struct ip_header {
2441 uint8 version_ihl;
2442 uint8 dscp_ecn;
2443 uint16 total_length;
2444 uint16 identification;
2445 uint16 flags_fragment_offset;
2446 uint8 ttl;
2447 uint8 protocol;
2448 uint16 header_checksum;
2449 union {
2450 uint32 integer;
2451 uint8 array[4];
2452 } src_ip;
2453 union {
2454 uint32 integer;
2455 uint8 array[4];
2456 } dst_ip;
2457 } __attribute__((packed));
2458  
2459 struct udp_header {
2460 uint16 src_port;
2461 uint16 dst_port;
2462 union {
2463 uint16 length; /* UDP: length of UDP header and payload */
2464 uint16 checksum_coverage; /* UDPLITE: checksum_coverage */
2465 } len_chk_cov;
2466 uint16 checksum;
2467 } __attribute__((packed));
2468  
2469 struct ethernet_ip_udp_header {
2470 struct ethernet_header ethernet;
2471 struct ip_header ip;
2472 struct udp_header udp;
2473 } __attribute__((packed));
2474  
2475 struct ethernet_ipv6_udp_header {
2476 struct ethernet_header ethernet;
2477 struct ipv6_header ipv6;
2478 struct udp_header udp;
2479 uint8 payload[1];
2480 } __attribute__((packed));
2481  
2482 struct nexmon_header {
2483 uint32 hooked_fct;
2484 uint32 args[3];
2485 uint8 payload[1];
2486 } __attribute__((packed));
2487  
2488 #endif /*STRUCTS_COMMON_H */