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1 office 1 /***************************************************************************
2 * *
3 * ########### ########### ########## ########## *
4 * ############ ############ ############ ############ *
5 * ## ## ## ## ## ## ## *
6 * ## ## ## ## ## ## ## *
7 * ########### #### ###### ## ## ## ## ###### *
8 * ########### #### # ## ## ## ## # # *
9 * ## ## ###### ## ## ## ## # # *
10 * ## ## # ## ## ## ## # # *
11 * ############ ##### ###### ## ## ## ##### ###### *
12 * ########### ########### ## ## ## ########## *
13 * *
14 * S E C U R E M O B I L E N E T W O R K I N G *
15 * *
16 * This file is part of NexMon. *
17 * *
18 * Copyright (c) 2016 NexMon Team *
19 * *
20 * NexMon is free software: you can redistribute it and/or modify *
21 * it under the terms of the GNU General Public License as published by *
22 * the Free Software Foundation, either version 3 of the License, or *
23 * (at your option) any later version. *
24 * *
25 * NexMon is distributed in the hope that it will be useful, *
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
28 * GNU General Public License for more details. *
29 * *
30 * You should have received a copy of the GNU General Public License *
31 * along with NexMon. If not, see <http://www.gnu.org/licenses/>. *
32 * *
33 **************************************************************************/
34  
35 #ifndef STRUCTS_COMMON_H
36 #define STRUCTS_COMMON_H
37  
38 #include <types.h>
39 #include <bcmcdc.h>
40  
41 /* used for PAPD cal */
42 typedef struct _acphy_txgains {
43 uint16 txlpf;
44 uint16 txgm;
45 uint16 pga;
46 uint16 pad;
47 uint16 ipa;
48 } acphy_txgains_t;
49  
50 /* htphy: tx gain settings */
51 typedef struct {
52 uint16 rad_gain; /* Radio gains */
53 uint16 rad_gain_mi; /* Radio gains [16:31] */
54 uint16 rad_gain_hi; /* Radio gains [32:47] */
55 uint16 dac_gain; /* DAC attenuation */
56 uint16 bbmult; /* BBmult */
57 } txgain_setting_t;
58  
59 typedef struct { /* wlc_phy_write_tx_gain_acphy */
60 uint8 txlpf; /* Radio gains */
61 uint8 ipa;
62 uint8 pad; /* Radio gains [16:31] */
63 uint8 pga;
64 uint8 txgm; /* Radio gains [32:47] */
65 uint8 unknown;
66 uint16 dac_gain; /* DAC attenuation */
67 uint16 bbmult; /* BBmult */
68 } ac_txgain_setting_t;
69  
70 struct ratesel_txparams {
71 uint32 rspec[4];
72 uint8 antselid[4];
73 uint8 num;
74 };
75  
76 struct wl_rxsts {
77 uint32 pkterror; /* error flags per pkt */
78 uint32 phytype; /* 802.11 A/B/G ... */
79 uint16 chanspec; /* channel spec */
80 uint16 datarate; /* rate in 500kbps (0 for HT frame) */
81 uint8 mcs; /* MCS for HT frame */
82 uint8 htflags; /* HT modulation flags */
83 uint8 PAD;
84 uint8 PAD;
85 uint32 antenna; /* antenna pkts received on */
86 uint32 pktlength; /* pkt length minus bcm phy hdr */
87 uint32 mactime; /* time stamp from mac, count per 1us */
88 uint32 sq; /* signal quality */
89 int32 signal; /* in dBm */
90 int32 noise; /* in dBm */
91 uint32 preamble; /* Unknown, short, long */
92 uint32 encoding; /* Unknown, CCK, PBCC, OFDM, HT */
93 uint32 nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
94 void *wlif; /* wl interface */
95 uint8 nss; /* Number of spatial streams for VHT frame */
96 uint8 coding;
97 uint16 aid; /* Partial AID for VHT frame */
98 uint8 gid; /* Group ID for VHT frame */
99 uint8 bw; /* Bandwidth for VHT frame */
100 uint16 vhtflags; /* VHT modulation flags */
101 uint8 bw_nonht; /* non-HT bw advertised in rts/cts */
102 uint8 PAD;
103 uint8 PAD;
104 uint8 PAD;
105 uint32 ampdu_counter; /* AMPDU counter for sniffer */
106 } __attribute__((packed));
107  
108 /* status per error RX pkt */
109 #define WL_RXS_CRC_ERROR 0x00000001 /* CRC Error in packet */
110 #define WL_RXS_RUNT_ERROR 0x00000002 /* Runt packet */
111 #define WL_RXS_ALIGN_ERROR 0x00000004 /* Misaligned packet */
112 #define WL_RXS_OVERSIZE_ERROR 0x00000008 /* packet bigger than RX_LENGTH (usually 1518) */
113 #define WL_RXS_WEP_ICV_ERROR 0x00000010 /* Integrity Check Value error */
114 #define WL_RXS_WEP_ENCRYPTED 0x00000020 /* Encrypted with WEP */
115 #define WL_RXS_PLCP_SHORT 0x00000040 /* Short PLCP error */
116 #define WL_RXS_DECRYPT_ERR 0x00000080 /* Decryption error */
117 #define WL_RXS_OTHER_ERR 0x80000000 /* Other errors */
118  
119 /* phy type */
120 #define WL_RXS_PHY_A 0x00000000 /* A phy type */
121 #define WL_RXS_PHY_B 0x00000001 /* B phy type */
122 #define WL_RXS_PHY_G 0x00000002 /* G phy type */
123 #define WL_RXS_PHY_N 0x00000004 /* N phy type */
124  
125 /* encoding */
126 #define WL_RXS_ENCODING_UNKNOWN 0x00000000
127 #define WL_RXS_ENCODING_DSSS_CCK 0x00000001 /* DSSS/CCK encoding (1, 2, 5.5, 11) */
128 #define WL_RXS_ENCODING_OFDM 0x00000002 /* OFDM encoding */
129 #define WL_RXS_ENCODING_HT 0x00000003 /* HT encoding */
130 #define WL_RXS_ENCODING_AC 0x00000004 /* HT encoding */
131  
132 /* preamble */
133 #define WL_RXS_UNUSED_STUB 0x0 /* stub to match with wlc_ethereal.h */
134 #define WL_RXS_PREAMBLE_SHORT 0x00000001 /* Short preamble */
135 #define WL_RXS_PREAMBLE_LONG 0x00000002 /* Long preamble */
136 #define WL_RXS_PREAMBLE_HT_MM 0x00000003 /* HT mixed mode preamble */
137 #define WL_RXS_PREAMBLE_HT_GF 0x00000004 /* HT green field preamble */
138  
139 /* htflags */
140 #define WL_RXS_HTF_40 0x01
141 #define WL_RXS_HTF_20L 0x02
142 #define WL_RXS_HTF_20U 0x04
143 #define WL_RXS_HTF_SGI 0x08
144 #define WL_RXS_HTF_STBC_MASK 0x30
145 #define WL_RXS_HTF_STBC_SHIFT 4
146 #define WL_RXS_HTF_LDPC 0x40
147  
148 #define WL_RXS_NFRM_AMPDU_FIRST 0x00000001 /* first MPDU in A-MPDU */
149 #define WL_RXS_NFRM_AMPDU_SUB 0x00000002 /* subsequent MPDU(s) in A-MPDU */
150 #define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
151 #define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
152  
153 struct osl_info {
154 unsigned int pktalloced;
155 int PAD[1];
156 void *callback_when_dropped;
157 unsigned int bustype;
158 } __attribute__((packed));
159  
160 typedef struct sk_buff {
161 struct sk_buff *next; /* 0x00 */
162 struct sk_buff *prev; /* 0x04 */
163 void *head; /* 0x08 - head of buffer */
164 void *end; /* 0x0C - end of buffer */
165 void *data; /* 0x10 - data head pointer */
166 short len; /* 0x14 */
167 short prio; /* 0x16 */
168 short PAD; /* 0x18 */
169 short PAD; /* 0x1A */
170 int PAD; /* 0x1C */
171 int flags; /* 0x20 */
172 int PAD; /* 0x24 */
173 int PAD; /* 0x28 */
174 int lifetime_end; /* 0x2C */
175 void *scb; /* 0x30 */
176 uint32 rspec; // 0x34
177 } __attribute__((packed)) sk_buff;
178  
179 #define HNDRTE_DEV_NAME_MAX 16
180  
181 typedef struct hndrte_dev {
182 char name[HNDRTE_DEV_NAME_MAX];
183 struct hndrte_devfuncs *funcs;
184 uint32 devid;
185 void *softc; /* Software context */
186 uint32 flags; /* RTEDEVFLAG_XXXX */
187 struct hndrte_dev *next;
188 struct hndrte_dev *chained;
189 void *pdev;
190 } hndrte_dev;
191  
192 struct hndrte_devfuncs {
193 void *(*probe)(struct hndrte_dev *dev, void *regs, uint bus,
194 uint16 device, uint coreid, uint unit);
195 int (*open)(struct hndrte_dev *dev);
196 int (*close)(struct hndrte_dev *dev);
197 int (*xmit)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb);
198 int (*recv)(struct hndrte_dev *src, struct hndrte_dev *dev, void *pkt);
199 int (*ioctl)(struct hndrte_dev *dev, uint32 cmd, void *buffer, int len,
200 int *used, int *needed, int set);
201 void (*txflowcontrol) (struct hndrte_dev *dev, bool state, int prio);
202 void (*poll)(struct hndrte_dev *dev);
203 int (*xmit_ctl)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb);
204 int (*xmit2)(struct hndrte_dev *src, struct hndrte_dev *dev, void *lb, int8 ch);
205 };
206  
207 struct tunables {
208 char gap[62];
209 short somebnd; // @ 0x38
210 short rxbnd; // @ 0x40
211 };
212  
213 struct wlc_hwband {
214 int bandtype; /* 0x00 */
215 int bandunit; /* 0x04 */
216 char mhfs; /* 0x05 */
217 char PAD[10]; /* 0x06 */
218 char bandhw_stf_ss_mode; /* 0x13 */
219 short CWmin; /* 0x14 */
220 short CWmax; /* 0x16 */
221 int core_flags; /* 0x18 */
222 short phytype; /* 0x1C */
223 short phyrev; /* 0x1E */
224 short radioid; /* 0x20 */
225 short radiorev; /* 0x22 */
226 struct phy_info *pi; /* 0x24 */
227 char abgphy_encore; /* 0x25 */
228 };
229  
230 struct wlc_hw_info {
231 struct wlc_info *wlc; /* 0x00 */
232 int PAD; /* 0x04 */
233 int PAD; /* 0x08 */
234 int PAD; /* 0x0c */
235 int PAD; /* 0x10 */
236 struct dma_info *di[6]; /* 0x14 - only 4 bytes */
237 int PAD; // 0x2c
238 int PAD; // 0x30
239 int PAD; // 0x34
240 int PAD; // 0x38
241 int PAD; // 0x3c
242 int PAD; // 0x40
243 int PAD; // 0x44
244 int PAD; // 0x48
245 int PAD; // 0x4c
246 int PAD; // 0x50
247 int PAD; // 0x54
248 int PAD; // 0x58
249 int PAD; // 0x5c
250 int PAD; // 0x60
251 int PAD; // 0x64
252 int PAD; // 0x68
253 int PAD; // 0x6c
254 char PAD; // 0x70
255 char PAD; // 0x71
256 char ucode_loaded; // 0x72
257 char PAD; // 0x73
258 int PAD; // 0x74
259 int sih; /* 0x78 */
260 int vars; /* 0x7C */
261 int vars_size; /* 0x80 */
262 struct d11regs* regs; /* 0x84 */
263 int physhim; /* 0x88 */
264 int phy_sh; /* 0x8C */
265 struct wlc_hwband *band; /* 0x90 */
266 int PAD; // 0x94
267 int PAD; // 0x98
268 int PAD; // 0x9c
269 int PAD; // 0xa0
270 int PAD; // 0xa4
271 char up; // 0xa8
272 char PAD;
273 char PAD;
274 char PAD;
275 int PAD; // 0xac
276 int PAD; // 0xb0
277 int PAD; // 0xb4
278 int PAD; // 0xb8
279 int PAD; // 0xbc
280 int PAD; // 0xc0
281 int PAD; // 0xc4
282 int PAD; // 0xc8
283 int PAD; // 0xcc
284 int PAD; // 0xd0
285 int PAD; // 0xd4
286 int PAD; // 0xd8
287 int PAD; // 0xdc
288 int PAD; // 0xe0
289 int PAD; // 0xe4
290 int maccontrol; // 0xe8
291 int PAD; // 0xec
292 int PAD; // 0xf0
293 int PAD; // 0xf4
294 char etheraddr[6]; // 0xf8
295 short PAD; // 0xfe
296 int PAD[18];
297 sk_buff *some_skbuff_ptr;
298  
299 };
300  
301 /**
302 * Name might be inaccurate
303 */
304 struct wl_info {
305 int unit; // 0x00
306 void *pub; // 0x04
307 struct wlc_info *wlc; // 0x08
308 struct wlc_hw_info *wlc_hw; // 0x0c
309 struct hndrte_dev *dev; // 0x10
310 int PAD; // 0x14
311 int PAD; // 0x18
312 int PAD; // 0x1c
313 int PAD; // 0x20
314 int PAD; // 0x24
315 int PAD; // 0x28
316 int PAD; // 0x2c
317 int PAD; // 0x30
318 int PAD; // 0x34
319 int PAD; // 0x38
320 int PAD; // 0x3c
321 struct hndrte_timer *dpcTimer; // 0x40
322 };
323  
324 /**
325 * Name might be inaccurate
326 */
327 struct sdiox_info {
328 int unit;
329 void *something;
330 void *sdio; // sdio_info struct
331 void *osh;
332 void *device_address;
333 } __attribute__((packed));
334  
335 struct shared_phy {
336 struct phy_info *phy_head; // 0x000 /* head of phy list */
337 uint unit; // 0x004 /* device instance number */
338 struct osl_info *osh; // 0x008 /* pointer to os handle */
339 void *sih; // 0x00c /* si handle (cookie for siutils calls) */
340 void *physhim; // 0x010 /* phy <-> wl shim layer for wlapi */
341 uint corerev; // 0x014 /* d11corerev, shadow of wlc_hw->corerev */
342 uint32 machwcap; // 0x018 /* mac hw capability */
343 bool up; // 0x01c /* main driver is up and running */
344 bool clk; // 0x01d /* main driver make the clk available */
345 uint8 PAD; // 0x01e
346 uint8 PAD; // 0x01f
347 uint32 PAD; // 0x020
348 uint32 PAD; // 0x024
349 uint32 PAD; // 0x028
350 uint32 PAD; // 0x02C
351 uint32 PAD; // 0x030
352 uint32 PAD; // 0x034
353 uint32 PAD; // 0x038
354 uint32 PAD; // 0x03C
355 uint32 PAD; // 0x040
356 uint32 PAD; // 0x044
357 uint32 PAD; // 0x048
358 uint32 PAD; // 0x04C
359 uint32 PAD; // 0x050
360 uint32 PAD; // 0x054
361 uint32 PAD; // 0x058
362 uint32 PAD; // 0x05C
363 uint32 PAD; // 0x060
364 uint32 PAD; // 0x064
365 uint32 PAD; // 0x068
366 uint32 PAD; // 0x06C
367 uint32 PAD; // 0x070
368 uint32 PAD; // 0x074
369 uint32 PAD; // 0x078
370 uint32 PAD; // 0x07C
371 uint32 PAD; // 0x080
372 uint32 PAD; // 0x084
373 uint32 PAD; // 0x088
374 uint32 PAD; // 0x08C
375 uint8 PAD; // 0x090
376 uint8 hw_phyrxchain; // 0x091
377 uint8 PAD; // 0x092
378 uint8 PAD; // 0x093
379 uint32 PAD; // 0x094
380 uint32 PAD; // 0x098
381 uint32 PAD; // 0x09C
382 } __attribute__((packed));
383  
384 struct phy_pub {
385 uint phy_type; /* PHY_TYPE_XX */
386 uint phy_rev; /* phy revision */
387 uint8 phy_corenum; /* number of cores */
388 uint16 radioid; /* radio id */
389 uint8 radiorev; /* radio revision */
390 uint8 radiover; /* radio version */
391 uint8 radiomajorrev; /* radio major revision */
392 uint8 radiominorrev; /* radio minor revision */
393 uint coreflags; /* sbtml core/phy specific flags */
394 uint ana_rev; /* analog core revision */
395 bool abgphy_encore; /* true if chipset is encore enabled */
396 };
397  
398 struct phy_info_acphy {
399 uint8 dac_mode; // 0x000
400 uint8 PAD; // 0x001
401 uint16 bb_mult_save[1]; // 0x002
402 uint8 bb_mult_save_valid; // 0x004
403 uint8 PAD; // 0x005
404 uint16 deaf_count; // 0x006
405 uint32 PAD; // 0x008
406 uint32 PAD; // 0x00C
407 uint32 PAD; // 0x010
408 uint32 PAD; // 0x014
409 uint32 PAD; // 0x018
410 uint32 PAD; // 0x01C
411 int PAD; // 0x020
412 int PAD; // 0x024
413 int PAD; // 0x028
414 int PAD; // 0x02c
415 int PAD; // 0x030
416 int PAD; // 0x034
417 int PAD; // 0x038
418 int PAD; // 0x03c
419 int PAD; // 0x040
420 int PAD; // 0x044
421 int PAD; // 0x048
422 int PAD; // 0x04c
423 int PAD; // 0x050
424 int PAD; // 0x054
425 int PAD; // 0x058
426 int PAD; // 0x05c
427 int PAD; // 0x060
428 int PAD; // 0x064
429 int PAD; // 0x068
430 int PAD; // 0x06c
431 int PAD; // 0x070
432 int PAD; // 0x074
433 int PAD; // 0x078
434 int PAD; // 0x07c
435 int PAD; // 0x080
436 int PAD; // 0x084
437 int PAD; // 0x088
438 int PAD; // 0x08c
439 int PAD; // 0x090
440 int PAD; // 0x094
441 int PAD; // 0x098
442 int PAD; // 0x09c
443 int PAD; // 0x0a0
444 int PAD; // 0x0a4
445 int PAD; // 0x0a8
446 int PAD; // 0x0ac
447 int PAD; // 0x0b0
448 int PAD; // 0x0b4
449 int PAD; // 0x0b8
450 int PAD; // 0x0bc
451 int PAD; // 0x0c0
452 int PAD; // 0x0c4
453 int PAD; // 0x0c8
454 int PAD; // 0x0cc
455 int PAD; // 0x0d0
456 int PAD; // 0x0d4
457 int PAD; // 0x0d8
458 int PAD; // 0x0dc
459 int PAD; // 0x0e0
460 int PAD; // 0x0e4
461 int PAD; // 0x0e8
462 int PAD; // 0x0ec
463 int PAD; // 0x0f0
464 int PAD; // 0x0f4
465 int PAD; // 0x0f8
466 int PAD; // 0x0fc
467 int PAD; // 0x100
468 int PAD; // 0x104
469 int PAD; // 0x108
470 int PAD; // 0x10c
471 int PAD; // 0x110
472 int PAD; // 0x114
473 int PAD; // 0x118
474 int PAD; // 0x11c
475 int PAD; // 0x120
476 int PAD; // 0x124
477 int PAD; // 0x128
478 int PAD; // 0x12c
479 int PAD; // 0x130
480 int PAD; // 0x134
481 int PAD; // 0x138
482 int PAD; // 0x13c
483 int PAD; // 0x140
484 int PAD; // 0x144
485 int PAD; // 0x148
486 int PAD; // 0x14c
487 int PAD; // 0x150
488 int PAD; // 0x154
489 int PAD; // 0x158
490 int PAD; // 0x15c
491 int PAD; // 0x160
492 int PAD; // 0x164
493 int PAD; // 0x168
494 int PAD; // 0x16c
495 int PAD; // 0x170
496 int PAD; // 0x174
497 int PAD; // 0x178
498 int PAD; // 0x17c
499 int PAD; // 0x180
500 int PAD; // 0x184
501 int PAD; // 0x188
502 int PAD; // 0x18c
503 int PAD; // 0x190
504 int PAD; // 0x194
505 int PAD; // 0x198
506 int PAD; // 0x19c
507 int PAD; // 0x1a0
508 int PAD; // 0x1a4
509 int PAD; // 0x1a8
510 int PAD; // 0x1ac
511 int PAD; // 0x1b0
512 int PAD; // 0x1b4
513 int PAD; // 0x1b8
514 int PAD; // 0x1bc
515 int PAD; // 0x1c0
516 int PAD; // 0x1c4
517 int PAD; // 0x1c8
518 int PAD; // 0x1cc
519 int PAD; // 0x1d0
520 int PAD; // 0x1d4
521 int PAD; // 0x1d8
522 int PAD; // 0x1dc
523 int PAD; // 0x1e0
524 int PAD; // 0x1e4
525 int PAD; // 0x1e8
526 int16 idle_tssi[1]; // 0x1ec
527 } __attribute__((packed));
528  
529 struct phy_info {
530 struct phy_pub pubpi_ro; // 0x000
531 struct shared_phy *sh; // 0x01c
532 int PAD; // 0x020
533 int PAD; // 0x024
534 int PAD; // 0x028
535 int PAD; // 0x02c
536 int PAD; // 0x030
537 int PAD; // 0x034
538 int PAD; // 0x038
539 int PAD; // 0x03c
540 int PAD; // 0x040
541 int PAD; // 0x044
542 int PAD; // 0x048
543 int PAD; // 0x04c
544 int PAD; // 0x050
545 int PAD; // 0x054
546 int PAD; // 0x058
547 int PAD; // 0x05c
548 int PAD; // 0x060
549 int PAD; // 0x064
550 int PAD; // 0x068
551 int PAD; // 0x06c
552 int PAD; // 0x070
553 int PAD; // 0x074
554 int PAD; // 0x078
555 int PAD; // 0x07c
556 int PAD; // 0x080
557 int PAD; // 0x084
558 int PAD; // 0x088
559 int PAD; // 0x08c
560 int PAD; // 0x090
561 int PAD; // 0x094
562 int PAD; // 0x098
563 int PAD; // 0x09c
564 int PAD; // 0x0a0
565 int PAD; // 0x0a4
566 int PAD; // 0x0a8
567 int PAD; // 0x0ac
568 int PAD; // 0x0b0
569 int PAD; // 0x0b4
570 int PAD; // 0x0b8
571 struct phy_info_acphy *pi_ac; // 0x0bc
572 int PAD; // 0x0c0
573 struct d11regs *regs; // 0x0c4
574 int PAD; // 0x0c8
575 int PAD; // 0x0cc
576 struct phy_pub pubpi; // 0x0d0
577 short PAD; // 0x0ec
578 short radio_chanspec; // 0x0ee
579 short PAD; // 0x0f0
580 short bw; // 0x0f2
581 int PAD; // 0x0f4
582 int PAD; // 0x0f8
583 int PAD; // 0x0fc
584 int PAD; // 0x100
585 int PAD; // 0x104
586 int PAD; // 0x108
587 int PAD; // 0x10c
588 int PAD; // 0x110
589 int PAD; // 0x114
590 int PAD; // 0x118
591 int PAD; // 0x11c
592 int PAD; // 0x120
593 } __attribute__((packed));
594  
595 struct wlcband {
596 int bandtype; /* 0x000 */
597 int bandunit; /* 0x004 */
598 short phytype; /* 0x008 */
599 short phyrev; /* 0x00A */
600 short radioid; /* 0x00C */
601 short radiorev; /* 0x00E */
602 struct phy_info *pi; /* 0x010 */
603 char abgphy_encore; /* 0x014 */
604 char gmode; /* 0x015 */
605 char PAD; /* 0x016 */
606 char PAD; /* 0x017 */
607 void *hwrs_scb; /* 0x018 */
608 int PAD; // 0x01c
609 uint32 rspec_override_alt; // 0x020
610 uint32 mrspec_override_alt; // 0x024
611 int PAD; // 0x028
612 int PAD; // 0x02c
613 int PAD; // 0x030
614 int PAD; // 0x034
615 int PAD; // 0x038
616 int PAD; // 0x03c
617 int PAD; // 0x040
618 uint32 rspec_override; // 0x044
619 uint32 mrspec_override; // 0x048
620 int PAD; // 0x04c
621 int PAD; // 0x050
622 // int defrateset; /* 0x01C */
623 // int rspec_override; /* 0x020 */
624 // int mrspec_override; /* 0x024 */
625 // char band_stf_ss_mode; /* 0x028 */
626 // char band_stf_stbc_tx; /* 0x029 */
627 // int hw_rateset; /* 0x030 */
628 // char basic_rate; /* 0x034 */
629 } __attribute__((packed));
630  
631 struct wlc_stf {
632 int PAD; // 0x000
633 int PAD; // 0x004
634 int PAD; // 0x008
635 int PAD; // 0x00c
636 uint8 PAD; // 0x010
637 uint8 PAD; // 0x011
638 int8 ldpc; // 0x012
639 int8 ldpc_tx; // 0x013
640 int PAD; // 0x014
641 int PAD; // 0x018
642 int PAD; // 0x01c
643 int PAD; // 0x020
644 } __attribute__((packed));
645  
646 struct wlc_info {
647 struct wlc_pub *pub; /* 0x000 */
648 struct osl_info *osh; /* 0x004 */
649 struct wl_info *wl; /* 0x008 */
650 volatile struct d11regs *regs; /* 0x00C */
651 struct wlc_hw_info *hw; /* 0x010 */
652 int PAD; /* 0x014 */
653 char PAD; /* 0x018 */
654 char clk; /* 0x019 */
655 char PAD; /* 0x01A */
656 char PAD; /* 0x01B */
657 void *core; /* 0x01C */
658 struct wlcband *band; /* 0x020 */
659 int PAD; /* 0x024 */
660 struct wlcband *bandstate[2]; /* 0x028 */
661 int PAD; /* 0x030 */
662 int PAD; /* 0x034 */
663 int PAD; /* 0x038 */
664 int PAD; /* 0x03C */
665 int PAD; /* 0x040 */
666 int PAD; /* 0x044 */
667 int PAD; /* 0x048 */
668 int PAD; /* 0x04C */
669 int PAD; /* 0x050 */
670 int PAD; /* 0x054 */
671 int PAD; /* 0x058 */
672 int PAD; /* 0x05C */
673 int PAD; /* 0x060 */
674 int PAD; /* 0x064 */
675 int PAD; /* 0x068 */
676 int PAD; /* 0x06C */
677 int PAD; /* 0x070 */
678 int PAD; /* 0x074 */
679 int PAD; /* 0x078 */
680 int PAD; /* 0x07C */
681 int PAD; /* 0x080 */
682 int PAD; /* 0x084 */
683 int PAD; /* 0x088 */
684 int PAD; /* 0x08C */
685 int PAD; /* 0x090 */
686 int PAD; /* 0x094 */
687 int PAD; /* 0x098 */
688 int PAD; /* 0x09C */
689 int PAD; /* 0x0A0 */
690 int PAD; /* 0x0A4 */
691 int PAD; /* 0x0A8 */
692 int PAD; /* 0x0AC */
693 int PAD; /* 0x0B0 */
694 int PAD; /* 0x0B4 */
695 int PAD; /* 0x0B8 */
696 int PAD; /* 0x0BC */
697 int PAD; /* 0x0C0 */
698 int PAD; /* 0x0C4 */
699 int PAD; /* 0x0C8 */
700 int PAD; /* 0x0CC */
701 int PAD; /* 0x0D0 */
702 int PAD; /* 0x0D4 */
703 int PAD; /* 0x0D8 */
704 int PAD; /* 0x0DC */
705 int PAD; /* 0x0E0 */
706 int PAD; /* 0x0E4 */
707 int PAD; /* 0x0E8 */
708 int PAD; /* 0x0EC */
709 int PAD; /* 0x0F0 */
710 int PAD; /* 0x0F4 */
711 int PAD; /* 0x0F8 */
712 int PAD; /* 0x0FC */
713 int PAD; /* 0x100 */
714 int PAD; /* 0x104 */
715 int PAD; /* 0x108 */
716 int PAD; /* 0x10C */
717 int PAD; /* 0x110 */
718 int PAD; /* 0x114 */
719 int PAD; /* 0x118 */
720 int PAD; /* 0x11C */
721 int PAD; /* 0x120 */
722 int PAD; /* 0x124 */
723 int PAD; /* 0x128 */
724 int PAD; /* 0x12C */
725 int PAD; /* 0x130 */
726 void *ampdu_tx; /* 0x134 */
727 void *ampdu_rx; /* 0x138 */
728 int PAD; /* 0x13C */
729 int PAD; /* 0x140 */
730 int PAD; /* 0x144 */
731 int PAD; /* 0x148 */
732 int PAD; /* 0x14C */
733 int PAD; /* 0x150 */
734 int PAD; /* 0x154 */
735 int PAD; /* 0x158 */
736 void *cmi; /* 0x15C */
737 int PAD; /* 0x160 */
738 int PAD; /* 0x164 */
739 void *scan; /* 0x168 */
740 int PAD; /* 0x16C */
741 int PAD; /* 0x170 */
742 int PAD; /* 0x174 */
743 int PAD; /* 0x178 */
744 int PAD; /* 0x17C */
745 int PAD; /* 0x180 */
746 int PAD; /* 0x184 */
747 int PAD; /* 0x188 */
748 int PAD; /* 0x18C */
749 int PAD; /* 0x190 */
750 int PAD; /* 0x194 */
751 int PAD; /* 0x198 */
752 int PAD; /* 0x19C */
753 int PAD; /* 0x1A0 */
754 int PAD; /* 0x1A4 */
755 int PAD; /* 0x1A8 */
756 int PAD; /* 0x1AC */
757 int PAD; /* 0x1B0 */
758 int PAD; /* 0x1B4 */
759 int PAD; /* 0x1B8 */
760 int PAD; /* 0x1BC */
761 int PAD; /* 0x1C0 */
762 char perm_etheraddr[6]; /* 0x1C4 */
763 char bandlocked; /* 0x1CA */
764 char field_1CB; /* 0x1CB */
765 int PAD; /* 0x1CC */
766 char mpc; /* 0x1D0 */ /* enable minimum power consumption */
767 char mpc_out; /* 0x1D1 */ /* disable radio_mpc_disable for out */
768 char mpc_scan; /* 0x1D2 */ /* disable radio_mpc_disable for scan */
769 char mpc_join; /* 0x1D3 */ /* disable radio_mpc_disable for join */
770 char mpc_oidscan; /* 0x1D4 */ /* disable radio_mpc_disable for oid scan */
771 char mpc_oidjoin; /* 0x1D5 */ /* disable radio_mpc_disable for oid join */
772 char mpc_oidnettype; /* 0x1D6 */ /* disable radio_mpc_disable for oid network_type_in_use */
773 char mpc_dlycnt; /* 0x1D7 */ /* # of watchdog cnt before turn disable radio */
774 char mpc_offcnt; /* 0x1D8 */ /* # of watchdog cnt that radio is disabled */
775 char mpc_delay_off; /* 0x1D9 */ /* delay radio disable by # of watchdog cnt */
776 char PAD; /* 0x1DA */
777 char PAD; /* 0x1DB */
778 int PAD; /* 0x1DC */
779 int PAD; /* 0x1E0 */
780 int PAD; /* 0x1E4 */
781 int PAD; /* 0x1E8 */
782 int PAD; /* 0x1EC */
783 int PAD; /* 0x1F0 */
784 int PAD; /* 0x1F4 */
785 int monitor; /* 0x1F8 */
786 int bcnmisc_ibss; /* 0x1FC */
787 int bcnmisc_scan; /* 0x200 */
788 int bcnmisc_monitor; /* 0x204 */
789 int PAD; /* 0x208 */
790 int PAD; /* 0x20C */
791 int PAD; /* 0x210 */
792 int PAD; /* 0x214 */
793 int PAD; /* 0x218 */
794 int PAD; /* 0x21C */
795 int PAD; /* 0x220 */
796 int PAD; /* 0x224 */
797 short PAD; /* 0x228 */
798 short wme_dp; /* 0x22A */
799 int PAD; /* 0x22C */
800 int PAD; /* 0x230 */
801 int PAD; /* 0x234 */
802 int PAD; /* 0x238 */
803 int PAD; /* 0x23C */
804 int PAD; /* 0x240 */
805 int PAD; /* 0x244 */
806 int PAD; /* 0x248 */
807 unsigned short tx_prec_map; /* 0x24C */
808 short PAD; /* 0x24E */
809 int PAD; /* 0x250 */
810 int PAD; /* 0x254 */
811 int PAD; /* 0x258 */
812 int PAD; /* 0x25C */
813 int PAD; /* 0x260 */
814 int PAD; /* 0x264 */
815 int PAD; /* 0x268 */
816 int PAD; /* 0x26C */
817 int PAD; /* 0x270 */
818 int PAD; /* 0x274 */
819 int PAD; /* 0x278 */
820 int PAD; /* 0x27C */
821 int PAD; /* 0x280 */
822 int PAD; /* 0x284 */
823 int PAD; /* 0x288 */
824 int PAD; /* 0x28C */
825 int PAD; /* 0x290 */
826 int PAD; /* 0x294 */
827 int PAD; /* 0x298 */
828 int PAD; /* 0x29C */
829 int PAD; /* 0x2A0 */
830 int PAD; /* 0x2A4 */
831 int PAD; /* 0x2A8 */
832 int PAD; /* 0x2AC */
833 int PAD; /* 0x2B0 */
834 int PAD; /* 0x2B4 */
835 int PAD; /* 0x2B8 */
836 int PAD; /* 0x2BC */
837 int PAD; /* 0x2C0 */
838 int PAD; /* 0x2C4 */
839 int PAD; /* 0x2C8 */
840 int PAD; /* 0x2CC */
841 int PAD; /* 0x2D0 */
842 int PAD; /* 0x2D4 */
843 int PAD; /* 0x2D8 */
844 int PAD; /* 0x2DC */
845 int PAD; /* 0x2E0 */
846 int PAD; /* 0x2E4 */
847 int PAD; /* 0x2E8 */
848 int PAD; /* 0x2EC */
849 int PAD; /* 0x2F0 */
850 int PAD; /* 0x2F4 */
851 int PAD; /* 0x2F8 */
852 int PAD; /* 0x2FC */
853 int PAD; /* 0X300 */
854 int PAD; /* 0X304 */
855 int PAD; /* 0X308 */
856 int PAD; /* 0X30C */
857 int PAD; /* 0X310 */
858 int PAD; /* 0X314 */
859 int PAD; /* 0X318 */
860 int PAD; /* 0X31C */
861 int PAD; /* 0X320 */
862 int PAD; /* 0X324 */
863 int PAD; /* 0X328 */
864 int PAD; /* 0X32C */
865 int PAD; /* 0X330 */
866 int PAD; /* 0X334 */
867 int PAD; /* 0X338 */
868 void *scan_results; /* 0X33C */
869 int PAD; /* 0X340 */
870 void *custom_scan_results; /* 0X344 */
871 int PAD; /* 0X348 */
872 int PAD; /* 0X34C */
873 int PAD; /* 0X350 */
874 int PAD; /* 0X354 */
875 int PAD; /* 0X358 */
876 int PAD; /* 0X35C */
877 int PAD; /* 0X360 */
878 short *field_364; /* 0X364 */
879 int PAD; /* 0X368 */
880 int PAD; /* 0X36C */
881 int PAD; /* 0X370 */
882 int PAD; /* 0X374 */
883 int PAD; /* 0X378 */
884 int PAD; /* 0X37C */
885 int PAD; /* 0X380 */
886 int PAD; /* 0X384 */
887 int PAD; /* 0X388 */
888 int PAD; /* 0X38C */
889 int PAD; /* 0X390 */
890 int PAD; /* 0X394 */
891 int PAD; /* 0X398 */
892 int PAD; /* 0X39C */
893 int PAD; /* 0X3A0 */
894 int PAD; /* 0X3A4 */
895 int PAD; /* 0X3A8 */
896 int PAD; /* 0X3AC */
897 int PAD; /* 0X3B0 */
898 int PAD; /* 0X3B4 */
899 int PAD; /* 0X3B8 */
900 int PAD; /* 0X3BC */
901 int PAD; /* 0X3C0 */
902 int PAD; /* 0X3C4 */
903 int PAD; /* 0X3C8 */
904 int PAD; /* 0X3CC */
905 int PAD; /* 0X3D0 */
906 int PAD; /* 0X3D4 */
907 int PAD; /* 0X3D8 */
908 int PAD; /* 0X3DC */
909 int PAD; /* 0X3E0 */
910 int PAD; /* 0X3E4 */
911 int PAD; /* 0X3E8 */
912 int PAD; /* 0X3EC */
913 int PAD; /* 0X3F0 */
914 int PAD; /* 0X3F4 */
915 int PAD; /* 0X3F8 */
916 int PAD; /* 0X3FC */
917 int PAD; /* 0X400 */
918 int PAD; /* 0X404 */
919 int PAD; /* 0X408 */
920 int PAD; /* 0X40C */
921 int PAD; /* 0X410 */
922 int PAD; /* 0X414 */
923 int PAD; /* 0X418 */
924 int PAD; /* 0X41C */
925 int PAD; /* 0X420 */
926 int PAD; /* 0X424 */
927 int PAD; /* 0X428 */
928 int PAD; /* 0X42C */
929 int PAD; /* 0X430 */
930 int PAD; /* 0X434 */
931 int PAD; /* 0X438 */
932 int PAD; /* 0X43C */
933 int PAD; /* 0X440 */
934 int PAD; /* 0X444 */
935 int PAD; /* 0X448 */
936 int PAD; /* 0X44C */
937 int PAD; /* 0X450 */
938 int PAD; /* 0X454 */
939 int PAD; /* 0X458 */
940 int PAD; /* 0X45C */
941 int PAD; /* 0X460 */
942 int PAD; /* 0X464 */
943 int PAD; /* 0X468 */
944 int PAD; /* 0X46C */
945 int PAD; /* 0X470 */
946 int PAD; /* 0X474 */
947 int PAD; /* 0X478 */
948 int PAD; /* 0X47C */
949 int PAD; /* 0X480 */
950 int PAD; /* 0X484 */
951 int PAD; /* 0X488 */
952 int PAD; /* 0X48C */
953 int PAD; /* 0X490 */
954 int PAD; /* 0X494 */
955 int PAD; /* 0X498 */
956 int PAD; /* 0X49C */
957 struct wlc_stf *stf; /* 0X4A0 */
958 int PAD; /* 0X4A4 */
959 int PAD; /* 0X4A8 */
960 int PAD; /* 0X4AC */
961 int PAD; /* 0X4B0 */
962 int PAD; /* 0X4B4 */
963 int PAD; /* 0X4B8 */
964 int PAD; /* 0X4BC */
965 int PAD; /* 0X4C0 */
966 int PAD; /* 0X4C4 */
967 int PAD; /* 0X4C8 */
968 int PAD; /* 0X4CC */
969 int PAD; /* 0X4D0 */
970 int PAD; /* 0X4D4 */
971 int PAD; /* 0X4D8 */
972 int PAD; /* 0X4DC */
973 int PAD; /* 0X4E0 */
974 int PAD; /* 0X4E4 */
975 int PAD; /* 0X4E8 */
976 int PAD; /* 0X4EC */
977 int PAD; /* 0X4F0 */
978 int PAD; /* 0X4F4 */
979 int PAD; /* 0X4F8 */
980 int PAD; /* 0X4FC */
981 int PAD; /* 0X500 */
982 int PAD; /* 0X504 */
983 int PAD; /* 0X508 */
984 int PAD; /* 0X50C */
985 short some_chanspec; /* 0X510 */
986 short PAD; /* 0X512 */
987 int PAD; /* 0X514 */
988 int PAD; /* 0X518 */
989 int PAD; /* 0X51C */
990 int PAD; /* 0X520 */
991 int PAD; /* 0X524 */
992 int PAD; /* 0X528 */
993 int PAD; /* 0X52C */
994 int PAD; /* 0X530 */
995 int PAD; /* 0X534 */
996 int PAD; /* 0X538 */
997 int PAD; /* 0X53C */
998 int PAD; /* 0X540 */
999 int PAD; /* 0X544 */
1000 int PAD; /* 0X548 */
1001 int PAD; /* 0X54C */
1002 int PAD; /* 0X550 */
1003 int PAD; /* 0X554 */
1004 int PAD; /* 0X558 */
1005 int PAD; /* 0X55C */
1006 int PAD; /* 0X560 */
1007 int PAD; /* 0X564 */
1008 int PAD; /* 0X568 */
1009 int PAD; /* 0X56C */
1010 int PAD; /* 0X570 */
1011 int PAD; /* 0X574 */
1012 int PAD; /* 0X578 */
1013 int PAD; /* 0X57C */
1014 int PAD; /* 0X580 */
1015 int PAD; /* 0X584 */
1016 int PAD; /* 0X588 */
1017 int PAD; /* 0X58C */
1018 int PAD; /* 0X590 */
1019 int PAD; /* 0X594 */
1020 int PAD; /* 0X598 */
1021 int PAD; /* 0X59C */
1022 int PAD; /* 0X5A0 */
1023 int PAD; /* 0X5A4 */
1024 int PAD; /* 0X5A8 */
1025 int PAD; /* 0X5AC */
1026 int PAD; /* 0X5B0 */
1027 int PAD; /* 0X5B4 */
1028 int PAD; /* 0X5B8 */
1029 int PAD; /* 0X5BC */
1030 int PAD; /* 0X5C0 */
1031 int PAD; /* 0X5C4 */
1032 int PAD; /* 0X5C8 */
1033 int PAD; /* 0X5CC */
1034 int PAD; /* 0X5D0 */
1035 int PAD; /* 0X5D4 */
1036 int PAD; /* 0X5D8 */
1037 int PAD; /* 0X5DC */
1038 int PAD; /* 0X5E0 */
1039 int PAD; /* 0X5E4 */
1040 void *active_queue; /* 0X5E8 */
1041 int PAD; /* 0X5EC */
1042 int PAD; /* 0X5F0 */
1043 int PAD; /* 0X5F4 */
1044 int PAD; /* 0X5F8 */
1045 int PAD; /* 0X5FC */
1046 int PAD; /* 0X600 */
1047 int PAD; /* 0X604 */
1048 int PAD; /* 0X608 */
1049 int hwrxoff; /* 0X60C */
1050 int PAD; /* 0X610 */
1051 int PAD; /* 0X614 */
1052 int PAD; /* 0X618 */
1053 int PAD; /* 0X61C */
1054 int PAD; /* 0X620 */
1055 int PAD; /* 0X624 */
1056 int PAD; /* 0X628 */
1057 int PAD; /* 0X62C */
1058 int PAD; /* 0X630 */
1059 int PAD; /* 0X634 */
1060 int PAD; /* 0X638 */
1061 int PAD; /* 0X63C */
1062 int PAD; /* 0X640 */
1063 int PAD; /* 0X644 */
1064 int PAD; /* 0X648 */
1065 int PAD; /* 0X64C */
1066 int PAD; /* 0X650 */
1067 int PAD; /* 0X654 */
1068 int PAD; /* 0X658 */
1069 int PAD; /* 0X65C */
1070 int PAD; /* 0X660 */
1071 int PAD; /* 0X664 */
1072 int PAD; /* 0X668 */
1073 int PAD; /* 0X66C */
1074 int PAD; /* 0X670 */
1075 int PAD; /* 0X674 */
1076 int PAD; /* 0X678 */
1077 uint8 PAD; /* 0X67C */
1078 uint8 toe_bypass; /* 0X67D */
1079 uint8 toe_capable; /* 0X67E */
1080 uint8 PAD; /* 0X67F */
1081 int PAD; /* 0X680 */
1082 };
1083  
1084 // source of wl_cnt_t: http://svn.dd-wrt.com/browser/src/linux/universal/linux-3.10/brcm/arm/include/wlioctl.h?rev=23022
1085 #define NFIFO 6 /* # tx/rx fifopairs */
1086  
1087 #define WL_CNT_T_VERSION 9 /* current version of wl_cnt_t struct */
1088  
1089 typedef struct {
1090 uint16 version; /* see definition of WL_CNT_T_VERSION */
1091 uint16 length; /* length of entire structure */
1092  
1093 /* transmit stat counters */
1094 uint32 txframe; /* tx data frames */
1095 uint32 txbyte; /* tx data bytes */
1096 uint32 txretrans; /* tx mac retransmits */
1097 uint32 txerror; /* tx data errors (derived: sum of others) */
1098 uint32 txctl; /* tx management frames */
1099 uint32 txprshort; /* tx short preamble frames */
1100 uint32 txserr; /* tx status errors */
1101 uint32 txnobuf; /* tx out of buffers errors */
1102 uint32 txnoassoc; /* tx discard because we're not associated */
1103 uint32 txrunt; /* tx runt frames */
1104 uint32 txchit; /* tx header cache hit (fastpath) */
1105 uint32 txcmiss; /* tx header cache miss (slowpath) */
1106  
1107 /* transmit chip error counters */
1108 uint32 txuflo; /* tx fifo underflows */
1109 uint32 txphyerr; /* tx phy errors (indicated in tx status) */
1110 uint32 txphycrs;
1111  
1112 /* receive stat counters */
1113 uint32 rxframe; /* rx data frames */
1114 uint32 rxbyte; /* rx data bytes */
1115 uint32 rxerror; /* rx data errors (derived: sum of others) */
1116 uint32 rxctl; /* rx management frames */
1117 uint32 rxnobuf; /* rx out of buffers errors */
1118 uint32 rxnondata; /* rx non data frames in the data channel errors */
1119 uint32 rxbadds; /* rx bad DS errors */
1120 uint32 rxbadcm; /* rx bad control or management frames */
1121 uint32 rxfragerr; /* rx fragmentation errors */
1122 uint32 rxrunt; /* rx runt frames */
1123 uint32 rxgiant; /* rx giant frames */
1124 uint32 rxnoscb; /* rx no scb error */
1125 uint32 rxbadproto; /* rx invalid frames */
1126 uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac */
1127 uint32 rxbadda; /* rx frames tossed for invalid da */
1128 uint32 rxfilter; /* rx frames filtered out */
1129  
1130 /* receive chip error counters */
1131 uint32 rxoflo; /* rx fifo overflow errors */
1132 uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
1133  
1134 uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
1135 uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
1136 uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
1137  
1138 /* misc counters */
1139 uint32 dmade; /* tx/rx dma descriptor errors */
1140 uint32 dmada; /* tx/rx dma data errors */
1141 uint32 dmape; /* tx/rx dma descriptor protocol errors */
1142 uint32 reset; /* reset count */
1143 uint32 tbtt; /* cnts the TBTT int's */
1144 uint32 txdmawar;
1145 uint32 pkt_callback_reg_fail; /* callbacks register failure */
1146  
1147 /* MAC counters: 32-bit version of d11.h's macstat_t */
1148 uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
1149 * Control Management (includes retransmissions)
1150 */
1151 uint32 txrtsfrm; /* number of RTS sent out by the MAC */
1152 uint32 txctsfrm; /* number of CTS sent out by the MAC */
1153 uint32 txackfrm; /* number of ACK frames sent out */
1154 uint32 txdnlfrm; /* Not used */
1155 uint32 txbcnfrm; /* beacons transmitted */
1156 uint32 txfunfl[6]; /* per-fifo tx underflows */
1157 uint32 rxtoolate; /* receive too late */
1158 uint32 txfbw; /* transmit at fallback bw (dynamic bw) */
1159 uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS
1160 * or BCN)
1161 */
1162 uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
1163 * driver enqueued frames
1164 */
1165 uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
1166 uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
1167 uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
1168 * data/control/management
1169 */
1170 uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
1171 uint32 rxbadplcp; /* parity check of the PLCP header failed */
1172 uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
1173 uint32 rxstrt; /* Number of received frames with a good PLCP
1174 * (i.e. passing parity check)
1175 */
1176 uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
1177 uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
1178 uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
1179 uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
1180 uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS) */
1181 uint32 rxackucast; /* number of ucast ACKS received (good FCS) */
1182 uint32 rxdfrmocast; /* number of received DATA frames (good FCS and not matching RA) */
1183 uint32 rxmfrmocast; /* number of received MGMT frames (good FCS and not matching RA) */
1184 uint32 rxcfrmocast; /* number of received CNTRL frame (good FCS and not matching RA) */
1185 uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
1186 uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
1187 uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
1188 uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
1189 uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC
1190 * (unlikely to see these)
1191 */
1192 uint32 rxbeaconmbss; /* beacons received from member of BSS */
1193 uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from
1194 * other BSS (WDS FRAME)
1195 */
1196 uint32 rxbeaconobss; /* beacons received from other BSS */
1197 uint32 rxrsptmout; /* Number of response timeouts for transmitted frames
1198 * expecting a response
1199 */
1200 uint32 bcntxcancl; /* transmit beacons canceled due to receipt of beacon (IBSS) */
1201 uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
1202 uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
1203 uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
1204 uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
1205 uint32 pmqovfl; /* Number of PMQ overflows */
1206 uint32 rxcgprqfrm; /* Number of received Probe requests that made it into
1207 * the PRQ fifo
1208 */
1209 uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
1210 uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did
1211 * not get ACK
1212 */
1213 uint32 txcgprssuc; /* Tx Probe Response Success (ACK was received) */
1214 uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ
1215 * fifo because a probe response could not be sent out within
1216 * the time limit defined in M_PRS_MAXTIME
1217 */
1218 uint32 rxnack; /* obsolete */
1219 uint32 frmscons; /* obsolete */
1220 uint32 txnack; /* obsolete */
1221 uint32 rxback; /* blockack rxcnt */
1222 uint32 txback; /* blockack txcnt */
1223  
1224 /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
1225 uint32 txfrag; /* dot11TransmittedFragmentCount */
1226 uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
1227 uint32 txfail; /* dot11FailedCount */
1228 uint32 txretry; /* dot11RetryCount */
1229 uint32 txretrie; /* dot11MultipleRetryCount */
1230 uint32 rxdup; /* dot11FrameduplicateCount */
1231 uint32 txrts; /* dot11RTSSuccessCount */
1232 uint32 txnocts; /* dot11RTSFailureCount */
1233 uint32 txnoack; /* dot11ACKFailureCount */
1234 uint32 rxfrag; /* dot11ReceivedFragmentCount */
1235 uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
1236 uint32 rxcrc; /* dot11FCSErrorCount */
1237 uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
1238 uint32 rxundec; /* dot11WEPUndecryptableCount */
1239  
1240 /* WPA2 counters (see rxundec for DecryptFailureCount) */
1241 uint32 tkipmicfaill; /* TKIPLocalMICFailures */
1242 uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
1243 uint32 tkipreplay; /* TKIPReplays */
1244 uint32 ccmpfmterr; /* CCMPFormatErrors */
1245 uint32 ccmpreplay; /* CCMPReplays */
1246 uint32 ccmpundec; /* CCMPDecryptErrors */
1247 uint32 fourwayfail; /* FourWayHandshakeFailures */
1248 uint32 wepundec; /* dot11WEPUndecryptableCount */
1249 uint32 wepicverr; /* dot11WEPICVErrorCount */
1250 uint32 decsuccess; /* DecryptSuccessCount */
1251 uint32 tkipicverr; /* TKIPICVErrorCount */
1252 uint32 wepexcluded; /* dot11WEPExcludedCount */
1253  
1254 uint32 txchanrej; /* Tx frames suppressed due to channel rejection */
1255 uint32 psmwds; /* Count PSM watchdogs */
1256 uint32 phywatchdog; /* Count Phy watchdogs (triggered by ucode) */
1257  
1258 /* MBSS counters, AP only */
1259 uint32 prq_entries_handled; /* PRQ entries read in */
1260 uint32 prq_undirected_entries; /* which were bcast bss & ssid */
1261 uint32 prq_bad_entries; /* which could not be translated to info */
1262 uint32 atim_suppress_count; /* TX suppressions on ATIM fifo */
1263 uint32 bcn_template_not_ready; /* Template marked in use on send bcn ... */
1264 uint32 bcn_template_not_ready_done; /* ...but "DMA done" interrupt rcvd */
1265 uint32 late_tbtt_dpc; /* TBTT DPC did not happen in time */
1266  
1267 /* per-rate receive stat counters */
1268 uint32 rx1mbps; /* packets rx at 1Mbps */
1269 uint32 rx2mbps; /* packets rx at 2Mbps */
1270 uint32 rx5mbps5; /* packets rx at 5.5Mbps */
1271 uint32 rx6mbps; /* packets rx at 6Mbps */
1272 uint32 rx9mbps; /* packets rx at 9Mbps */
1273 uint32 rx11mbps; /* packets rx at 11Mbps */
1274 uint32 rx12mbps; /* packets rx at 12Mbps */
1275 uint32 rx18mbps; /* packets rx at 18Mbps */
1276 uint32 rx24mbps; /* packets rx at 24Mbps */
1277 uint32 rx36mbps; /* packets rx at 36Mbps */
1278 uint32 rx48mbps; /* packets rx at 48Mbps */
1279 uint32 rx54mbps; /* packets rx at 54Mbps */
1280 uint32 rx108mbps; /* packets rx at 108mbps */
1281 uint32 rx162mbps; /* packets rx at 162mbps */
1282 uint32 rx216mbps; /* packets rx at 216 mbps */
1283 uint32 rx270mbps; /* packets rx at 270 mbps */
1284 uint32 rx324mbps; /* packets rx at 324 mbps */
1285 uint32 rx378mbps; /* packets rx at 378 mbps */
1286 uint32 rx432mbps; /* packets rx at 432 mbps */
1287 uint32 rx486mbps; /* packets rx at 486 mbps */
1288 uint32 rx540mbps; /* packets rx at 540 mbps */
1289  
1290 /* pkteng rx frame stats */
1291 uint32 pktengrxducast; /* unicast frames rxed by the pkteng code */
1292 uint32 pktengrxdmcast; /* multicast frames rxed by the pkteng code */
1293  
1294 uint32 rfdisable; /* count of radio disables */
1295 uint32 bphy_rxcrsglitch; /* PHY count of bphy glitches */
1296 uint32 bphy_badplcp;
1297  
1298 uint32 txexptime; /* Tx frames suppressed due to timer expiration */
1299  
1300 uint32 txmpdu_sgi; /* count for sgi transmit */
1301 uint32 rxmpdu_sgi; /* count for sgi received */
1302 uint32 txmpdu_stbc; /* count for stbc transmit */
1303 uint32 rxmpdu_stbc; /* count for stbc received */
1304  
1305 uint32 rxundec_mcst; /* dot11WEPUndecryptableCount */
1306  
1307 /* WPA2 counters (see rxundec for DecryptFailureCount) */
1308 uint32 tkipmicfaill_mcst; /* TKIPLocalMICFailures */
1309 uint32 tkipcntrmsr_mcst; /* TKIPCounterMeasuresInvoked */
1310 uint32 tkipreplay_mcst; /* TKIPReplays */
1311 uint32 ccmpfmterr_mcst; /* CCMPFormatErrors */
1312 uint32 ccmpreplay_mcst; /* CCMPReplays */
1313 uint32 ccmpundec_mcst; /* CCMPDecryptErrors */
1314 uint32 fourwayfail_mcst; /* FourWayHandshakeFailures */
1315 uint32 wepundec_mcst; /* dot11WEPUndecryptableCount */
1316 uint32 wepicverr_mcst; /* dot11WEPICVErrorCount */
1317 uint32 decsuccess_mcst; /* DecryptSuccessCount */
1318 uint32 tkipicverr_mcst; /* TKIPICVErrorCount */
1319 uint32 wepexcluded_mcst; /* dot11WEPExcludedCount */
1320  
1321 uint32 dma_hang; /* count for dma hang */
1322 uint32 reinit; /* count for reinit */
1323  
1324 uint32 pstatxucast; /* count of ucast frames xmitted on all psta assoc */
1325 uint32 pstatxnoassoc; /* count of txnoassoc frames xmitted on all psta assoc */
1326 uint32 pstarxucast; /* count of ucast frames received on all psta assoc */
1327 uint32 pstarxbcmc; /* count of bcmc frames received on all psta */
1328 uint32 pstatxbcmc; /* count of bcmc frames transmitted on all psta */
1329  
1330 uint32 cso_passthrough; /* hw cso required but passthrough */
1331 uint32 cso_normal; /* hw cso hdr for normal process */
1332 uint32 chained; /* number of frames chained */
1333 uint32 chainedsz1; /* number of chain size 1 frames */
1334 uint32 unchained; /* number of frames not chained */
1335 uint32 maxchainsz; /* max chain size so far */
1336 uint32 currchainsz; /* current chain size */
1337 uint32 rxdrop20s; /* drop secondary cnt */
1338 uint32 pciereset; /* Secondary Bus Reset issued by driver */
1339 uint32 cfgrestore; /* configspace restore by driver */
1340 } wl_cnt_t;
1341  
1342 struct wlc_pub {
1343 struct wlc_info *wlc; /* 0x000 */
1344 char cur_etheraddr[6]; /* 0x004 */
1345 short PAD; /* 0x00A */
1346 int PAD; /* 0x00C */
1347 int PAD; /* 0x010 */
1348 int osh; /* 0x014 */
1349 int PAD; /* 0x018 */
1350 int PAD; /* 0x01C */
1351 int PAD; /* 0x020 */
1352 char up_maybe; /* 0x024 */
1353 char field_25; /* 0x025 */
1354 char field_26; /* 0x026 */
1355 char field_27; /* 0x027 */
1356 struct tunables *tunables; /* 0x028 */
1357 int PAD; /* 0x02C */
1358 int field_30; /* 0x030 */
1359 int PAD; /* 0x034 */
1360 int PAD; /* 0x038 */
1361 int PAD; /* 0x03C */
1362 int PAD; /* 0x040 */
1363 char PAD; /* 0x044 */
1364 char PAD; /* 0x045 */
1365 char field_46; /* 0x046 */
1366 char PAD; /* 0x047 */
1367 int PAD; /* 0x048 */
1368 char associated; /* 0x04C */
1369 char PAD; /* 0x04D */
1370 char PAD; /* 0x04E */
1371 bool _ampdu_tx; /* 0x04F */
1372 bool _ampdu_rx; /* 0x050 */
1373 bool _amsdu_tx; /* 0x051 */
1374 bool PAD; /* 0x052 */
1375 bool PAD; /* 0x053 */
1376 int PAD; /* 0x054 */
1377 int PAD; /* 0x058 */
1378 int PAD; /* 0x05C */
1379 int PAD; /* 0x060 */
1380 int PAD; /* 0x064 */
1381 int PAD; /* 0x068 */
1382 int PAD; /* 0x06C */
1383 int PAD; /* 0x070 */
1384 int PAD; /* 0x074 */
1385 int PAD; /* 0x078 */
1386 int PAD; /* 0x07C */
1387 int PAD; /* 0x080 */
1388 int PAD; /* 0x084 */
1389 int PAD; /* 0x088 */
1390 int PAD; /* 0x08C */
1391 int PAD; /* 0x090 */
1392 wl_cnt_t *_cnt; /* 0x094 */
1393 int PAD; /* 0x098 */
1394 int PAD; /* 0x09C */
1395 int PAD; /* 0x0A0 */
1396 int PAD; /* 0x0A4 */
1397 int PAD; /* 0x0A8 */
1398 int PAD; /* 0x0AC */
1399 int PAD; /* 0x0B0 */
1400 int PAD; /* 0x0B4 */
1401 char gap2[47];
1402 char is_amsdu; // @ 0xe7
1403 } __attribute__((packed));
1404  
1405 struct wlc_bsscfg {
1406 void *wlc; /* 0x000 */
1407 char associated; /* 0x004 */
1408 char PAD; /* 0x005 */
1409 char PAD; /* 0x006 */
1410 char PAD; /* 0x007 */
1411 int PAD; /* 0x008 */
1412 int PAD; /* 0x00C */
1413 int PAD; /* 0x010 */
1414 int PAD; /* 0x014 */
1415 int PAD; /* 0x018 */
1416 int PAD; /* 0x01C */
1417 int PAD; /* 0x020 */
1418 int PAD; /* 0x024 */
1419 int PAD; /* 0x028 */
1420 int PAD; /* 0x02C */
1421 int PAD; /* 0x030 */
1422 int PAD; /* 0x034 */
1423 int PAD; /* 0x038 */
1424 int PAD; /* 0x03C */
1425 int PAD; /* 0x040 */
1426 int PAD; /* 0x044 */
1427 int PAD; /* 0x048 */
1428 int PAD; /* 0x04C */
1429 int PAD; /* 0x050 */
1430 int PAD; /* 0x054 */
1431 int PAD; /* 0x058 */
1432 int PAD; /* 0x05C */
1433 int PAD; /* 0x060 */
1434 int PAD; /* 0x064 */
1435 int PAD; /* 0x068 */
1436 int PAD; /* 0x06C */
1437 int PAD; /* 0x070 */
1438 int PAD; /* 0x074 */
1439 int PAD; /* 0x078 */
1440 int PAD; /* 0x07C */
1441 int PAD; /* 0x080 */
1442 int PAD; /* 0x084 */
1443 int PAD; /* 0x088 */
1444 int PAD; /* 0x08C */
1445 int PAD; /* 0x090 */
1446 int PAD; /* 0x094 */
1447 int PAD; /* 0x098 */
1448 int PAD; /* 0x09C */
1449 int PAD; /* 0x0A0 */
1450 int PAD; /* 0x0A4 */
1451 int PAD; /* 0x0A8 */
1452 int PAD; /* 0x0AC */
1453 int PAD; /* 0x0B0 */
1454 int PAD; /* 0x0B4 */
1455 int PAD; /* 0x0B8 */
1456 int PAD; /* 0x0BC */
1457 int PAD; /* 0x0C0 */
1458 int PAD; /* 0x0C4 */
1459 int PAD; /* 0x0C8 */
1460 int PAD; /* 0x0CC */
1461 int PAD; /* 0x0D0 */
1462 int PAD; /* 0x0D4 */
1463 int PAD; /* 0x0D8 */
1464 int PAD; /* 0x0DC */
1465 int PAD; /* 0x0E0 */
1466 int PAD; /* 0x0E4 */
1467 int PAD; /* 0x0E8 */
1468 int PAD; /* 0x0EC */
1469 int PAD; /* 0x0F0 */
1470 int PAD; /* 0x0F4 */
1471 int PAD; /* 0x0F8 */
1472 int PAD; /* 0x0FC */
1473 int PAD; /* 0x100 */
1474 int PAD; /* 0x104 */
1475 int PAD; /* 0x108 */
1476 int PAD; /* 0x10C */
1477 int PAD; /* 0x110 */
1478 int PAD; /* 0x114 */
1479 int PAD; /* 0x118 */
1480 int PAD; /* 0x11C */
1481 int PAD; /* 0x120 */
1482 int PAD; /* 0x124 */
1483 int PAD; /* 0x128 */
1484 int PAD; /* 0x12C */
1485 int PAD; /* 0x130 */
1486 int PAD; /* 0x134 */
1487 int PAD; /* 0x138 */
1488 int PAD; /* 0x13C */
1489 int PAD; /* 0x140 */
1490 int PAD; /* 0x144 */
1491 int PAD; /* 0x148 */
1492 int PAD; /* 0x14C */
1493 int PAD; /* 0x150 */
1494 int PAD; /* 0x154 */
1495 int PAD; /* 0x158 */
1496 int PAD; /* 0x15C */
1497 int PAD; /* 0x160 */
1498 int PAD; /* 0x164 */
1499 int PAD; /* 0x168 */
1500 int PAD; /* 0x16C */
1501 int PAD; /* 0x170 */
1502 int PAD; /* 0x174 */
1503 int PAD; /* 0x178 */
1504 int PAD; /* 0x17C */
1505 int PAD; /* 0x180 */
1506 int PAD; /* 0x184 */
1507 int PAD; /* 0x188 */
1508 int PAD; /* 0x18C */
1509 int PAD; /* 0x190 */
1510 int PAD; /* 0x194 */
1511 int PAD; /* 0x198 */
1512 int PAD; /* 0x19C */
1513 int PAD; /* 0x1A0 */
1514 int PAD; /* 0x1A4 */
1515 int PAD; /* 0x1A8 */
1516 int PAD; /* 0x1AC */
1517 int PAD; /* 0x1B0 */
1518 int PAD; /* 0x1B4 */
1519 int PAD; /* 0x1B8 */
1520 int PAD; /* 0x1BC */
1521 int PAD; /* 0x1C0 */
1522 int PAD; /* 0x1C4 */
1523 int PAD; /* 0x1C8 */
1524 int PAD; /* 0x1CC */
1525 int PAD; /* 0x1D0 */
1526 int PAD; /* 0x1D4 */
1527 int PAD; /* 0x1D8 */
1528 int PAD; /* 0x1DC */
1529 int PAD; /* 0x1E0 */
1530 int PAD; /* 0x1E4 */
1531 int PAD; /* 0x1E8 */
1532 int PAD; /* 0x1EC */
1533 int PAD; /* 0x1F0 */
1534 int PAD; /* 0x1F4 */
1535 int PAD; /* 0x1F8 */
1536 int PAD; /* 0x1FC */
1537 int PAD; /* 0x200 */
1538 int PAD; /* 0x204 */
1539 int PAD; /* 0x208 */
1540 int PAD; /* 0x20C */
1541 int PAD; /* 0x210 */
1542 int PAD; /* 0x214 */
1543 int PAD; /* 0x218 */
1544 int PAD; /* 0x21C */
1545 int PAD; /* 0x220 */
1546 int PAD; /* 0x224 */
1547 int PAD; /* 0x228 */
1548 int PAD; /* 0x22C */
1549 int PAD; /* 0x230 */
1550 int PAD; /* 0x234 */
1551 int PAD; /* 0x238 */
1552 int PAD; /* 0x23C */
1553 int PAD; /* 0x240 */
1554 int PAD; /* 0x244 */
1555 int PAD; /* 0x248 */
1556 int PAD; /* 0x24C */
1557 int PAD; /* 0x250 */
1558 int PAD; /* 0x254 */
1559 int PAD; /* 0x258 */
1560 int PAD; /* 0x25C */
1561 int PAD; /* 0x260 */
1562 int PAD; /* 0x264 */
1563 int PAD; /* 0x268 */
1564 int PAD; /* 0x26C */
1565 int PAD; /* 0x270 */
1566 int PAD; /* 0x274 */
1567 int PAD; /* 0x278 */
1568 int PAD; /* 0x27C */
1569 int PAD; /* 0x280 */
1570 int PAD; /* 0x284 */
1571 int PAD; /* 0x288 */
1572 int PAD; /* 0x28C */
1573 int PAD; /* 0x290 */
1574 int PAD; /* 0x294 */
1575 int PAD; /* 0x298 */
1576 int PAD; /* 0x29C */
1577 int PAD; /* 0x2A0 */
1578 int PAD; /* 0x2A4 */
1579 int PAD; /* 0x2A8 */
1580 int PAD; /* 0x2AC */
1581 int PAD; /* 0x2B0 */
1582 int PAD; /* 0x2B4 */
1583 int PAD; /* 0x2B8 */
1584 int PAD; /* 0x2BC */
1585 int PAD; /* 0x2C0 */
1586 int PAD; /* 0x2C4 */
1587 int PAD; /* 0x2C8 */
1588 int PAD; /* 0x2CC */
1589 int PAD; /* 0x2D0 */
1590 int PAD; /* 0x2D4 */
1591 int PAD; /* 0x2D8 */
1592 int PAD; /* 0x2DC */
1593 int PAD; /* 0x2E0 */
1594 int PAD; /* 0x2E4 */
1595 int PAD; /* 0x2E8 */
1596 int PAD; /* 0x2EC */
1597 int PAD; /* 0x2F0 */
1598 int PAD; /* 0x2F4 */
1599 int PAD; /* 0x2F8 */
1600 int PAD; /* 0x2FC */
1601 int PAD; /* 0X300 */
1602 int PAD; /* 0X304 */
1603 int PAD; /* 0X308 */
1604 int PAD; /* 0X30C */
1605 int PAD; /* 0X310 */
1606 int PAD; /* 0X314 */
1607 int PAD; /* 0X318 */
1608 int PAD; /* 0X31C */
1609 int PAD; /* 0X320 */
1610 int PAD; /* 0X324 */
1611 int PAD; /* 0X328 */
1612 int PAD; /* 0X32C */
1613 int PAD; /* 0X330 */
1614 int PAD; /* 0X334 */
1615 int PAD; /* 0X338 */
1616 int PAD; /* 0X33C */
1617 int PAD; /* 0X340 */
1618 int PAD; /* 0X344 */
1619 int PAD; /* 0X348 */
1620 int PAD; /* 0X34C */
1621 int PAD; /* 0X350 */
1622 int PAD; /* 0X354 */
1623 int PAD; /* 0X358 */
1624 int PAD; /* 0X35C */
1625 int PAD; /* 0X360 */
1626 int PAD; /* 0X364 */
1627 int PAD; /* 0X368 */
1628 int PAD; /* 0X36C */
1629 int PAD; /* 0X370 */
1630 int PAD; /* 0X374 */
1631 int PAD; /* 0X378 */
1632 int PAD; /* 0X37C */
1633 int PAD; /* 0X380 */
1634 int PAD; /* 0X384 */
1635 int PAD; /* 0X388 */
1636 int PAD; /* 0X38C */
1637 int PAD; /* 0X390 */
1638 int PAD; /* 0X394 */
1639 int PAD; /* 0X398 */
1640 int PAD; /* 0X39C */
1641 int PAD; /* 0X3A0 */
1642 int PAD; /* 0X3A4 */
1643 int PAD; /* 0X3A8 */
1644 int PAD; /* 0X3AC */
1645 int PAD; /* 0X3B0 */
1646 int PAD; /* 0X3B4 */
1647 int PAD; /* 0X3B8 */
1648 int PAD; /* 0X3BC */
1649 int PAD; /* 0X3C0 */
1650 int PAD; /* 0X3C4 */
1651 int PAD; /* 0X3C8 */
1652 int PAD; /* 0X3CC */
1653 int PAD; /* 0X3D0 */
1654 int PAD; /* 0X3D4 */
1655 int PAD; /* 0X3D8 */
1656 int PAD; /* 0X3DC */
1657 int PAD; /* 0X3E0 */
1658 int PAD; /* 0X3E4 */
1659 int PAD; /* 0X3E8 */
1660 int PAD; /* 0X3EC */
1661 int PAD; /* 0X3F0 */
1662 int PAD; /* 0X3F4 */
1663 int PAD; /* 0X3F8 */
1664 int PAD; /* 0X3FC */
1665 int PAD; /* 0X400 */
1666 int PAD; /* 0X404 */
1667 int PAD; /* 0X408 */
1668 int PAD; /* 0X40C */
1669 int PAD; /* 0X410 */
1670 int PAD; /* 0X414 */
1671 int PAD; /* 0X418 */
1672 int PAD; /* 0X41C */
1673 int PAD; /* 0X420 */
1674 int PAD; /* 0X424 */
1675 int PAD; /* 0X428 */
1676 int PAD; /* 0X42C */
1677 int PAD; /* 0X430 */
1678 int PAD; /* 0X434 */
1679 int PAD; /* 0X438 */
1680 int PAD; /* 0X43C */
1681 int PAD; /* 0X440 */
1682 int PAD; /* 0X444 */
1683 int PAD; /* 0X448 */
1684 int PAD; /* 0X44C */
1685 int PAD; /* 0X450 */
1686 int PAD; /* 0X454 */
1687 int PAD; /* 0X458 */
1688 int PAD; /* 0X45C */
1689 int PAD; /* 0X460 */
1690 int PAD; /* 0X464 */
1691 int PAD; /* 0X468 */
1692 int PAD; /* 0X46C */
1693 int PAD; /* 0X470 */
1694 int PAD; /* 0X474 */
1695 int PAD; /* 0X478 */
1696 int PAD; /* 0X47C */
1697 int PAD; /* 0X480 */
1698 int PAD; /* 0X484 */
1699 int PAD; /* 0X488 */
1700 int PAD; /* 0X48C */
1701 int PAD; /* 0X490 */
1702 int PAD; /* 0X494 */
1703 int PAD; /* 0X498 */
1704 int PAD; /* 0X49C */
1705 int PAD; /* 0X4A0 */
1706 int PAD; /* 0X4A4 */
1707 int PAD; /* 0X4A8 */
1708 int PAD; /* 0X4AC */
1709 int PAD; /* 0X4B0 */
1710 int PAD; /* 0X4B4 */
1711 int PAD; /* 0X4B8 */
1712 int PAD; /* 0X4BC */
1713 int PAD; /* 0X4C0 */
1714 int PAD; /* 0X4C4 */
1715 int PAD; /* 0X4C8 */
1716 int PAD; /* 0X4CC */
1717 int PAD; /* 0X4D0 */
1718 int PAD; /* 0X4D4 */
1719 int PAD; /* 0X4D8 */
1720 int PAD; /* 0X4DC */
1721 int PAD; /* 0X4E0 */
1722 int PAD; /* 0X4E4 */
1723 int PAD; /* 0X4E8 */
1724 int PAD; /* 0X4EC */
1725 int PAD; /* 0X4F0 */
1726 int PAD; /* 0X4F4 */
1727 int PAD; /* 0X4F8 */
1728 int PAD; /* 0X4FC */
1729 int PAD; /* 0X500 */
1730 int PAD; /* 0X504 */
1731 int PAD; /* 0X508 */
1732 int PAD; /* 0X50C */
1733 int PAD; /* 0X510 */
1734 int PAD; /* 0X514 */
1735 int PAD; /* 0X518 */
1736 int PAD; /* 0X51C */
1737 int PAD; /* 0X520 */
1738 int PAD; /* 0X524 */
1739 int PAD; /* 0X528 */
1740 int PAD; /* 0X52C */
1741 int PAD; /* 0X530 */
1742 int PAD; /* 0X534 */
1743 int PAD; /* 0X538 */
1744 int PAD; /* 0X53C */
1745 int PAD; /* 0X540 */
1746 short PAD; /* 0X544 */
1747 short field_546; /* 0X546 */
1748 int PAD; /* 0X548 */
1749 int PAD; /* 0X54C */
1750 int PAD; /* 0X550 */
1751 int PAD; /* 0X554 */
1752 int PAD; /* 0X558 */
1753 int PAD; /* 0X55C */
1754 int PAD; /* 0X560 */
1755 int PAD; /* 0X564 */
1756 int PAD; /* 0X568 */
1757 int PAD; /* 0X56C */
1758 int PAD; /* 0X570 */
1759 int PAD; /* 0X574 */
1760 int PAD; /* 0X578 */
1761 int PAD; /* 0X57C */
1762 int PAD; /* 0X580 */
1763 int PAD; /* 0X584 */
1764 } __attribute__((packed));
1765  
1766 struct hnddma_pub {
1767 void *di_fn; /* DMA function pointers */
1768 unsigned int txavail; /* # free tx descriptors */
1769 unsigned int dmactrlflags; /* dma control flags */
1770 /* rx error counters */
1771 unsigned int rxgiants; /* rx giant frames */
1772 unsigned int rxnobuf; /* rx out of dma descriptors */
1773 /* tx error counters */
1774 unsigned int txnobuf; /* tx out of dma descriptors */
1775 } __attribute__((packed));
1776  
1777 struct dma_info {
1778 struct hnddma_pub hnddma; /* exported structure */
1779 int msg_level; /* message level pointer */
1780 int something;
1781 char name[8]; /* callers name for diag msgs */
1782 void *osh;
1783 void *sih;
1784 bool dma64; /* this dma engine is operating in 64-bit mode */
1785 bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
1786 char gap2[2];
1787 void *txregs; /* 64-bit dma tx engine registers */
1788 void *rxregs; /* 64-bit dma rx engine registers */
1789 void *txd; /* pointer to dma64 tx descriptor ring */
1790 void *rxd; /* pointer to dma64 rx descriptor ring */
1791 short dmadesc_align; /* alignment requirement for dma descriptors */
1792 short ntxd; /* # tx descriptors tunable */
1793 short txin; /* index of next descriptor to reclaim */
1794 short txout; /* index of next descriptor to post */
1795 void **txp; /* pointer to parallel array of pointers to packets */
1796 void *tx_dmah; /* DMA MAP meta-data handle */
1797 int txp_dmah;
1798 int txdpa; /* Aligned physical address of descriptor ring */
1799 int txdpaorig; /* Original physical address of descriptor ring */
1800 short txdalign; /* #bytes added to alloc'd mem to align txd */
1801 int txdalloc; /* #bytes allocated for the ring */
1802 int xmtptrbase; /* When using unaligned descriptors, the ptr register
1803 * is not just an index, it needs all 13 bits to be
1804 * an offset from the addr register.
1805 */
1806 short PAD;
1807 short nrxd;
1808 short rxin;
1809 short rxout;
1810 short PAD;
1811 void **rxp;
1812 int PAD;
1813 int PAD;
1814 int rxdpa;
1815 short rxdalign;
1816 short PAD;
1817 int PAD;
1818 int PAD;
1819 int PAD;
1820 int rxbufsize; /* rx buffer size in bytes, not including the extra headroom */
1821 int rxextrahdrroom; /* extra rx headroom. */
1822  
1823 } __attribute__((packed));
1824  
1825 struct intctrlregs {
1826 unsigned int intstatus;
1827 unsigned int intmask;
1828 };
1829  
1830 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
1831 * write: only low 16b-it half can be written
1832 */
1833 union pmqreg {
1834 unsigned int pmqhostdata; /* read only! */
1835 struct {
1836 unsigned short pmqctrlstatus; /* read/write */
1837 unsigned short PAD;
1838 } w;
1839 };
1840  
1841 /* dma registers per channel(xmt or rcv) */
1842 struct dma64regs {
1843 unsigned int control; /* enable, et al */
1844 unsigned int ptr; /* last descriptor posted to chip */
1845 unsigned int addrlow; /* desc ring base address low 32-bits (8K aligned) */
1846 unsigned int addrhigh; /* desc ring base address bits 63:32 (8K aligned) */
1847 unsigned int status0; /* current descriptor, xmt state */
1848 unsigned int status1; /* active descriptor, xmt error */
1849 };
1850  
1851 /* 4byte-wide pio register set per channel(xmt or rcv) */
1852 struct pio4regs {
1853 unsigned int fifocontrol;
1854 unsigned int fifodata;
1855 };
1856  
1857 struct fifo64 {
1858 struct dma64regs dmaxmt; /* dma tx */
1859 struct pio4regs piotx; /* pio tx */
1860 struct dma64regs dmarcv; /* dma rx */
1861 struct pio4regs piorx; /* pio rx */
1862 };
1863  
1864 struct dma32diag { /* diag access */
1865 unsigned int fifoaddr; /* diag address */
1866 unsigned int fifodatalow; /* low 32bits of data */
1867 unsigned int fifodatahigh; /* high 32bits of data */
1868 unsigned int pad; /* reserved */
1869 };
1870  
1871 /*
1872 * Host Interface Registers
1873 */
1874 struct d11regs {
1875 /* Device Control ("semi-standard host registers") */
1876 unsigned int PAD[3]; /* 0x0 - 0x8 */
1877 unsigned int biststatus; /* 0xC */
1878 unsigned int biststatus2; /* 0x10 */
1879 unsigned int PAD; /* 0x14 */
1880 unsigned int gptimer; /* 0x18 */
1881 unsigned int usectimer; /* 0x1c *//* for corerev >= 26 */
1882  
1883 /* Interrupt Control *//* 0x20 */
1884 struct intctrlregs intctrlregs[8];
1885  
1886 unsigned int PAD[40]; /* 0x60 - 0xFC */
1887  
1888 unsigned int intrcvlazy[4]; /* 0x100 - 0x10C */
1889  
1890 unsigned int PAD[4]; /* 0x110 - 0x11c */
1891  
1892 unsigned int maccontrol; /* 0x120 */
1893 unsigned int maccommand; /* 0x124 */
1894 unsigned int macintstatus; /* 0x128 */
1895 unsigned int macintmask; /* 0x12C */
1896  
1897 /* Transmit Template Access */
1898 unsigned int tplatewrptr; /* 0x130 */
1899 unsigned int tplatewrdata; /* 0x134 */
1900 unsigned int PAD[2]; /* 0x138 - 0x13C */
1901  
1902 /* Power Management Queue (PMQ) registers */
1903 union pmqreg pmqreg; /* 0x140 */
1904 unsigned int pmqpatl; /* 0x144 */
1905 unsigned int pmqpath; /* 0x148 */
1906 unsigned int PAD; /* 0x14C */
1907  
1908 unsigned int chnstatus; /* 0x150 */
1909 unsigned int psmdebug; /* 0x154 */
1910 unsigned int phydebug; /* 0x158 */
1911 unsigned int machwcap; /* 0x15C */
1912  
1913 /* Extended Internal Objects */
1914 unsigned int objaddr; /* 0x160 */
1915 unsigned int objdata; /* 0x164 */
1916 unsigned int PAD[2]; /* 0x168 - 0x16c */
1917  
1918 unsigned int frmtxstatus; /* 0x170 */
1919 unsigned int frmtxstatus2; /* 0x174 */
1920 unsigned int PAD[2]; /* 0x178 - 0x17c */
1921  
1922 /* TSF host access */
1923 unsigned int tsf_timerlow; /* 0x180 */
1924 unsigned int tsf_timerhigh; /* 0x184 */
1925 unsigned int tsf_cfprep; /* 0x188 */
1926 unsigned int tsf_cfpstart; /* 0x18c */
1927 unsigned int tsf_cfpmaxdur32; /* 0x190 */
1928 unsigned int PAD[3]; /* 0x194 - 0x19c */
1929  
1930 unsigned int maccontrol1; /* 0x1a0 */
1931 unsigned int machwcap1; /* 0x1a4 */
1932 unsigned int PAD[14]; /* 0x1a8 - 0x1dc */
1933  
1934 /* Clock control and hardware workarounds*/
1935 unsigned int clk_ctl_st; /* 0x1e0 */
1936 unsigned int hw_war;
1937 unsigned int d11_phypllctl; /* the phypll request/avail bits are
1938 * moved to clk_ctl_st
1939 */
1940 unsigned int PAD[5]; /* 0x1ec - 0x1fc */
1941  
1942 /* 0x200-0x37F dma/pio registers */
1943 struct fifo64 fifo64regs[6];
1944  
1945 /* FIFO diagnostic port access */
1946 struct dma32diag dmafifo; /* 0x380 - 0x38C */
1947  
1948 unsigned int aggfifocnt; /* 0x390 */
1949 unsigned int aggfifodata; /* 0x394 */
1950 unsigned int PAD[16]; /* 0x398 - 0x3d4 */
1951 unsigned short radioregaddr; /* 0x3d8 */
1952 unsigned short radioregdata; /* 0x3da */
1953  
1954 /*
1955 * time delay between the change on rf disable input and
1956 * radio shutdown
1957 */
1958 unsigned int rfdisabledly; /* 0x3DC */
1959  
1960 /* PHY register access */
1961 unsigned short phyversion; /* 0x3e0 - 0x0 */
1962 unsigned short phybbconfig; /* 0x3e2 - 0x1 */
1963 unsigned short phyadcbias; /* 0x3e4 - 0x2 Bphy only */
1964 unsigned short phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
1965 unsigned short phyrxstatus0; /* 0x3e8 - 0x4 */
1966 unsigned short phyrxstatus1; /* 0x3ea - 0x5 */
1967 unsigned short phycrsth; /* 0x3ec - 0x6 */
1968 unsigned short phytxerror; /* 0x3ee - 0x7 */
1969 unsigned short phychannel; /* 0x3f0 - 0x8 */
1970 unsigned short PAD[1]; /* 0x3f2 - 0x9 */
1971 unsigned short phytest; /* 0x3f4 - 0xa */
1972 unsigned short phy4waddr; /* 0x3f6 - 0xb */
1973 unsigned short phy4wdatahi; /* 0x3f8 - 0xc */
1974 unsigned short phy4wdatalo; /* 0x3fa - 0xd */
1975 unsigned short phyregaddr; /* 0x3fc - 0xe */
1976 unsigned short phyregdata; /* 0x3fe - 0xf */
1977  
1978 /* IHR *//* 0x400 - 0x7FE */
1979  
1980 /* RXE Block */
1981 unsigned short PAD; /* SPR_RXE_0x00 0x400 */
1982 unsigned short PAD; /* SPR_RXE_Copy_Offset 0x402 */
1983 unsigned short PAD; /* SPR_RXE_Copy_Length 0x404 */
1984 unsigned short rcv_fifo_ctl; /* SPR_RXE_FIFOCTL0 0x406 */
1985 unsigned short PAD; /* SPR_RXE_FIFOCTL1 0x408 */
1986 unsigned short rcv_frm_cnt; /* SPR_Received_Frame_Count 0x40a */
1987 unsigned short PAD; /* SPR_RXE_0x0c 0x40c */
1988 unsigned short PAD; /* SPR_RXE_RXHDR_OFFSET 0x40e */
1989 unsigned short PAD; /* SPR_RXE_RXHDR_LEN 0x410 */
1990 unsigned short PAD; /* SPR_RXE_PHYRXSTAT0 0x412 */
1991 unsigned short rssi; /* SPR_RXE_PHYRXSTAT1 0x414 */
1992 unsigned short PAD; /* SPR_RXE_0x16 0x416 */
1993 unsigned short PAD; /* SPR_RXE_FRAMELEN 0x418 */
1994 unsigned short PAD; /* SPR_RXE_0x1a 0x41a */
1995 unsigned short PAD; /* SPR_RXE_ENCODING 0x41c */
1996 unsigned short PAD; /* SPR_RXE_0x1e 0x41e */
1997 unsigned short rcm_ctl; /* SPR_RCM_Control 0x420 */
1998 unsigned short rcm_mat_data; /* SPR_RCM_Match_Data 0x422 */
1999 unsigned short rcm_mat_mask; /* SPR_RCM_Match_Mask 0x424 */
2000 unsigned short rcm_mat_dly; /* SPR_RCM_Match_Delay 0x426 */
2001 unsigned short rcm_cond_mask_l; /* SPR_RCM_Condition_Mask_Low 0x428 */
2002 unsigned short rcm_cond_mask_h; /* SPR_RCM_Condition_Mask_High 0x42A */
2003 unsigned short rcm_cond_dly; /* SPR_RCM_Condition_Delay 0x42C */
2004 unsigned short PAD; /* SPR_RXE_0x2e 0x42E */
2005 unsigned short ext_ihr_addr; /* SPR_Ext_IHR_Address 0x430 */
2006 unsigned short ext_ihr_data; /* SPR_Ext_IHR_Data 0x432 */
2007 unsigned short rxe_phyrs_2; /* SPR_RXE_PHYRXSTAT2 0x434 */
2008 unsigned short rxe_phyrs_3; /* SPR_RXE_PHYRXSTAT3 0x436 */
2009 unsigned short phy_mode; /* SPR_PHY_Mode 0x438 */
2010 unsigned short rcmta_ctl; /* SPR_RCM_TA_Control 0x43a */
2011 unsigned short rcmta_size; /* SPR_RCM_TA_Size 0x43c */
2012 unsigned short rcmta_addr0; /* SPR_RCM_TA_Address_0 0x43e */
2013 unsigned short rcmta_addr1; /* SPR_RCM_TA_Address_1 0x440 */
2014 unsigned short rcmta_addr2; /* SPR_RCM_TA_Address_2 0x442 */
2015 unsigned short PAD[30]; /* SPR_RXE_0x44 ... 0x7e 0x444 */
2016  
2017  
2018 /* PSM Block *//* 0x480 - 0x500 */
2019  
2020 unsigned short PAD; /* SPR_MAC_MAX_NAP 0x480 */
2021 unsigned short psm_maccontrol_h; /* SPR_MAC_CTLHI 0x482 */
2022 unsigned short psm_macintstatus_l; /* SPR_MAC_IRQLO 0x484 */
2023 unsigned short psm_macintstatus_h; /* SPR_MAC_IRQHI 0x486 */
2024 unsigned short psm_macintmask_l; /* SPR_MAC_IRQMASKLO 0x488 */
2025 unsigned short psm_macintmask_h; /* SPR_MAC_IRQMASKHI 0x48A */
2026 unsigned short psm_0x0c; /* SPR_PSM_0x0c 0x48C */
2027 unsigned short psm_maccommand; /* SPR_MAC_CMD 0x48E */
2028 unsigned short psm_brc; /* SPR_BRC 0x490 */
2029 unsigned short psm_phy_hdr_param; /* SPR_PHY_HDR_Parameter 0x492 */
2030 unsigned short psm_postcard; /* SPR_Postcard 0x494 */
2031 unsigned short psm_pcard_loc_l; /* SPR_Postcard_Location_Low 0x496 */
2032 unsigned short psm_pcard_loc_h; /* SPR_Postcard_Location_High 0x498 */
2033 unsigned short psm_gpio_in; /* SPR_GPIO_IN 0x49A */
2034 unsigned short psm_gpio_out; /* SPR_GPIO_OUT 0x49C */
2035 unsigned short psm_gpio_oe; /* SPR_GPIO_OUTEN 0x49E */
2036  
2037 unsigned short psm_bred_0; /* SPR_BRED0 0x4A0 */
2038 unsigned short psm_bred_1; /* SPR_BRED1 0x4A2 */
2039 unsigned short psm_bred_2; /* SPR_BRED2 0x4A4 */
2040 unsigned short psm_bred_3; /* SPR_BRED3 0x4A6 */
2041 unsigned short psm_brcl_0; /* SPR_BRCL0 0x4A8 */
2042 unsigned short psm_brcl_1; /* SPR_BRCL1 0x4AA */
2043 unsigned short psm_brcl_2; /* SPR_BRCL2 0x4AC */
2044 unsigned short psm_brcl_3; /* SPR_BRCL3 0x4AE */
2045 unsigned short psm_brpo_0; /* SPR_BRPO0 0x4B0 */
2046 unsigned short psm_brpo_1; /* SPR_BRPO1 0x4B2 */
2047 unsigned short psm_brpo_2; /* SPR_BRPO2 0x4B4 */
2048 unsigned short psm_brpo_3; /* SPR_BRPO3 0x4B6 */
2049 unsigned short psm_brwk_0; /* SPR_BRWK0 0x4B8 */
2050 unsigned short psm_brwk_1; /* SPR_BRWK1 0x4BA */
2051 unsigned short psm_brwk_2; /* SPR_BRWK2 0x4BC */
2052 unsigned short psm_brwk_3; /* SPR_BRWK3 0x4BE */
2053  
2054 unsigned short psm_base_0; /* SPR_BASE0 - Offset Register 0 0x4C0 */
2055 unsigned short psm_base_1; /* SPR_BASE1 - Offset Register 1 0x4C2 */
2056 unsigned short psm_base_2; /* SPR_BASE2 - Offset Register 2 0x4C4 */
2057 unsigned short psm_base_3; /* SPR_BASE3 - Offset Register 3 0x4C6 */
2058 unsigned short psm_base_4; /* SPR_BASE4 - Offset Register 4 0x4C8 */
2059 unsigned short psm_base_5; /* SPR_BASE5 - Offset Register 5 0x4CA */
2060 unsigned short psm_base_6; /* SPR_BASE6 - Do not use (broken) 0x4CC */
2061 unsigned short psm_ihr_err; /* SPR_PSM_0x4e 0x4CE */
2062 unsigned short psm_pc_reg_0; /* SPR_PC0 - Link Register 0 0x4D0 */
2063 unsigned short psm_pc_reg_1; /* SPR_PC1 - Link Register 1 0x4D2 */
2064 unsigned short psm_pc_reg_2; /* SPR_PC2 - Link Register 2 0x4D4 */
2065 unsigned short psm_pc_reg_3; /* SPR_PC2 - Link Register 6 0x4D6 */
2066 unsigned short psm_brc_1; /* SPR_PSM_COND - PSM external condition bits 0x4D8 */
2067 unsigned short PAD; /* SPR_PSM_0x5a ... 0x7e 0x4DA */
2068 unsigned short PAD; /* SPR_PSM_0x5c 0x4DC */
2069 unsigned short PAD; /* SPR_PSM_0x5e 0x4DE */
2070 unsigned short PAD; /* SPR_PSM_0x60 0x4E0 */
2071 unsigned short PAD; /* SPR_PSM_0x62 0x4E2 */
2072 unsigned short PAD; /* SPR_PSM_0x64 0x4E4 */
2073 unsigned short PAD; /* SPR_PSM_0x66 0x4E6 */
2074 unsigned short PAD; /* SPR_PSM_0x68 0x4E8 */
2075 unsigned short PAD; /* SPR_PSM_0x6a 0x4EA */
2076 unsigned short PAD; /* SPR_PSM_0x6c 0x4EC */
2077 unsigned short PAD; /* SPR_PSM_0x6e 0x4EE */
2078 unsigned short psm_corectlsts; /* SPR_PSM_0x70 0x4F0 *//* Corerev >= 13 */
2079 unsigned short PAD; /* SPR_PSM_0x72 0x4F2 */
2080 unsigned short PAD; /* SPR_PSM_0x74 0x4F4 */
2081 unsigned short PAD; /* SPR_PSM_0x76 0x4F6 */
2082 unsigned short PAD; /* SPR_PSM_0x78 0x4F8 */
2083 unsigned short PAD; /* SPR_PSM_0x7a 0x4FA */
2084 unsigned short PAD; /* SPR_PSM_0x7c 0x4FC */
2085 unsigned short PAD; /* SPR_PSM_0x7e 0x4FE */
2086  
2087 /* TXE0 Block *//* 0x500 - 0x580 */
2088 unsigned short txe_ctl; /* SPR_TXE0_CTL 0x500 */
2089 unsigned short txe_aux; /* SPR_TXE0_AUX 0x502 */
2090 unsigned short txe_ts_loc; /* SPR_TXE0_TS_LOC 0x504 */
2091 unsigned short txe_time_out; /* SPR_TXE0_TIMEOUT 0x506 */
2092 unsigned short txe_wm_0; /* SPR_TXE0_WM0 0x508 */
2093 unsigned short txe_wm_1; /* SPR_TXE0_WM1 0x50A */
2094 unsigned short txe_phyctl; /* SPR_TXE0_PHY_CTL 0x50C */
2095 unsigned short txe_status; /* SPR_TXE0_STATUS 0x50E */
2096 unsigned short txe_mmplcp0; /* SPR_TXE0_0x10 0x510 */
2097 unsigned short txe_mmplcp1; /* SPR_TXE0_0x12 0x512 */
2098 unsigned short txe_phyctl1; /* SPR_TXE0_0x14 0x514 */
2099  
2100 unsigned short PAD; /* SPR_TXE0_0x16 0x516 */
2101 unsigned short PAD; /* SPR_TX_STATUS0 0x518 */
2102 unsigned short PAD; /* SPR_TX_STATUS1 0x51a */
2103 unsigned short PAD; /* SPR_TX_STATUS2 0x51c */
2104 unsigned short PAD; /* SPR_TX_STATUS3 0x51e */
2105  
2106 union {
2107 struct {
2108 /* Transmit control */
2109 uint16 xmtfifodef; /* 0x520 */
2110 uint16 xmtfifo_frame_cnt; /* 0x522 */ /* Corerev >= 16 */
2111 uint16 xmtfifo_byte_cnt; /* 0x524 */ /* Corerev >= 16 */
2112 uint16 xmtfifo_head; /* 0x526 */ /* Corerev >= 16 */
2113 uint16 xmtfifo_rd_ptr; /* 0x528 */ /* Corerev >= 16 */
2114 uint16 xmtfifo_wr_ptr; /* 0x52A */ /* Corerev >= 16 */
2115 uint16 xmtfifodef1; /* 0x52C */ /* Corerev >= 16 */
2116  
2117 /* AggFifo */
2118 uint16 aggfifo_cmd; /* 0x52e */
2119 uint16 aggfifo_stat; /* 0x530 */
2120 uint16 aggfifo_cfgctl; /* 0x532 */
2121 uint16 aggfifo_cfgdata; /* 0x534 */
2122 uint16 aggfifo_mpdunum; /* 0x536 */
2123 uint16 aggfifo_len; /* 0x538 */
2124 uint16 aggfifo_bmp; /* 0x53A */
2125 uint16 aggfifo_ackedcnt; /* 0x53C */
2126 uint16 aggfifo_sel; /* 0x53E */
2127  
2128 uint16 xmtfifocmd; /* 0x540 */
2129 uint16 xmtfifoflush; /* 0x542 */
2130 uint16 xmtfifothresh; /* 0x544 */
2131 uint16 xmtfifordy; /* 0x546 */
2132 uint16 xmtfifoprirdy; /* 0x548 */
2133 uint16 xmtfiforqpri; /* 0x54A */
2134 uint16 xmttplatetxptr; /* 0x54C */
2135 uint16 PAD; /* 0x54E */
2136 uint16 xmttplateptr; /* 0x550 */
2137 uint16 smpl_clct_strptr; /* 0x552 */ /* Corerev >= 22 */
2138 uint16 smpl_clct_stpptr; /* 0x554 */ /* Corerev >= 22 */
2139 uint16 smpl_clct_curptr; /* 0x556 */ /* Corerev >= 22 */
2140 uint16 aggfifo_data; /* 0x558 */
2141 uint16 PAD[0x03]; /* 0x55A - 0x55E */
2142 uint16 xmttplatedatalo; /* 0x560 */
2143 uint16 xmttplatedatahi; /* 0x562 */
2144  
2145 uint16 PAD[2]; /* 0x564 - 0x566 */
2146  
2147 uint16 xmtsel; /* 0x568 */
2148 uint16 xmttxcnt; /* 0x56A */
2149 uint16 xmttxshmaddr; /* 0x56C */
2150  
2151 uint16 PAD[0x09]; /* 0x56E - 0x57E */
2152  
2153 /* TXE1 Block */
2154 uint16 PAD[0x40]; /* 0x580 - 0x5FE */
2155  
2156 /* TSF Block */
2157 uint16 PAD[0X02]; /* 0x600 - 0x602 */
2158 uint16 tsf_cfpstrt_l; /* 0x604 */
2159 uint16 tsf_cfpstrt_h; /* 0x606 */
2160 uint16 PAD[0X05]; /* 0x608 - 0x610 */
2161 uint16 tsf_cfppretbtt; /* 0x612 */
2162 uint16 PAD[0XD]; /* 0x614 - 0x62C */
2163 uint16 tsf_clk_frac_l; /* 0x62E */
2164 uint16 tsf_clk_frac_h; /* 0x630 */
2165 uint16 PAD[0X14]; /* 0x632 - 0x658 */
2166 uint16 tsf_random; /* 0x65A */
2167 uint16 PAD[0x05]; /* 0x65C - 0x664 */
2168 /* GPTimer 2 registers are corerev >= 3 */
2169 uint16 tsf_gpt2_stat; /* 0x666 */
2170 uint16 tsf_gpt2_ctr_l; /* 0x668 */
2171 uint16 tsf_gpt2_ctr_h; /* 0x66A */
2172 uint16 tsf_gpt2_val_l; /* 0x66C */
2173 uint16 tsf_gpt2_val_h; /* 0x66E */
2174 uint16 tsf_gptall_stat; /* 0x670 */
2175 uint16 PAD[0x07]; /* 0x672 - 0x67E */
2176  
2177 /* IFS Block */
2178 uint16 ifs_sifs_rx_tx_tx; /* 0x680 */
2179 uint16 ifs_sifs_nav_tx; /* 0x682 */
2180 uint16 ifs_slot; /* 0x684 */
2181 uint16 PAD; /* 0x686 */
2182 uint16 ifs_ctl; /* 0x688 */
2183 uint16 ifs_boff; /* 0x68a */
2184 uint16 PAD[0x2]; /* 0x68c - 0x68F */
2185 uint16 ifsstat; /* 0x690 */
2186 uint16 ifsmedbusyctl; /* 0x692 */
2187 uint16 iftxdur; /* 0x694 */
2188 uint16 PAD[0x3]; /* 0x696 - 0x69b */
2189 /* EDCF support in dot11macs with corerevs >= 16 */
2190 uint16 ifs_aifsn; /* 0x69c */
2191 uint16 ifs_ctl1; /* 0x69e */
2192  
2193 /* New slow clock registers on corerev >= 5 */
2194 uint16 scc_ctl; /* 0x6a0 */
2195 uint16 scc_timer_l; /* 0x6a2 */
2196 uint16 scc_timer_h; /* 0x6a4 */
2197 uint16 scc_frac; /* 0x6a6 */
2198 uint16 scc_fastpwrup_dly; /* 0x6a8 */
2199 uint16 scc_per; /* 0x6aa */
2200 uint16 scc_per_frac; /* 0x6ac */
2201 uint16 scc_cal_timer_l; /* 0x6ae */
2202 uint16 scc_cal_timer_h; /* 0x6b0 */
2203 uint16 PAD; /* 0x6b2 */
2204  
2205 /* BTCX block on corerev >=13 */
2206 uint16 btcx_ctrl; /* 0x6b4 */
2207 uint16 btcx_stat; /* 0x6b6 */
2208 uint16 btcx_trans_ctrl; /* 0x6b8 */
2209 uint16 btcx_pri_win; /* 0x6ba */
2210 uint16 btcx_tx_conf_timer; /* 0x6bc */
2211 uint16 btcx_ant_sw_timer; /* 0x6be */
2212  
2213 uint16 btcx_prv_rfact_timer; /* 0x6c0 */
2214 uint16 btcx_cur_rfact_timer; /* 0x6c2 */
2215 uint16 btcx_rfact_dur_timer; /* 0x6c4 */
2216  
2217 uint16 ifs_ctl_sel_pricrs; /* 0x6c6 */
2218 uint16 ifs_ctl_sel_seccrs; /* 0x6c8 */
2219 uint16 PAD[19]; /* 0x6ca - 0x6ee */
2220  
2221 /* ECI regs on corerev >=14 */
2222 uint16 btcx_eci_addr; /* 0x6f0 */
2223 uint16 btcx_eci_data; /* 0x6f2 */
2224  
2225 uint16 PAD[6];
2226  
2227 /* NAV Block */
2228 uint16 nav_ctl; /* 0x700 */
2229 uint16 navstat; /* 0x702 */
2230 uint16 PAD[0x3e]; /* 0x702 - 0x77E */
2231  
2232 /* WEP/PMQ Block */ /* 0x780 - 0x7FE */
2233 uint16 PAD[0x20]; /* 0x780 - 0x7BE */
2234  
2235 uint16 wepctl; /* 0x7C0 */
2236 uint16 wepivloc; /* 0x7C2 */
2237 uint16 wepivkey; /* 0x7C4 */
2238 uint16 wepwkey; /* 0x7C6 */
2239  
2240 uint16 PAD[4]; /* 0x7C8 - 0x7CE */
2241 uint16 pcmctl; /* 0X7D0 */
2242 uint16 pcmstat; /* 0X7D2 */
2243 uint16 PAD[6]; /* 0x7D4 - 0x7DE */
2244  
2245 uint16 pmqctl; /* 0x7E0 */
2246 uint16 pmqstatus; /* 0x7E2 */
2247 uint16 pmqpat0; /* 0x7E4 */
2248 uint16 pmqpat1; /* 0x7E6 */
2249 uint16 pmqpat2; /* 0x7E8 */
2250  
2251 uint16 pmqdat; /* 0x7EA */
2252 uint16 pmqdator; /* 0x7EC */
2253 uint16 pmqhst; /* 0x7EE */
2254 uint16 pmqpath0; /* 0x7F0 */
2255 uint16 pmqpath1; /* 0x7F2 */
2256 uint16 pmqpath2; /* 0x7F4 */
2257 uint16 pmqdath; /* 0x7F6 */
2258  
2259 uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */
2260 /* SHM */ /* 0x800 - 0xEFE */
2261 uint16 PAD[0x380]; /* 0x800 - 0xEFE */
2262 } d11regs;
2263  
2264 struct {
2265 /* Transmit control */
2266 unsigned short xmtfifodef; /* SPR_TXE0_FIFO_Def 0x520 */
2267 unsigned short xmtfifo_frame_cnt; /* SPR_TXE0_0x22 0x522 *//* Corerev >= 16 */
2268 unsigned short xmtfifo_byte_cnt; /* SPR_TXE0_0x24 0x524 *//* Corerev >= 16 */
2269 unsigned short xmtfifo_head; /* SPR_TXE0_0x26 0x526 *//* Corerev >= 16 */
2270 unsigned short xmtfifo_rd_ptr; /* SPR_TXE0_0x28 0x528 *//* Corerev >= 16 */
2271 unsigned short xmtfifo_wr_ptr; /* SPR_TXE0_0x2a 0x52A *//* Corerev >= 16 */
2272 unsigned short xmtfifodef1; /* SPR_TXE0_0x2c 0x52C *//* Corerev >= 16 */
2273  
2274 unsigned short PAD; /* SPR_TXE0_0x2e 0x52E */
2275 unsigned short PAD; /* SPR_TXE0_0x30 0x530 */
2276 unsigned short PAD; /* SPR_TXE0_0x32 0x532 */
2277 unsigned short PAD; /* SPR_TXE0_0x34 0x534 */
2278 unsigned short PAD; /* SPR_TXE0_0x36 0x536 */
2279 unsigned short PAD; /* SPR_TXE0_0x38 0x538 */
2280 unsigned short PAD; /* SPR_TXE0_0x3a 0x53A */
2281 unsigned short PAD; /* SPR_TXE0_0x3c 0x53C */
2282 unsigned short PAD; /* SPR_TXE0_0x3e 0x53E */
2283  
2284 unsigned short xmtfifocmd; /* SPR_TXE0_FIFO_CMD 0x540 */
2285 unsigned short xmtfifoflush; /* SPR_TXE0_FIFO_FLUSH 0x542 */
2286 unsigned short xmtfifothresh; /* SPR_TXE0_FIFO_THRES 0x544 */
2287 unsigned short xmtfifordy; /* SPR_TXE0_FIFO_RDY 0x546 */
2288 unsigned short xmtfifoprirdy; /* SPR_TXE0_FIFO_PRI_RDY 0x548 */
2289 unsigned short xmtfiforqpri; /* SPR_TXE0_FIFO_RQ_PRI 0x54A */
2290 unsigned short xmttplatetxptr; /* SPR_TXE0_Template_TX_Pointer 0x54C */
2291 unsigned short PAD; /* SPR_TXE0_0x4e 0x54E */
2292 unsigned short xmttplateptr; /* SPR_TXE0_Template_Pointer 0x550 */
2293 unsigned short smpl_clct_strptr; /* SPR_TXE0_0x52 0x552 *//* Corerev >= 22 */
2294 unsigned short smpl_clct_stpptr; /* SPR_TXE0_0x54 0x554 *//* Corerev >= 22 */
2295 unsigned short smpl_clct_curptr; /* SPR_TXE0_0x56 0x556 *//* Corerev >= 22 */
2296 unsigned short PAD; /* SPR_TXE0_0x58 0x558 */
2297 unsigned short PAD; /* SPR_TXE0_0x5a 0x55A */
2298 unsigned short PAD; /* SPR_TXE0_0x5c 0x55C */
2299 unsigned short PAD; /* SPR_TXE0_0x5e 0x55E */
2300 unsigned short xmttplatedatalo; /* SPR_TXE0_Template_Data_Low 0x560 */
2301 unsigned short xmttplatedatahi; /* SPR_TXE0_Template_Data_High 0x562 */
2302  
2303 unsigned short PAD; /* SPR_TXE0_0x64 0x564 */
2304 unsigned short PAD; /* SPR_TXE0_0x66 0x566 */
2305  
2306 unsigned short xmtsel; /* SPR_TXE0_SELECT 0x568 */
2307 unsigned short xmttxcnt; /* 0x56A */
2308 unsigned short xmttxshmaddr; /* 0x56C */
2309  
2310 unsigned short PAD[0x09]; /* 0x56E - 0x57E */
2311  
2312 /* TXE1 Block */
2313 unsigned short PAD[0x40]; /* 0x580 - 0x5FE */
2314  
2315 /* TSF Block */
2316 unsigned short PAD[0X02]; /* 0x600 - 0x602 */
2317 unsigned short tsf_cfpstrt_l; /* 0x604 */
2318 unsigned short tsf_cfpstrt_h; /* 0x606 */
2319 unsigned short PAD[0X05]; /* 0x608 - 0x610 */
2320 unsigned short tsf_cfppretbtt; /* 0x612 */
2321 unsigned short PAD[0XD]; /* 0x614 - 0x62C */
2322 unsigned short tsf_clk_frac_l; /* 0x62E */
2323 unsigned short tsf_clk_frac_h; /* 0x630 */
2324 unsigned short PAD[0X14]; /* 0x632 - 0x658 */
2325 unsigned short tsf_random; /* 0x65A */
2326 unsigned short PAD[0x05]; /* 0x65C - 0x664 */
2327 /* GPTimer 2 registers */
2328 unsigned short tsf_gpt2_stat; /* 0x666 */
2329 unsigned short tsf_gpt2_ctr_l; /* 0x668 */
2330 unsigned short tsf_gpt2_ctr_h; /* 0x66A */
2331 unsigned short tsf_gpt2_val_l; /* 0x66C */
2332 unsigned short tsf_gpt2_val_h; /* 0x66E */
2333 unsigned short tsf_gptall_stat; /* 0x670 */
2334 unsigned short PAD[0x07]; /* 0x672 - 0x67E */
2335  
2336 /* IFS Block */
2337 unsigned short ifs_sifs_rx_tx_tx; /* 0x680 */
2338 unsigned short ifs_sifs_nav_tx; /* 0x682 */
2339 unsigned short ifs_slot; /* 0x684 */
2340 unsigned short PAD; /* 0x686 */
2341 unsigned short ifs_ctl; /* 0x688 */
2342 unsigned short PAD[0x3]; /* 0x68a - 0x68F */
2343 unsigned short ifsstat; /* 0x690 */
2344 unsigned short ifsmedbusyctl; /* 0x692 */
2345 unsigned short iftxdur; /* 0x694 */
2346 unsigned short PAD[0x3]; /* 0x696 - 0x69b */
2347 /* EDCF support in dot11macs */
2348 unsigned short ifs_aifsn; /* 0x69c */
2349 unsigned short ifs_ctl1; /* 0x69e */
2350  
2351 /* slow clock registers */
2352 unsigned short scc_ctl; /* 0x6a0 */
2353 unsigned short scc_timer_l; /* 0x6a2 */
2354 unsigned short scc_timer_h; /* 0x6a4 */
2355 unsigned short scc_frac; /* 0x6a6 */
2356 unsigned short scc_fastpwrup_dly; /* 0x6a8 */
2357 unsigned short scc_per; /* 0x6aa */
2358 unsigned short scc_per_frac; /* 0x6ac */
2359 unsigned short scc_cal_timer_l; /* 0x6ae */
2360 unsigned short scc_cal_timer_h; /* 0x6b0 */
2361 unsigned short PAD; /* 0x6b2 */
2362  
2363 unsigned short PAD[0x26];
2364  
2365 /* NAV Block */
2366 unsigned short nav_ctl; /* 0x700 */
2367 unsigned short navstat; /* 0x702 */
2368 unsigned short PAD[0x3e]; /* 0x702 - 0x77E */
2369  
2370 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
2371 unsigned short PAD[0x20]; /* 0x780 - 0x7BE */
2372  
2373 unsigned short wepctl; /* 0x7C0 */
2374 unsigned short wepivloc; /* 0x7C2 */
2375 unsigned short wepivkey; /* 0x7C4 */
2376 unsigned short wepwkey; /* 0x7C6 */
2377  
2378 unsigned short PAD[4]; /* 0x7C8 - 0x7CE */
2379 unsigned short pcmctl; /* 0X7D0 */
2380 unsigned short pcmstat; /* 0X7D2 */
2381 unsigned short PAD[6]; /* 0x7D4 - 0x7DE */
2382  
2383 unsigned short pmqctl; /* 0x7E0 */
2384 unsigned short pmqstatus; /* 0x7E2 */
2385 unsigned short pmqpat0; /* 0x7E4 */
2386 unsigned short pmqpat1; /* 0x7E6 */
2387 unsigned short pmqpat2; /* 0x7E8 */
2388  
2389 unsigned short pmqdat; /* 0x7EA */
2390 unsigned short pmqdator; /* 0x7EC */
2391 unsigned short pmqhst; /* 0x7EE */
2392 unsigned short pmqpath0; /* 0x7F0 */
2393 unsigned short pmqpath1; /* 0x7F2 */
2394 unsigned short pmqpath2; /* 0x7F4 */
2395 unsigned short pmqdath; /* 0x7F6 */
2396  
2397 unsigned short PAD[0x04]; /* 0x7F8 - 0x7FE */
2398  
2399 /* SHM *//* 0x800 - 0xEFE */
2400 unsigned short PAD[0x380]; /* 0x800 - 0xEFE */
2401 } d11regs_nexmon_old;
2402  
2403 struct {
2404 uint16 XmtFIFOFullThreshold; /* 0x520 */
2405 uint16 XmtFifoFrameCnt; /* 0x522 */
2406 uint16 PAD[1];
2407 uint16 BMCReadReq; /* 0x526 */
2408 uint16 BMCReadOffset; /* 0x528 */
2409 uint16 BMCReadLength; /* 0x52a */
2410 uint16 BMCReadStatus; /* 0x52c */
2411 uint16 XmtShmAddr; /* 0x52e */
2412 uint16 PsmMSDUAccess; /* 0x530 */
2413 uint16 MSDUEntryBufCnt; /* 0x532 */
2414 uint16 MSDUEntryStartIdx; /* 0x534 */
2415 uint16 MSDUEntryEndIdx; /* 0x536 */
2416 uint16 SampleCollectPlayPtrHigh; /* 0x538 */
2417 uint16 SampleCollectCurPtrHigh; /* 0x53a */
2418 uint16 BMCCmd1; /* 0x53c */
2419 uint16 PAD[1];
2420 uint16 BMCCTL; /* 0x540 */
2421 uint16 BMCConfig; /* 0x542 */
2422 uint16 BMCStartAddr; /* 0x544 */
2423 uint16 BMCSize; /* 0x546 */
2424 uint16 BMCCmd; /* 0x548 */
2425 uint16 BMCMaxBuffers; /* 0x54a */
2426 uint16 BMCMinBuffers; /* 0x54c */
2427 uint16 BMCAllocCtl; /* 0x54e */
2428 uint16 BMCDescrLen; /* 0x550 */
2429 uint16 SampleCollectStartPtr; /* 0x552 */
2430 uint16 SampleCollectStopPtr; /* 0x554 */
2431 uint16 SampleCollectCurPtr; /* 0x556 */
2432 uint16 SaveRestoreStartPtr; /* 0x558 */
2433 uint16 SamplePlayStartPtr; /* 0x55a */
2434 uint16 SamplePlayStopPtr; /* 0x55c */
2435 uint16 XmtDMABusy; /* 0x55e */
2436 uint16 XmtTemplateDataLo; /* 0x560 */
2437 uint16 XmtTemplateDataHi; /* 0x562 */
2438 uint16 XmtTemplatePtr; /* 0x564 */
2439 uint16 XmtSuspFlush; /* 0x566 */
2440 uint16 XmtFifoRqPrio; /* 0x568 */
2441 uint16 BMCStatCtl; /* 0x56a */
2442 uint16 BMCStatData; /* 0x56c */
2443 uint16 BMCMSDUFifoStat; /* 0x56e */
2444 uint16 PAD[4]; /* 0x570-576 */
2445 uint16 txe_status1; /* 0x578 */
2446 uint16 PAD[323]; /* 0x57a - 0x800 */
2447  
2448 /* AQM */
2449 uint16 AQMConfig; /* 0x800 */
2450 uint16 AQMFifoDef; /* 0x802 */
2451 uint16 AQMMaxIdx; /* 0x804 */
2452 uint16 AQMRcvdBA0; /* 0x806 */
2453 uint16 AQMRcvdBA1; /* 0x808 */
2454 uint16 AQMRcvdBA2; /* 0x80a */
2455 uint16 AQMRcvdBA3; /* 0x80c */
2456 uint16 AQMBaSSN; /* 0x80e */
2457 uint16 AQMRefSN; /* 0x810 */
2458 uint16 AQMMaxAggLenLow; /* 0x812 */
2459 uint16 AQMMaxAggLenHi; /* 0x814 */
2460 uint16 AQMAggParams; /* 0x816 */
2461 uint16 AQMMinMpduLen; /* 0x818 */
2462 uint16 AQMMacAdjLen; /* 0x81a */
2463 uint16 DebugBusCtrl; /* 0x81c */
2464 uint16 PAD[1];
2465 uint16 AQMAggStats; /* 0x820 */
2466 uint16 AQMAggLenLow; /* 0x822 */
2467 uint16 AQMAggLenHi; /* 0x824 */
2468 uint16 AQMIdxFifo; /* 0x826 */
2469 uint16 AQMMpduLenFifo; /* 0x828 */
2470 uint16 AQMTxCntFifo; /* 0x82a */
2471 uint16 AQMUpdBA0; /* 0x82c */
2472 uint16 AQMUpdBA1; /* 0x82e */
2473 uint16 AQMUpdBA2; /* 0x830 */
2474 uint16 AQMUpdBA3; /* 0x832 */
2475 uint16 AQMAckCnt; /* 0x834 */
2476 uint16 AQMConsCnt; /* 0x836 */
2477 uint16 AQMFifoReady; /* 0x838 */
2478 uint16 AQMStartLoc; /* 0x83a */
2479 uint16 PAD[2];
2480 uint16 TDCCTL; /* 0x840 */
2481 uint16 TDC_Plcp0; /* 0x842 */
2482 uint16 TDC_Plcp1; /* 0x844 */
2483 uint16 TDC_FrmLen0; /* 0x846 */
2484 uint16 TDC_FrmLen1; /* 0x848 */
2485 uint16 TDC_Txtime; /* 0x84a */
2486 uint16 TDC_VhtSigB0; /* 0x84c */
2487 uint16 TDC_VhtSigB1; /* 0x84e */
2488 uint16 TDC_LSigLen; /* 0x850 */
2489 uint16 TDC_NSym0; /* 0x852 */
2490 uint16 TDC_NSym1; /* 0x854 */
2491 uint16 TDC_VhtPsduLen0; /* 0x856 */
2492 uint16 TDC_VhtPsduLen1; /* 0x858 */
2493 uint16 TDC_VhtMacPad; /* 0x85a */
2494 uint16 PAD[2];
2495 uint16 ShmDma_Ctl; /* 0x860 */
2496 uint16 ShmDma_TxdcAddr; /* 0x862 */
2497 uint16 ShmDma_ShmAddr; /* 0x864 */
2498 uint16 ShmDma_XferCnt; /* 0x866 */
2499 uint16 Txdc_Addr; /* 0x868 */
2500 uint16 Txdc_Data; /* 0x86a */
2501 uint16 PAD[10]; /* 0x86c - 0x880 */
2502  
2503 /* RXE Register */
2504 uint16 MHP_Status; /* 0x880 */
2505 uint16 MHP_FC; /* 0x882 */
2506 uint16 MHP_DUR; /* 0x884 */
2507 uint16 MHP_SC; /* 0x886 */
2508 uint16 MHP_QOS; /* 0x888 */
2509 uint16 MHP_HTC_H; /* 0x88a */
2510 uint16 MHP_HTC_L; /* 0x88c */
2511 uint16 MHP_Addr1_H; /* 0x88e */
2512 uint16 MHP_Addr1_M; /* 0x890 */
2513 uint16 MHP_Addr1_L; /* 0x892 */
2514 uint16 PAD[6]; /* 0x894 - 0x8a0 */
2515 uint16 MHP_Addr2_H; /* 0x8a0 */
2516 uint16 MHP_Addr2_M; /* 0x8a2 */
2517 uint16 MHP_Addr2_L; /* 0x8a4 */
2518 uint16 MHP_Addr3_H; /* 0x8a6 */
2519 uint16 MHP_Addr3_M; /* 0x8a8 */
2520 uint16 MHP_Addr3_L; /* 0x8aa */
2521 uint16 MHP_Addr4_H; /* 0x8ac */
2522 uint16 MHP_Addr4_M; /* 0x8ae */
2523 uint16 MHP_Addr4_L; /* 0x8b0 */
2524 uint16 MHP_CFC; /* 0x8b2 */
2525 uint16 PAD[6]; /* 0x8b4 - 0x8c0 */
2526 uint16 DAGG_CTL2; /* 0x8c0 */
2527 uint16 DAGG_BYTESLEFT; /* 0x8c2 */
2528 uint16 DAGG_SH_OFFSET; /* 0x8c4 */
2529 uint16 DAGG_STAT; /* 0x8c6 */
2530 uint16 DAGG_LEN; /* 0x8c8 */
2531 uint16 TXBA_CTL; /* 0x8ca */
2532 uint16 TXBA_DataSel; /* 0x8cc */
2533 uint16 TXBA_Data; /* 0x8ce */
2534 uint16 PAD[8]; /* 0x8d0 - 0x8e0 */
2535 uint16 AMT_CTL; /* 0x8e0 */
2536 uint16 AMT_Status; /* 0x8e2 */
2537 uint16 AMT_Limit; /* 0x8e4 */
2538 uint16 AMT_Attr; /* 0x8e6 */
2539 uint16 AMT_Match1; /* 0x8e8 */
2540 uint16 AMT_Match2; /* 0x8ea */
2541 uint16 AMT_Table_Addr; /* 0x8ec */
2542 uint16 AMT_Table_Data; /* 0x8ee */
2543 uint16 AMT_Table_Val; /* 0x8f0 */
2544 uint16 AMT_DBG_SEL; /* 0x8f2 */
2545 uint16 PAD[6]; /* 0x8f4 - 0x900 */
2546 uint16 RoeCtrl; /* 0x900 */
2547 uint16 RoeStatus; /* 0x902 */
2548 uint16 RoeIPChkSum; /* 0x904 */
2549 uint16 RoeTCPUDPChkSum; /* 0x906 */
2550 uint16 PAD[12]; /* 0x908 - 0x920 */
2551 uint16 PSOCtl; /* 0x920 */
2552 uint16 PSORxWordsWatermark; /* 0x922 */
2553 uint16 PSORxCntWatermark; /* 0x924 */
2554 uint16 PAD[5]; /* 0x926 - 0x930 */
2555 uint16 OBFFCtl; /* 0x930 */
2556 uint16 OBFFRxWordsWatermark; /* 0x932 */
2557 uint16 OBFFRxCntWatermark; /* 0x934 */
2558 uint16 PAD[101]; /* 0x936 - 0xa00 */
2559  
2560 /* TOE */
2561 uint16 ToECTL; /* 0xa00 */
2562 uint16 ToERst; /* 0xa02 */
2563 uint16 ToECSumNZ; /* 0xa04 */
2564 uint16 PAD[29]; /* 0xa06 - 0xa40 */
2565  
2566 uint16 TxSerialCtl; /* 0xa40 */
2567 uint16 TxPlcpLSig0; /* 0xa42 */
2568 uint16 TxPlcpLSig1; /* 0xa44 */
2569 uint16 TxPlcpHtSig0; /* 0xa46 */
2570 uint16 TxPlcpHtSig1; /* 0xa48 */
2571 uint16 TxPlcpHtSig2; /* 0xa4a */
2572 uint16 TxPlcpVhtSigB0; /* 0xa4c */
2573 uint16 TxPlcpVhtSigB1; /* 0xa4e */
2574 uint16 PAD[1];
2575  
2576 uint16 MacHdrFromShmLen; /* 0xa52 */
2577 uint16 TxPlcpLen; /* 0xa54 */
2578 uint16 PAD[1];
2579  
2580 uint16 TxBFRptLen; /* 0xa58 */
2581 uint16 PAD[3];
2582  
2583 uint16 TXBFCtl; /* 0xa60 */
2584 uint16 BfmRptOffset; /* 0xa62 */
2585 uint16 BfmRptLen; /* 0xa64 */
2586 uint16 TXBFBfeRptRdCnt; /* 0xa66 */
2587 uint16 PAD[76]; /* 0xa68 - 0xafe */
2588 uint16 RXMapFifoSize; /* 0xb00 */
2589 uint16 PAD[511]; /* 0xb02 - 0xEFE */
2590 } d11acregs;
2591 } u;
2592 } __attribute__((packed));
2593  
2594 /* 11AC TX DMA buffer header */
2595 #define D11_PHY_HDR_LEN 6
2596 #define D11AC_TXH_NUM_RATES 4
2597 /* per rate info */
2598 typedef struct d11actxh_rate d11actxh_rate_t;
2599 struct d11actxh_rate {
2600 uint16 PhyTxControlWord_0; /* 0 - 1 */
2601 uint16 PhyTxControlWord_1; /* 2 - 3 */
2602 uint16 PhyTxControlWord_2; /* 4 - 5 */
2603 uint8 plcp[D11_PHY_HDR_LEN]; /* 6 - 11 */
2604 uint16 FbwInfo; /* 12 -13 */
2605 uint16 TxRate; /* 14 */
2606 uint16 RtsCtsControl; /* 16 */
2607 uint16 Bfm0; /* 18 */
2608 } __attribute__((packed));
2609  
2610 /* per packet info */
2611 typedef struct d11actxh_pkt d11actxh_pkt_t;
2612 struct d11actxh_pkt {
2613 /* Per pkt info */
2614 uint16 TSOInfo; /* 0 */
2615 uint16 MacTxControlLow; /* 2 */
2616 uint16 MacTxControlHigh; /* 4 */
2617 uint16 Chanspec; /* 6 */
2618 uint8 IVOffset; /* 8 */
2619 uint8 PktCacheLen; /* 9 */
2620 uint16 FrameLen; /* 10 */
2621 uint16 TxFrameID; /* 12 */
2622 uint16 Seq; /* 14 */
2623 uint16 Tstamp; /* 16 */
2624 uint16 TxStatus; /* 18 */
2625 } __attribute__((packed));
2626  
2627 /* Per cache info */
2628 typedef struct d11actxh_cache d11actxh_cache_t;
2629 struct d11actxh_cache {
2630 uint8 BssIdEncAlg; /* 0 */
2631 uint8 KeyIdx; /* 1 */
2632 uint8 PrimeMpduMax; /* 2 */
2633 uint8 FallbackMpduMax; /* 3 */
2634 uint16 AmpduDur; /* 4 - 5 */
2635 uint8 BAWin; /* 6 */
2636 uint8 MaxAggLen; /* 7 */
2637 uint8 TkipPH1Key[10]; /* 8 - 17 */
2638 uint8 TSCPN[6]; /* 18 - 23 */
2639 } __attribute__((packed));
2640  
2641 /* Long format tx descriptor */
2642 typedef struct d11actxh d11actxh_t;
2643 struct d11actxh {
2644 /* Per pkt info */
2645 d11actxh_pkt_t PktInfo; /* 0 - 19 */
2646 /* Per rate info */
2647 d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 20 - 99 */
2648 /* Per cache info */
2649 d11actxh_cache_t CacheInfo; /* 100 - 123 */
2650 } __attribute__((packed));
2651  
2652 typedef void (*to_fun_t)(void *arg);
2653  
2654 typedef struct _ctimeout {
2655 struct _ctimeout *next;
2656 uint32 ms;
2657 to_fun_t fun;
2658 void *arg;
2659 bool expired;
2660 } ctimeout_t;
2661  
2662 struct hndrte_timer
2663 {
2664 uint32 *context; /* first field so address of context is timer struct ptr */
2665 void *data;
2666 void (*mainfn)(struct hndrte_timer *);
2667 void (*auxfn)(void *context);
2668 ctimeout_t t;
2669 int interval;
2670 int set;
2671 int periodic;
2672 bool _freedone;
2673 } __attribute__((packed));
2674  
2675 /*== maccontrol register ==*/
2676 #define MCTL_GMODE (1U << 31)
2677 #define MCTL_DISCARD_PMQ (1 << 30)
2678 #define MCTL_WAKE (1 << 26)
2679 #define MCTL_HPS (1 << 25)
2680 #define MCTL_PROMISC (1 << 24)
2681 #define MCTL_KEEPBADFCS (1 << 23)
2682 #define MCTL_KEEPCONTROL (1 << 22)
2683 #define MCTL_PHYLOCK (1 << 21)
2684 #define MCTL_BCNS_PROMISC (1 << 20)
2685 #define MCTL_LOCK_RADIO (1 << 19)
2686 #define MCTL_AP (1 << 18)
2687 #define MCTL_INFRA (1 << 17)
2688 #define MCTL_BIGEND (1 << 16)
2689 #define MCTL_GPOUT_SEL_MASK (3 << 14)
2690 #define MCTL_GPOUT_SEL_SHIFT 14
2691 #define MCTL_EN_PSMDBG (1 << 13)
2692 #define MCTL_IHR_EN (1 << 10)
2693 #define MCTL_SHM_UPPER (1 << 9)
2694 #define MCTL_SHM_EN (1 << 8)
2695 #define MCTL_PSM_JMP_0 (1 << 2)
2696 #define MCTL_PSM_RUN (1 << 1)
2697 #define MCTL_EN_MAC (1 << 0)
2698  
2699  
2700 struct ethernet_header {
2701 uint8 dst[6];
2702 uint8 src[6];
2703 uint16 type;
2704 } __attribute__((packed));
2705  
2706 struct ipv6_header {
2707 uint32 version_traffic_class_flow_label;
2708 uint16 payload_length;
2709 uint8 next_header;
2710 uint8 hop_limit;
2711 uint8 src_ip[16];
2712 uint8 dst_ip[16];
2713 } __attribute__((packed));
2714  
2715 struct ip_header {
2716 uint8 version_ihl;
2717 uint8 dscp_ecn;
2718 uint16 total_length;
2719 uint16 identification;
2720 uint16 flags_fragment_offset;
2721 uint8 ttl;
2722 uint8 protocol;
2723 uint16 header_checksum;
2724 union {
2725 uint32 integer;
2726 uint8 array[4];
2727 } src_ip;
2728 union {
2729 uint32 integer;
2730 uint8 array[4];
2731 } dst_ip;
2732 } __attribute__((packed));
2733  
2734 struct udp_header {
2735 uint16 src_port;
2736 uint16 dst_port;
2737 union {
2738 uint16 length; /* UDP: length of UDP header and payload */
2739 uint16 checksum_coverage; /* UDPLITE: checksum_coverage */
2740 } len_chk_cov;
2741 uint16 checksum;
2742 } __attribute__((packed));
2743  
2744 struct icmp_header {
2745 uint8 type;
2746 uint8 code;
2747 uint16 checksum;
2748 } __attribute__((packed));
2749  
2750 struct icmp_ping_header {
2751 uint16 identifier;
2752 uint16 sequence_number;
2753 } __attribute__((packed));
2754  
2755 struct ethernet_ip_icmp_ping_header {
2756 struct ethernet_header ethernet;
2757 struct ip_header ip;
2758 struct icmp_header icmp;
2759 struct icmp_ping_header ping;
2760 uint8 payload[];
2761 } __attribute__((packed));
2762  
2763 struct ethernet_ip_udp_header {
2764 struct ethernet_header ethernet;
2765 struct ip_header ip;
2766 struct udp_header udp;
2767 } __attribute__((packed));
2768  
2769 struct bdc_ethernet_ip_udp_header {
2770 struct bdc_header bdc;
2771 struct ethernet_header ethernet;
2772 struct ip_header ip;
2773 struct udp_header udp;
2774 } __attribute__((packed));
2775  
2776 struct bdc_ethernet_ipv6_udp_header {
2777 struct bdc_header bdc;
2778 struct ethernet_header ethernet;
2779 struct ipv6_header ipv6;
2780 struct udp_header udp;
2781 uint8 payload[1];
2782 } __attribute__((packed));
2783  
2784 struct nexmon_header {
2785 uint32 hooked_fct;
2786 uint32 args[3];
2787 uint8 payload[1];
2788 } __attribute__((packed));
2789  
2790 #endif /*STRUCTS_COMMON_H */