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1 office 1 /*
2 Copyright (c) 2013, Jurriaan Bremer
3 All rights reserved.
4  
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7  
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of the darm developer(s) nor the names of its
14 contributors may be used to endorse or promote products derived from this
15 software without specific prior written permission.
16  
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28 */
29 #ifndef __DARM_TBL__
30 #define __DARM_TBL__
31 #include <stdint.h>
32 typedef enum _darm_enctype_t {
33 // info:
34 // Invalid or non-existent type
35 //
36 // encodings:
37 // I_INVLD
38 //
39 // affects:
40 //
41 T_INVLD,
42  
43 // info:
44 // ADR Instruction, which is an optimization of ADD
45 //
46 // encodings:
47 // ADR<c> <Rd>,<label>
48 //
49 // affects:
50 // ADR
51 T_ARM_ADR,
52  
53 // info:
54 // All unconditional instructions
55 //
56 // encodings:
57 // ins <endian_specifier>
58 // ins [<Rn>,#+/-<imm12>]
59 // ins [<Rn>,#<imm12>]
60 // ins
61 // ins #<option>
62 // ins <label>
63 //
64 // affects:
65 // BLX, CLREX, DMB, DSB, ISB, PLD, PLI, SETEND
66 T_ARM_UNCOND,
67  
68 // info:
69 // All multiplication instructions
70 //
71 // encodings:
72 // ins{S}<c> <Rd>,<Rn>,<Rm>
73 // ins{S}<c> <Rd>,<Rn>,<Rm>,<Ra>
74 // ins{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
75 //
76 // affects:
77 // MLA, MLS, MUL, SMLAL, SMULL, UMAAL, UMLAL, UMULL
78 T_ARM_MUL,
79  
80 // info:
81 // Various STR and LDR instructions
82 //
83 // encodings:
84 // ins<c> <Rt>,[<Rn>,#+/-<imm12>]
85 // ins<c> <Rt>,[<Rn>],#+/-<imm12>
86 // ins<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}
87 //
88 // affects:
89 // LDR, LDRB, LDRBT, LDRT, POP, PUSH, STR, STRB, STRBT, STRT
90 T_ARM_STACK0,
91  
92 // info:
93 // Various unprivileged STR and LDR instructions
94 //
95 // encodings:
96 // ins<c> <Rt>,[<Rn>],+/-<Rm>
97 // ins<c> <Rt>,[<Rn>]{,#+/-<imm8>}
98 //
99 // affects:
100 // LDRHT, LDRSBT, LDRSHT, STRHT
101 T_ARM_STACK1,
102  
103 // info:
104 // Various other STR and LDR instructions
105 //
106 // encodings:
107 // ins<c> <Rt>,<Rt2>,[<Rn>],+/-<Rm>
108 // ins<c> <Rt>,[<Rn>],+/-<Rm>
109 // ins<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
110 // ins<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]
111 // ins<c> <Rt>,[<Rn>,#+/-<imm8>]
112 //
113 // affects:
114 // LDRD, LDRH, LDRSB, LDRSH, STRD, STRH
115 T_ARM_STACK2,
116  
117 // info:
118 // Arithmetic instructions which take a shift for the second source
119 //
120 // encodings:
121 // ins{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}
122 // ins{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
123 //
124 // affects:
125 // ADC, ADD, AND, BIC, EOR, ORR, RSB, RSC, SBC, SUB
126 T_ARM_ARITH_SHIFT,
127  
128 // info:
129 // Arithmetic instructions which take an immediate as second source
130 //
131 // encodings:
132 // ins{S}<c> <Rd>,<Rn>,#<const>
133 //
134 // affects:
135 // ADC, ADD, AND, BIC, EOR, ORR, RSB, RSC, SBC, SUB
136 T_ARM_ARITH_IMM,
137  
138 // info:
139 // Bit field magic
140 //
141 // encodings:
142 //
143 //
144 // affects:
145 // BFC, BFI, SBFX, UBFX
146 T_ARM_BITS,
147  
148 // info:
149 // Branch and System Call instructions
150 //
151 // encodings:
152 // B(L)<c> <label>
153 // SVC<c> #<imm24>
154 //
155 // affects:
156 // B, BL, SVC
157 T_ARM_BRNCHSC,
158  
159 // info:
160 // Branch and Misc instructions
161 //
162 // encodings:
163 // B(L)X(J)<c> <Rm>
164 // BKPT #<imm16>
165 // MSR<c> <spec_reg>,<Rn>
166 //
167 // affects:
168 // BKPT, BLX, BX, BXJ, MSR, SMLAW, SMULW
169 T_ARM_BRNCHMISC,
170  
171 // info:
172 // Move immediate to a register (possibly negating it)
173 //
174 // encodings:
175 // ins{S}<c> <Rd>,#<const>
176 //
177 // affects:
178 // MOV, MOVT, MOVW, MVN
179 T_ARM_MOV_IMM,
180  
181 // info:
182 // Comparison instructions which take two operands
183 //
184 // encodings:
185 // ins<c> <Rn>,<Rm>{,<shift>}
186 // ins<c> <Rn>,<Rm>,<type> <Rs>
187 //
188 // affects:
189 // CMN, CMP, TEQ, TST
190 T_ARM_CMP_OP,
191  
192 // info:
193 // Comparison instructions which take an immediate
194 //
195 // encodings:
196 // ins<c> <Rn>,#<const>
197 //
198 // affects:
199 // CMN, CMP, TEQ, TST
200 T_ARM_CMP_IMM,
201  
202 // info:
203 // Instructions which don't take any operands
204 //
205 // encodings:
206 // ins<c>
207 //
208 // affects:
209 // NOP, SEV, WFE, WFI, YIELD
210 T_ARM_OPLESS,
211  
212 // info:
213 // Manipulate and move a register to another register
214 //
215 // encodings:
216 // ins{S}<c> <Rd>,<Rm>
217 // ins{S}<c> <Rd>,<Rm>,#<imm>
218 // ins{S}<c> <Rd>,<Rn>,<Rm>
219 //
220 // affects:
221 // ASR, LDREXD, LSL, LSR, MOV, ROR, RRX, STREXD
222 T_ARM_DST_SRC,
223  
224 // info:
225 // Load or store multiple registers at once
226 //
227 // encodings:
228 // ins<c> <Rn>{!},<registers>
229 //
230 // affects:
231 // LDM, LDMDA, LDMDB, LDMIB, PUSH, STM, STMDA, STMDB, STMIB
232 T_ARM_LDSTREGS,
233  
234 // info:
235 // Bit reverse instructions
236 //
237 // encodings:
238 // ins<c> <Rd>,<Rm>
239 //
240 // affects:
241 // CLZ, RBIT, REV, REV16, REVSH
242 T_ARM_BITREV,
243  
244 // info:
245 // Various miscellaneous instructions
246 //
247 // encodings:
248 // ins{S}<c> <Rd>,<Rm>,<type> <Rs>
249 // ins{S}<c> <Rd>,<Rm>{,<shift>}
250 // ins<c> #<imm4>
251 // ins<c> #<option>
252 // ins<c> <Rd>,<Rn>,<Rm>{,<type> #<imm>}
253 // ins<c> <Rd>,<Rn>,<Rm>
254 //
255 // affects:
256 // DBG, MVN, PKH, SEL, SMC
257 T_ARM_MISC,
258  
259 // info:
260 // Various signed multiply instructions
261 //
262 // encodings:
263 //
264 //
265 // affects:
266 // SMLA, SMLAD, SMLAL, SMLALD, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD,
267 // SMUL, SMUSD
268 T_ARM_SM,
269  
270 // info:
271 // Parallel signed and unsigned addition and subtraction
272 //
273 // encodings:
274 // ins<c> <Rd>,<Rn>,<Rm>
275 //
276 // affects:
277 // QADD16, QADD8, QASX, QSAX, QSUB16, QSUB8, SADD16, SADD8, SASX, SHADD16,
278 // SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SSAX, SSUB16, SSUB8, UADD16, UADD8,
279 // UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UQADD16, UQADD8,
280 // UQASX, UQSAX, UQSUB16, UQSUB8, USAX, USUB16, USUB8
281 T_ARM_PAS,
282  
283 // info:
284 // Saturating addition and subtraction instructions
285 //
286 // encodings:
287 // ins<c> <Rd>,<Rn>,<Rm>
288 //
289 // affects:
290 // QADD, QDADD, QDSUB, QSUB
291 T_ARM_SAT,
292  
293 // info:
294 // Synchronization primitives
295 //
296 // encodings:
297 // ins{B}<c> <Rt>,<Rt2>,[<Rn>]
298 // ins<c> <Rd>,<Rt>,[<Rn>]
299 // ins<c> <Rt>,<Rt2>,[<Rn>]
300 // ins<c> <Rt>,[<Rn>]
301 //
302 // affects:
303 // LDREX, LDREXB, LDREXH, STREX, STREXB, STREXH, SWP, SWPB
304 T_ARM_SYNC,
305  
306 // info:
307 // Packing, unpacking, saturation, and reversal instructions
308 //
309 // encodings:
310 // ins<c> <Rd>,#<imm>,<Rn>
311 // ins<c> <Rd>,#<imm>,<Rn>{,<shift>}
312 // ins<c> <Rd>,<Rn>,<Rm>{,<rotation>}
313 // ins<c> <Rd>,<Rm>{,<rotation>}
314 //
315 // affects:
316 // SSAT, SSAT16, SXTAB, SXTAB16, SXTAH, SXTB, SXTB16, SXTH, USAT, USAT16,
317 // UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, UXTH
318 T_ARM_PUSR,
319  
320 // info:
321 // Move to/from Coprocessor to/from ARM core register
322 //
323 // encodings:
324 // ins<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,{,<opc2>}
325 //
326 // affects:
327 // CDP, MCR, MRC
328 T_ARM_MVCR,
329  
330 // info:
331 // Permanently Undefined Instruction
332 //
333 // encodings:
334 // ins<c> #<imm>
335 //
336 // affects:
337 // UDF
338 T_ARM_UDF,
339  
340 // info:
341 // Instructions which only take an 8-byte immediate
342 //
343 // encodings:
344 // ins<c> #<imm8>
345 //
346 // affects:
347 // BKPT, SVC, UDF
348 T_THUMB_ONLY_IMM8,
349  
350 // info:
351 // Conditional branch
352 //
353 // encodings:
354 // ins<c> <label>
355 //
356 // affects:
357 // B
358 T_THUMB_COND_BRANCH,
359  
360 // info:
361 // Unconditional branch
362 //
363 // encodings:
364 // ins<c> <label>
365 //
366 // affects:
367 // B
368 T_THUMB_UNCOND_BRANCH,
369  
370 // info:
371 // Shifting instructions which take an immediate
372 //
373 // encodings:
374 // ins<c> <Rd>, <Rm>, #<imm>
375 //
376 // affects:
377 // ASR, LSL, LSR
378 T_THUMB_SHIFT_IMM,
379  
380 // info:
381 // Load from and Store to the stack
382 //
383 // encodings:
384 // ins<c> <Rt>, [SP, #<imm>]
385 //
386 // affects:
387 // LDR, STR
388 T_THUMB_STACK,
389  
390 // info:
391 // Load a value relative to PC
392 //
393 // encodings:
394 // ins<c> <Rt>, <label>
395 //
396 // affects:
397 // LDR
398 T_THUMB_LDR_PC,
399  
400 // info:
401 // Various General Purpose Instructions
402 //
403 // encodings:
404 // ins<c> <Rdn>, <Rm>
405 // ins<c> <Rn>, <Rm>
406 // ins<c> <Rdm>, <Rn>, <Rdm>
407 // ins<c> <Rd>, <Rm>
408 //
409 // affects:
410 // ADC, AND, ASR, BIC, CMN, CMP, EOR, LSL, LSR, MUL, MVN, ORR, ROR, RSB, SBC,
411 // TST
412 T_THUMB_GPI,
413  
414 // info:
415 // Branch (and optionally link) to a Register
416 //
417 // encodings:
418 // ins<c> <Rm>
419 //
420 // affects:
421 // BLX, BX
422 T_THUMB_BRANCH_REG,
423  
424 // info:
425 // If-Then and Hints
426 //
427 // encodings:
428 // ins<c>
429 //
430 // affects:
431 // IT, NOP, SEV, WFE, WFI, YIELD
432 T_THUMB_IT_HINTS,
433  
434 // info:
435 // Instructions with an 8bit immediate
436 //
437 // encodings:
438 // ins<c> <Rdn>, #<imm>
439 // ins<c> <Rd>, SP, #<imm>
440 // ins<c> <Rd>, <label>
441 // ins<c> <Rn>, #<imm>
442 // ins<c> <Rd>, #<imm>
443 //
444 // affects:
445 // ADD, ADR, CMP, MOV, SUB
446 T_THUMB_HAS_IMM8,
447  
448 // info:
449 // Bit Extension instructions
450 //
451 // encodings:
452 // ins<c> <Rd>, <Rm>
453 //
454 // affects:
455 // SXTB, SXTH, UXTB, UXTH
456 T_THUMB_EXTEND,
457  
458 // info:
459 // Modifies the Stack Pointer by an Immediate
460 //
461 // encodings:
462 // ins<c> SP, SP, #<imm>
463 //
464 // affects:
465 // ADD, SUB
466 T_THUMB_MOD_SP_IMM,
467  
468 // info:
469 // Instructions with 3 registers as operands
470 //
471 // encodings:
472 // ins<c> <Rd>, <Rn>, <Rm>
473 //
474 // affects:
475 // ADD, SUB
476 T_THUMB_3REG,
477  
478 // info:
479 // Instructions with two registers and an immediate
480 //
481 // encodings:
482 // ins<c> <Rd>, <Rn>, #<imm>
483 //
484 // affects:
485 // ADD, SUB
486 T_THUMB_2REG_IMM,
487  
488 // info:
489 // Add SP with an Immediate to a register
490 //
491 // encodings:
492 // ins<c> <Rd>, SP, #<imm>
493 //
494 // affects:
495 // ADD
496 T_THUMB_ADD_SP_IMM,
497  
498 // info:
499 // Move operation with 4bit registers
500 //
501 // encodings:
502 // ins<c> <Rd>, <Rn>
503 //
504 // affects:
505 // MOV
506 T_THUMB_MOV4,
507  
508 // info:
509 // Instructions to manipulate memory
510 //
511 // encodings:
512 // ins<c> <Rt>, [<Rn>, #<imm>]
513 //
514 // affects:
515 // LDR, LDRB, LDRH, STR, STRB, STRH
516 T_THUMB_RW_MEMI,
517  
518 // info:
519 // Instructions to manipulate memory
520 //
521 // encodings:
522 // ins<c> <Rt>, [<Rn>, <Rm>]
523 //
524 // affects:
525 // LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH
526 T_THUMB_RW_MEMO,
527  
528 // info:
529 // Load and Store register lists
530 //
531 // encodings:
532 // ins<c> <Rn>{!}, <registers>
533 //
534 // affects:
535 // LDM, STM
536 T_THUMB_RW_REG,
537  
538 // info:
539 // Various Reverse instructions
540 //
541 // encodings:
542 // ins<c> <Rd>, <Rm>
543 //
544 // affects:
545 // REV, REV16, REVSH
546 T_THUMB_REV,
547  
548 // info:
549 // Set Endian instruction
550 //
551 // encodings:
552 // ins <endian_specifier>
553 //
554 // affects:
555 // SETEND
556 T_THUMB_SETEND,
557  
558 // info:
559 // Push and Pop registers
560 //
561 // encodings:
562 // ins<c> <registers>
563 //
564 // affects:
565 // POP, PUSH
566 T_THUMB_PUSHPOP,
567  
568 // info:
569 // Comparison instruction
570 //
571 // encodings:
572 // ins<c> <Rn>, <Rm>
573 //
574 // affects:
575 // CMP
576 T_THUMB_CMP,
577  
578 // info:
579 // Add a Register to the Stack Pointer
580 //
581 // encodings:
582 // ins<c> SP, <Rm>
583 //
584 // affects:
585 // ADD
586 T_THUMB_MOD_SP_REG,
587  
588 // info:
589 // Compare and Branch on (Non)Zero
590 //
591 // encodings:
592 // ins<c> <Rn>, <label>
593 //
594 // affects:
595 // CBZ
596 T_THUMB_CBZ,
597  
598 // info:
599 // Instructions that do not operate on a register
600 //
601 // encodings:
602 //
603 //
604 // affects:
605 //
606 T_THUMB2_NO_REG,
607  
608 // info:
609 // Instructions that operate on Rt register
610 //
611 // encodings:
612 //
613 //
614 // affects:
615 //
616 T_THUMB2_RT_REG,
617  
618 // info:
619 // Instructions that operate on Rt and Rt2 register
620 //
621 // encodings:
622 //
623 //
624 // affects:
625 //
626 T_THUMB2_RT_RT2_REG,
627  
628 // info:
629 // Instructions that operate on the Rm register
630 //
631 // encodings:
632 //
633 //
634 // affects:
635 //
636 T_THUMB2_RM_REG,
637  
638 // info:
639 // Instructions that operate on the Rd register
640 //
641 // encodings:
642 //
643 //
644 // affects:
645 //
646 T_THUMB2_RD_REG,
647  
648 // info:
649 // Instructions that operate on the Rd and Rm register
650 //
651 // encodings:
652 //
653 //
654 // affects:
655 //
656 T_THUMB2_RD_RM_REG,
657  
658 // info:
659 // Instructions that operate on the Rn register
660 //
661 // encodings:
662 //
663 //
664 // affects:
665 //
666 T_THUMB2_RN_REG,
667  
668 // info:
669 // Instructions that operate on the Rn and Rt register
670 //
671 // encodings:
672 //
673 //
674 // affects:
675 //
676 T_THUMB2_RN_RT_REG,
677  
678 // info:
679 // Instructions that operate on the Rn, Rt and Rt2 register
680 //
681 // encodings:
682 //
683 //
684 // affects:
685 //
686 T_THUMB2_RN_RT_RT2_REG,
687  
688 // info:
689 // Instructions that operate on the Rn and Rm register
690 //
691 // encodings:
692 //
693 //
694 // affects:
695 //
696 T_THUMB2_RN_RM_REG,
697  
698 // info:
699 // Instructions that operate on the Rn, Rm and Rt register
700 //
701 // encodings:
702 //
703 //
704 // affects:
705 //
706 T_THUMB2_RN_RM_RT_REG,
707  
708 // info:
709 // Instructions that operate on the Rn and Rd register
710 //
711 // encodings:
712 //
713 //
714 // affects:
715 //
716 T_THUMB2_RN_RD_REG,
717  
718 // info:
719 // Instructions that operate on the Rn, Rd and Rt register
720 //
721 // encodings:
722 //
723 //
724 // affects:
725 //
726 T_THUMB2_RN_RD_RT_REG,
727  
728 // info:
729 // Instructions that operate on the Rn, Rd, Rt and Rt2 register
730 //
731 // encodings:
732 //
733 //
734 // affects:
735 //
736 T_THUMB2_RN_RD_RT_RT2_REG,
737  
738 // info:
739 // Instructions that operate on the Rn, Rd and Rm register
740 //
741 // encodings:
742 //
743 //
744 // affects:
745 //
746 T_THUMB2_RN_RD_RM_REG,
747  
748 // info:
749 // Instructions that operate on the Rn, Rd, Rm and Ra register
750 //
751 // encodings:
752 //
753 //
754 // affects:
755 //
756 T_THUMB2_RN_RD_RM_RA_REG,
757  
758 // info:
759 // Instructions that do not operate on an immediate
760 //
761 // encodings:
762 //
763 //
764 // affects:
765 //
766 T_THUMB2_NO_IMM,
767  
768 // info:
769 // Instructions that use a 12 bit immediate
770 //
771 // encodings:
772 //
773 //
774 // affects:
775 //
776 T_THUMB2_IMM12,
777  
778 // info:
779 // Instructions that use an 8 bit immediate
780 //
781 // encodings:
782 //
783 //
784 // affects:
785 //
786 T_THUMB2_IMM8,
787  
788 // info:
789 // Instructions that use a 2 bit immediate
790 //
791 // encodings:
792 //
793 //
794 // affects:
795 //
796 T_THUMB2_IMM2,
797  
798 // info:
799 // Instructions that use a 2 and 3 bit immediate
800 //
801 // encodings:
802 //
803 //
804 // affects:
805 //
806 T_THUMB2_IMM2_IMM3,
807  
808 // info:
809 // Instructions that use a 1, 3 and 8 bit immediate
810 //
811 // encodings:
812 //
813 //
814 // affects:
815 //
816 T_THUMB2_IMM1_IMM3_IMM8,
817  
818 // info:
819 // Instructions that have no flags
820 //
821 // encodings:
822 //
823 //
824 // affects:
825 //
826 T_THUMB2_NO_FLAG,
827  
828 // info:
829 // Instructions that use the rotate flag
830 //
831 // encodings:
832 //
833 //
834 // affects:
835 //
836 T_THUMB2_ROTATE_FLAG,
837  
838 // info:
839 // Instructions that use the U flag
840 //
841 // encodings:
842 //
843 //
844 // affects:
845 //
846 T_THUMB2_U_FLAG,
847  
848 // info:
849 // Instructions that use the WUP flags
850 //
851 // encodings:
852 //
853 //
854 // affects:
855 //
856 T_THUMB2_WUP_FLAG,
857  
858 // info:
859 // Instructions that use the shift type flag
860 //
861 // encodings:
862 //
863 //
864 // affects:
865 //
866 T_THUMB2_TYPE_FLAG,
867  
868 // info:
869 // Instructions that use the register list
870 //
871 // encodings:
872 //
873 //
874 // affects:
875 //
876 T_THUMB2_REGLIST_FLAG,
877  
878 // info:
879 // Instructions that use the WP flags and register list
880 //
881 // encodings:
882 //
883 //
884 // affects:
885 //
886 T_THUMB2_WP_REGLIST_FLAG,
887  
888 // info:
889 // Instructions that use the S flag
890 //
891 // encodings:
892 //
893 //
894 // affects:
895 //
896 T_THUMB2_S_FLAG,
897  
898 // info:
899 // Instructions that use the S flag and shift type flag
900 //
901 // encodings:
902 //
903 //
904 // affects:
905 //
906 T_THUMB2_S_TYPE_FLAG,
907 } darm_enctype_t;
908  
909 typedef enum _darm_instr_t {
910 I_INVLD, I_ADC, I_ADD, I_ADDW, I_ADR, I_AND, I_ASR, I_B, I_BFC, I_BFI,
911 I_BIC, I_BKPT, I_BL, I_BLX, I_BX, I_BXJ, I_CBNZ, I_CBZ, I_CDP, I_CDP2,
912 I_CHKA, I_CLREX, I_CLZ, I_CMN, I_CMP, I_CPS, I_CPY, I_DBG, I_DMB, I_DSB,
913 I_ENTERX, I_EOR, I_HB, I_HBL, I_HBLP, I_HBP, I_ISB, I_IT, I_LDC, I_LDC2,
914 I_LDM, I_LDMDA, I_LDMDB, I_LDMIB, I_LDR, I_LDRB, I_LDRBT, I_LDRD, I_LDREX,
915 I_LDREXB, I_LDREXD, I_LDREXH, I_LDRH, I_LDRHT, I_LDRSB, I_LDRSBT, I_LDRSH,
916 I_LDRSHT, I_LDRT, I_LEAVEX, I_LSL, I_LSR, I_MCR, I_MCR2, I_MCRR, I_MCRR2,
917 I_MLA, I_MLS, I_MOV, I_MOVT, I_MOVW, I_MRC, I_MRC2, I_MRRC, I_MRRC2,
918 I_MRS, I_MSR, I_MUL, I_MVN, I_NEG, I_NOP, I_ORN, I_ORR, I_PKH, I_PLD,
919 I_PLDW, I_PLI, I_POP, I_PUSH, I_QADD, I_QADD16, I_QADD8, I_QASX, I_QDADD,
920 I_QDSUB, I_QSAX, I_QSUB, I_QSUB16, I_QSUB8, I_RBIT, I_REV, I_REV16,
921 I_REVSH, I_RFE, I_ROR, I_RRX, I_RSB, I_RSC, I_SADD16, I_SADD8, I_SASX,
922 I_SBC, I_SBFX, I_SDIV, I_SEL, I_SETEND, I_SEV, I_SHADD16, I_SHADD8,
923 I_SHASX, I_SHSAX, I_SHSUB16, I_SHSUB8, I_SMC, I_SMLA, I_SMLABB, I_SMLABT,
924 I_SMLAD, I_SMLAL, I_SMLALBB, I_SMLALBT, I_SMLALD, I_SMLALTB, I_SMLALTT,
925 I_SMLATB, I_SMLATT, I_SMLAW, I_SMLSD, I_SMLSLD, I_SMMLA, I_SMMLS, I_SMMUL,
926 I_SMUAD, I_SMUL, I_SMULBB, I_SMULBT, I_SMULL, I_SMULTB, I_SMULTT, I_SMULW,
927 I_SMUSD, I_SRS, I_SSAT, I_SSAT16, I_SSAX, I_SSUB16, I_SSUB8, I_STC,
928 I_STC2, I_STM, I_STMDA, I_STMDB, I_STMIB, I_STR, I_STRB, I_STRBT, I_STRD,
929 I_STREX, I_STREXB, I_STREXD, I_STREXH, I_STRH, I_STRHT, I_STRT, I_SUB,
930 I_SUBW, I_SVC, I_SWP, I_SWPB, I_SXTAB, I_SXTAB16, I_SXTAH, I_SXTB,
931 I_SXTB16, I_SXTH, I_TBB, I_TBH, I_TEQ, I_TST, I_UADD16, I_UADD8, I_UASX,
932 I_UBFX, I_UDF, I_UDIV, I_UHADD16, I_UHADD8, I_UHASX, I_UHSAX, I_UHSUB16,
933 I_UHSUB8, I_UMAAL, I_UMLAL, I_UMULL, I_UQADD16, I_UQADD8, I_UQASX,
934 I_UQSAX, I_UQSUB16, I_UQSUB8, I_USAD8, I_USADA8, I_USAT, I_USAT16, I_USAX,
935 I_USUB16, I_USUB8, I_UXTAB, I_UXTAB16, I_UXTAH, I_UXTB, I_UXTB16, I_UXTH,
936 I_VABA, I_VABAL, I_VABD, I_VABDL, I_VABS, I_VACGE, I_VACGT, I_VACLE,
937 I_VACLT, I_VADD, I_VADDHN, I_VADDL, I_VADDW, I_VAND, I_VBIC, I_VBIF,
938 I_VBIT, I_VBSL, I_VCEQ, I_VCGE, I_VCGT, I_VCLE, I_VCLS, I_VCLT, I_VCLZ,
939 I_VCMP, I_VCMPE, I_VCNT, I_VCVT, I_VCVTB, I_VCVTR, I_VCVTT, I_VDIV,
940 I_VDUP, I_VEOR, I_VEXT, I_VHADD, I_VHSUB, I_VLD1, I_VLD2, I_VLD3, I_VLD4,
941 I_VLDM, I_VLDR, I_VMAX, I_VMIN, I_VMLA, I_VMLAL, I_VMLS, I_VMLSL, I_VMOV,
942 I_VMOVL, I_VMOVN, I_VMRS, I_VMSR, I_VMUL, I_VMULL, I_VMVN, I_VNEG,
943 I_VNMLA, I_VNMLS, I_VNMUL, I_VORN, I_VORR, I_VPADAL, I_VPADD, I_VPADDL,
944 I_VPMAX, I_VPMIN, I_VPOP, I_VPUSH, I_VQABS, I_VQADD, I_VQDMLAL, I_VQDMLSL,
945 I_VQDMULH, I_VQDMULL, I_VQMOVN, I_VQMOVUN, I_VQNEG, I_VQRDMULH, I_VQRSHL,
946 I_VQRSHRN, I_VQRSHRUN, I_VQSHL, I_VQSHLU, I_VQSHRN, I_VQSHRUN, I_VQSUB,
947 I_VRADDHN, I_VRECPE, I_VRECPS, I_VREV16, I_VREV32, I_VREV64, I_VRHADD,
948 I_VRSHL, I_VRSHR, I_VRSHRN, I_VRSQRTE, I_VRSQRTS, I_VRSRA, I_VRSUBHN,
949 I_VSHL, I_VSHLL, I_VSHR, I_VSHRN, I_VSLI, I_VSQRT, I_VSRA, I_VSRI, I_VST1,
950 I_VST2, I_VST3, I_VST4, I_VSTM, I_VSTR, I_VSUB, I_VSUBHN, I_VSUBL,
951 I_VSUBW, I_VSWP, I_VTBL, I_VTBX, I_VTRN, I_VTST, I_VUZP, I_VZIP, I_WFE,
952 I_WFI, I_YIELD, I_INSTRCNT
953 } darm_instr_t;
954  
955 extern const char *darm_mnemonics[354];
956 extern const char *darm_enctypes[83];
957 extern const char *darm_registers[16];
958 #endif