OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Mon, 7 Dec 2015 17:16:50 +0100 |
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4 | Subject: [PATCH 52/53] pwm: add mediatek support |
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5 | |||
6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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7 | --- |
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8 | drivers/pwm/Kconfig | 9 +++ |
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9 | drivers/pwm/Makefile | 1 + |
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10 | drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ |
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11 | 3 files changed, 183 insertions(+) |
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12 | create mode 100644 drivers/pwm/pwm-mediatek.c |
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13 | |||
14 | --- a/drivers/pwm/Kconfig |
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15 | +++ b/drivers/pwm/Kconfig |
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16 | @@ -302,6 +302,15 @@ config PWM_MEDIATEK |
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17 | To compile this driver as a module, choose M here: the module |
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18 | will be called pwm-mediatek. |
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19 | |||
20 | +config PWM_MEDIATEK_RAMIPS |
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21 | + tristate "Mediatek PWM support" |
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22 | + depends on RALINK && OF |
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23 | + help |
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24 | + Generic PWM framework driver for Mediatek ARM SoC. |
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25 | + |
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26 | + To compile this driver as a module, choose M here: the module |
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27 | + will be called pwm-mxs. |
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28 | + |
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29 | config PWM_MXS |
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30 | tristate "Freescale MXS PWM support" |
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31 | depends on ARCH_MXS && OF |
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32 | --- a/drivers/pwm/Makefile |
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33 | +++ b/drivers/pwm/Makefile |
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34 | @@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p |
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35 | obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o |
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36 | obj-$(CONFIG_PWM_MESON) += pwm-meson.o |
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37 | obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o |
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38 | +obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o |
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39 | obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o |
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40 | obj-$(CONFIG_PWM_MXS) += pwm-mxs.o |
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41 | obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o |
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42 | --- /dev/null |
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43 | +++ b/drivers/pwm/pwm-mediatek-ramips.c |
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44 | @@ -0,0 +1,173 @@ |
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45 | +/* |
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46 | + * Mediatek Pulse Width Modulator driver |
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47 | + * |
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48 | + * Copyright (C) 2015 John Crispin <blogic@openwrt.org> |
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49 | + * |
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50 | + * This file is licensed under the terms of the GNU General Public |
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51 | + * License version 2. This program is licensed "as is" without any |
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52 | + * warranty of any kind, whether express or implied. |
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53 | + */ |
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54 | + |
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55 | +#include <linux/err.h> |
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56 | +#include <linux/io.h> |
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57 | +#include <linux/ioport.h> |
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58 | +#include <linux/kernel.h> |
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59 | +#include <linux/module.h> |
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60 | +#include <linux/of.h> |
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61 | +#include <linux/platform_device.h> |
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62 | +#include <linux/pwm.h> |
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63 | +#include <linux/slab.h> |
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64 | +#include <linux/types.h> |
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65 | + |
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66 | +#define NUM_PWM 4 |
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67 | + |
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68 | +/* PWM registers and bits definitions */ |
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69 | +#define PWMCON 0x00 |
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70 | +#define PWMHDUR 0x04 |
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71 | +#define PWMLDUR 0x08 |
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72 | +#define PWMGDUR 0x0c |
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73 | +#define PWMWAVENUM 0x28 |
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74 | +#define PWMDWIDTH 0x2c |
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75 | +#define PWMTHRES 0x30 |
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76 | + |
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77 | +/** |
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78 | + * struct mtk_pwm_chip - struct representing pwm chip |
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79 | + * |
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80 | + * @mmio_base: base address of pwm chip |
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81 | + * @chip: linux pwm chip representation |
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82 | + */ |
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83 | +struct mtk_pwm_chip { |
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84 | + void __iomem *mmio_base; |
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85 | + struct pwm_chip chip; |
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86 | +}; |
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87 | + |
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88 | +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) |
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89 | +{ |
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90 | + return container_of(chip, struct mtk_pwm_chip, chip); |
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91 | +} |
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92 | + |
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93 | +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, |
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94 | + unsigned long offset) |
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95 | +{ |
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96 | + return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset); |
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97 | +} |
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98 | + |
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99 | +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, |
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100 | + unsigned int num, unsigned long offset, |
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101 | + unsigned long val) |
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102 | +{ |
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103 | + iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset); |
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104 | +} |
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105 | + |
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106 | +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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107 | + int duty_ns, int period_ns) |
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108 | +{ |
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109 | + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); |
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110 | + u32 resolution = 100 / 4; |
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111 | + u32 clkdiv = 0; |
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112 | + |
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113 | + while (period_ns / resolution > 8191) { |
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114 | + clkdiv++; |
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115 | + resolution *= 2; |
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116 | + } |
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117 | + |
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118 | + if (clkdiv > 7) |
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119 | + return -1; |
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120 | + |
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121 | + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); |
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122 | + mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); |
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123 | + mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); |
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124 | + return 0; |
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125 | +} |
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126 | + |
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127 | +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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128 | +{ |
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129 | + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); |
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130 | + u32 val; |
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131 | + |
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132 | + val = ioread32(pc->mmio_base); |
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133 | + val |= BIT(pwm->hwpwm); |
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134 | + iowrite32(val, pc->mmio_base); |
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135 | + |
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136 | + return 0; |
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137 | +} |
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138 | + |
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139 | +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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140 | +{ |
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141 | + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); |
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142 | + u32 val; |
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143 | + |
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144 | + val = ioread32(pc->mmio_base); |
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145 | + val &= ~BIT(pwm->hwpwm); |
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146 | + iowrite32(val, pc->mmio_base); |
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147 | +} |
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148 | + |
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149 | +static const struct pwm_ops mtk_pwm_ops = { |
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150 | + .config = mtk_pwm_config, |
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151 | + .enable = mtk_pwm_enable, |
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152 | + .disable = mtk_pwm_disable, |
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153 | + .owner = THIS_MODULE, |
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154 | +}; |
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155 | + |
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156 | +static int mtk_pwm_probe(struct platform_device *pdev) |
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157 | +{ |
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158 | + struct mtk_pwm_chip *pc; |
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159 | + struct resource *r; |
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160 | + int ret; |
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161 | + |
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162 | + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
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163 | + if (!pc) |
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164 | + return -ENOMEM; |
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165 | + |
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166 | + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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167 | + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
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168 | + if (IS_ERR(pc->mmio_base)) |
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169 | + return PTR_ERR(pc->mmio_base); |
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170 | + |
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171 | + platform_set_drvdata(pdev, pc); |
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172 | + |
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173 | + pc->chip.dev = &pdev->dev; |
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174 | + pc->chip.ops = &mtk_pwm_ops; |
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175 | + pc->chip.base = -1; |
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176 | + pc->chip.npwm = NUM_PWM; |
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177 | + |
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178 | + ret = pwmchip_add(&pc->chip); |
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179 | + if (ret < 0) |
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180 | + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
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181 | + |
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182 | + return ret; |
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183 | +} |
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184 | + |
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185 | +static int mtk_pwm_remove(struct platform_device *pdev) |
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186 | +{ |
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187 | + struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); |
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188 | + int i; |
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189 | + |
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190 | + for (i = 0; i < NUM_PWM; i++) |
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191 | + pwm_disable(&pc->chip.pwms[i]); |
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192 | + |
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193 | + return pwmchip_remove(&pc->chip); |
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194 | +} |
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195 | + |
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196 | +static const struct of_device_id mtk_pwm_of_match[] = { |
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197 | + { .compatible = "mediatek,mt7628-pwm" }, |
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198 | + { } |
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199 | +}; |
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200 | + |
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201 | +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); |
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202 | + |
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203 | +static struct platform_driver mtk_pwm_driver = { |
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204 | + .driver = { |
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205 | + .name = "mtk-pwm", |
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206 | + .owner = THIS_MODULE, |
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207 | + .of_match_table = mtk_pwm_of_match, |
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208 | + }, |
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209 | + .probe = mtk_pwm_probe, |
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210 | + .remove = mtk_pwm_remove, |
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211 | +}; |
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212 | + |
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213 | +module_platform_driver(mtk_pwm_driver); |
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214 | + |
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215 | +MODULE_LICENSE("GPL"); |
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216 | +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
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217 | +MODULE_ALIAS("platform:mtk-pwm"); |