OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:31:47 +0100
4 Subject: [PATCH 48/53] asoc: add mt7620 support
5  
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/ralink/of.c | 2 +
9 sound/soc/Kconfig | 1 +
10 sound/soc/Makefile | 1 +
11 sound/soc/ralink/Kconfig | 15 ++
12 sound/soc/ralink/Makefile | 11 +
13 sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
14 sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
15 7 files changed, 699 insertions(+)
16 create mode 100644 sound/soc/ralink/Kconfig
17 create mode 100644 sound/soc/ralink/Makefile
18 create mode 100644 sound/soc/ralink/mt7620-i2s.c
19 create mode 100644 sound/soc/ralink/mt7620-wm8960.c
20  
21 --- a/arch/mips/ralink/of.c
22 +++ b/arch/mips/ralink/of.c
23 @@ -15,6 +15,7 @@
24 #include <linux/of_fdt.h>
25 #include <linux/kernel.h>
26 #include <linux/bootmem.h>
27 +#include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/of_address.h>
30  
31 @@ -26,6 +27,7 @@
32 #include "common.h"
33  
34 __iomem void *rt_sysc_membase;
35 +EXPORT_SYMBOL(rt_sysc_membase);
36 __iomem void *rt_memc_membase;
37  
38 __iomem void *plat_of_remap_node(const char *node)
39 --- a/sound/soc/Kconfig
40 +++ b/sound/soc/Kconfig
41 @@ -59,6 +59,7 @@ source "sound/soc/mxs/Kconfig"
42 source "sound/soc/pxa/Kconfig"
43 source "sound/soc/qcom/Kconfig"
44 source "sound/soc/rockchip/Kconfig"
45 +source "sound/soc/ralink/Kconfig"
46 source "sound/soc/samsung/Kconfig"
47 source "sound/soc/sh/Kconfig"
48 source "sound/soc/sirf/Kconfig"
49 --- a/sound/soc/Makefile
50 +++ b/sound/soc/Makefile
51 @@ -40,6 +40,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
52 obj-$(CONFIG_SND_SOC) += pxa/
53 obj-$(CONFIG_SND_SOC) += qcom/
54 obj-$(CONFIG_SND_SOC) += rockchip/
55 +obj-$(CONFIG_SND_SOC) += ralink/
56 obj-$(CONFIG_SND_SOC) += samsung/
57 obj-$(CONFIG_SND_SOC) += sh/
58 obj-$(CONFIG_SND_SOC) += sirf/
59 --- /dev/null
60 +++ b/sound/soc/ralink/Kconfig
61 @@ -0,0 +1,8 @@
62 +config SND_RALINK_SOC_I2S
63 + depends on RALINK && SND_SOC && !SOC_RT288X
64 + select SND_SOC_GENERIC_DMAENGINE_PCM
65 + select REGMAP_MMIO
66 + tristate "SoC Audio (I2S protocol) for Ralink SoC"
67 + help
68 + Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
69 + based boards.
70 --- /dev/null
71 +++ b/sound/soc/ralink/Makefile
72 @@ -0,0 +1,6 @@
73 +#
74 +# Ralink/MediaTek Platform Support
75 +#
76 +snd-soc-ralink-i2s-objs := ralink-i2s.o
77 +
78 +obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
79 --- /dev/null
80 +++ b/sound/soc/ralink/ralink-i2s.c
81 @@ -0,0 +1,965 @@
82 +/*
83 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
84 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
85 + *
86 + * This program is free software; you can redistribute it and/or modify it
87 + * under the terms of the GNU General Public License as published by the
88 + * Free Software Foundation; either version 2 of the License, or (at your
89 + * option) any later version.
90 + *
91 + * You should have received a copy of the GNU General Public License along
92 + * with this program; if not, write to the Free Software Foundation, Inc.,
93 + * 675 Mass Ave, Cambridge, MA 02139, USA.
94 + *
95 + */
96 +
97 +#include <linux/module.h>
98 +#include <linux/platform_device.h>
99 +#include <linux/clk.h>
100 +#include <linux/regmap.h>
101 +#include <linux/reset.h>
102 +#include <linux/debugfs.h>
103 +#include <linux/of_device.h>
104 +#include <sound/pcm_params.h>
105 +#include <sound/dmaengine_pcm.h>
106 +
107 +#include <asm/mach-ralink/ralink_regs.h>
108 +
109 +#define DRV_NAME "ralink-i2s"
110 +
111 +#define I2S_REG_CFG0 0x00
112 +#define I2S_REG_INT_STATUS 0x04
113 +#define I2S_REG_INT_EN 0x08
114 +#define I2S_REG_FF_STATUS 0x0c
115 +#define I2S_REG_WREG 0x10
116 +#define I2S_REG_RREG 0x14
117 +#define I2S_REG_CFG1 0x18
118 +#define I2S_REG_DIVCMP 0x20
119 +#define I2S_REG_DIVINT 0x24
120 +
121 +/* I2S_REG_CFG0 */
122 +#define I2S_REG_CFG0_EN BIT(31)
123 +#define I2S_REG_CFG0_DMA_EN BIT(30)
124 +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
125 +#define I2S_REG_CFG0_TX_EN BIT(24)
126 +#define I2S_REG_CFG0_RX_EN BIT(20)
127 +#define I2S_REG_CFG0_SLAVE BIT(16)
128 +#define I2S_REG_CFG0_RX_THRES 12
129 +#define I2S_REG_CFG0_TX_THRES 4
130 +#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \
131 + (4 << I2S_REG_CFG0_TX_THRES)
132 +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
133 + (4 << I2S_REG_CFG0_TX_THRES)
134 +/* RT305x */
135 +#define I2S_REG_CFG0_CLK_DIS BIT(8)
136 +#define I2S_REG_CFG0_TXCH_SWAP BIT(3)
137 +#define I2S_REG_CFG0_TXCH1_OFF BIT(2)
138 +#define I2S_REG_CFG0_TXCH0_OFF BIT(1)
139 +#define I2S_REG_CFG0_SLAVE_EN BIT(0)
140 +/* RT3883 */
141 +#define I2S_REG_CFG0_RXCH_SWAP BIT(11)
142 +#define I2S_REG_CFG0_RXCH1_OFF BIT(10)
143 +#define I2S_REG_CFG0_RXCH0_OFF BIT(9)
144 +#define I2S_REG_CFG0_WS_INV BIT(0)
145 +/* MT7628 */
146 +#define I2S_REG_CFG0_FMT_LE BIT(29)
147 +#define I2S_REG_CFG0_SYS_BE BIT(28)
148 +#define I2S_REG_CFG0_NORM_24 BIT(18)
149 +#define I2S_REG_CFG0_DATA_24 BIT(17)
150 +
151 +/* I2S_REG_INT_STATUS */
152 +#define I2S_REG_INT_RX_FAULT BIT(7)
153 +#define I2S_REG_INT_RX_OVRUN BIT(6)
154 +#define I2S_REG_INT_RX_UNRUN BIT(5)
155 +#define I2S_REG_INT_RX_THRES BIT(4)
156 +#define I2S_REG_INT_TX_FAULT BIT(3)
157 +#define I2S_REG_INT_TX_OVRUN BIT(2)
158 +#define I2S_REG_INT_TX_UNRUN BIT(1)
159 +#define I2S_REG_INT_TX_THRES BIT(0)
160 +#define I2S_REG_INT_TX_MASK 0xf
161 +#define I2S_REG_INT_RX_MASK 0xf0
162 +
163 +/* I2S_REG_INT_STATUS */
164 +#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf)
165 +#define I2S_TX_AVCNT(x) (x & 0xf)
166 +/* MT7628 */
167 +#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f)
168 +#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f)
169 +
170 +/* I2S_REG_CFG1 */
171 +#define I2S_REG_CFG1_LBK BIT(31)
172 +#define I2S_REG_CFG1_EXTLBK BIT(30)
173 +/* RT3883 */
174 +#define I2S_REG_CFG1_LEFT_J BIT(0)
175 +#define I2S_REG_CFG1_RIGHT_J BIT(1)
176 +#define I2S_REG_CFG1_FMT_MASK 0x3
177 +
178 +/* I2S_REG_DIVCMP */
179 +#define I2S_REG_DIVCMP_CLKEN BIT(31)
180 +#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff
181 +
182 +/* I2S_REG_DIVINT */
183 +#define I2S_REG_DIVINT_MASK 0x3ff
184 +
185 +/* BCLK dividers */
186 +#define RALINK_I2S_DIVCMP 0
187 +#define RALINK_I2S_DIVINT 1
188 +
189 +/* FIFO */
190 +#define RALINK_I2S_FIFO_SIZE 32
191 +
192 +/* feature flags */
193 +#define RALINK_FLAGS_TXONLY BIT(0)
194 +#define RALINK_FLAGS_LEFT_J BIT(1)
195 +#define RALINK_FLAGS_RIGHT_J BIT(2)
196 +#define RALINK_FLAGS_ENDIAN BIT(3)
197 +#define RALINK_FLAGS_24BIT BIT(4)
198 +
199 +#define RALINK_I2S_INT_EN 0
200 +
201 +struct ralink_i2s_stats {
202 + u32 dmafault;
203 + u32 overrun;
204 + u32 underrun;
205 + u32 belowthres;
206 +};
207 +
208 +struct ralink_i2s {
209 + struct device *dev;
210 + void __iomem *regs;
211 + struct clk *clk;
212 + struct regmap *regmap;
213 + u32 flags;
214 + unsigned int fmt;
215 + u16 txdma_req;
216 + u16 rxdma_req;
217 +
218 + struct snd_dmaengine_dai_dma_data playback_dma_data;
219 + struct snd_dmaengine_dai_dma_data capture_dma_data;
220 +
221 + struct dentry *dbg_dir;
222 + struct dentry *dbg_stats;
223 + struct ralink_i2s_stats txstats;
224 + struct ralink_i2s_stats rxstats;
225 +};
226 +
227 +static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
228 +{
229 + u32 buf[10];
230 + int ret;
231 +
232 + ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
233 + buf, ARRAY_SIZE(buf));
234 +
235 + dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
236 + "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
237 + "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
238 + buf[0], buf[1], buf[2], buf[3], buf[4],
239 + buf[5], buf[6], buf[8], buf[9]);
240 +}
241 +
242 +static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
243 + int clk_id, unsigned int freq, int dir)
244 +{
245 + return 0;
246 +}
247 +
248 +static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
249 +{
250 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
251 + unsigned long clk = clk_get_rate(i2s->clk);
252 + int div;
253 + uint32_t data;
254 +
255 + /* disable clock at slave mode */
256 + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
257 + SND_SOC_DAIFMT_CBM_CFM) {
258 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
259 + I2S_REG_CFG0_CLK_DIS,
260 + I2S_REG_CFG0_CLK_DIS);
261 + return 0;
262 + }
263 +
264 + /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
265 + div = (clk / rate ) - 1;
266 +
267 + data = rt_sysc_r32(0x30);
268 + data &= (0xff << 8);
269 + data |= (0x1 << 15) | (div << 8);
270 + rt_sysc_w32(data, 0x30);
271 +
272 + /* enable clock */
273 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
274 +
275 + dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
276 + clk, rate, div);
277 +
278 + return 0;
279 +}
280 +
281 +static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
282 +{
283 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
284 + unsigned long clk = clk_get_rate(i2s->clk);
285 + int divint, divcomp;
286 +
287 + /* disable clock at slave mode */
288 + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
289 + SND_SOC_DAIFMT_CBM_CFM) {
290 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
291 + I2S_REG_DIVCMP_CLKEN, 0);
292 + return 0;
293 + }
294 +
295 + /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
296 + clk = clk / (2 * 2 * width);
297 + divint = clk / rate;
298 + divcomp = ((clk % rate) * 512) / rate;
299 +
300 + if ((divint > I2S_REG_DIVINT_MASK) ||
301 + (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
302 + return -EINVAL;
303 +
304 + regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
305 + I2S_REG_DIVINT_MASK, divint);
306 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
307 + I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
308 +
309 + /* enable clock */
310 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
311 + I2S_REG_DIVCMP_CLKEN);
312 +
313 + dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
314 + clk_get_rate(i2s->clk), rate, divint, divcomp);
315 +
316 + return 0;
317 +}
318 +
319 +static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
320 +{
321 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
322 + unsigned int cfg0 = 0, cfg1 = 0;
323 +
324 + /* set master/slave audio interface */
325 + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
326 + case SND_SOC_DAIFMT_CBM_CFM:
327 + if (i2s->flags & RALINK_FLAGS_TXONLY)
328 + cfg0 |= I2S_REG_CFG0_SLAVE_EN;
329 + else
330 + cfg0 |= I2S_REG_CFG0_SLAVE;
331 + break;
332 + case SND_SOC_DAIFMT_CBS_CFS:
333 + break;
334 + default:
335 + return -EINVAL;
336 + }
337 +
338 + /* interface format */
339 + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
340 + case SND_SOC_DAIFMT_I2S:
341 + break;
342 + case SND_SOC_DAIFMT_RIGHT_J:
343 + if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
344 + cfg1 |= I2S_REG_CFG1_RIGHT_J;
345 + break;
346 + }
347 + return -EINVAL;
348 + case SND_SOC_DAIFMT_LEFT_J:
349 + if (i2s->flags & RALINK_FLAGS_LEFT_J) {
350 + cfg1 |= I2S_REG_CFG1_LEFT_J;
351 + break;
352 + }
353 + return -EINVAL;
354 + default:
355 + return -EINVAL;
356 + }
357 +
358 + /* clock inversion */
359 + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
360 + case SND_SOC_DAIFMT_NB_NF:
361 + break;
362 + default:
363 + return -EINVAL;
364 + }
365 +
366 + if (i2s->flags & RALINK_FLAGS_TXONLY) {
367 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
368 + I2S_REG_CFG0_SLAVE_EN, cfg0);
369 + } else {
370 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
371 + I2S_REG_CFG0_SLAVE, cfg0);
372 + }
373 + regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
374 + I2S_REG_CFG1_FMT_MASK, cfg1);
375 + i2s->fmt = fmt;
376 +
377 + return 0;
378 +}
379 +
380 +static int ralink_i2s_startup(struct snd_pcm_substream *substream,
381 + struct snd_soc_dai *dai)
382 +{
383 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
384 +
385 + if (dai->active)
386 + return 0;
387 +
388 + /* setup status interrupt */
389 +#if (RALINK_I2S_INT_EN)
390 + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
391 +#else
392 + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
393 +#endif
394 +
395 + /* enable */
396 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
397 + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
398 + I2S_REG_CFG0_THRES_MASK,
399 + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
400 + I2S_REG_CFG0_DFT_THRES);
401 +
402 + return 0;
403 +}
404 +
405 +static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
406 + struct snd_soc_dai *dai)
407 +{
408 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
409 +
410 + /* If both streams are stopped, disable module and clock */
411 + if (dai->active)
412 + return;
413 +
414 + /*
415 + * datasheet mention when disable all control regs are cleared
416 + * to initial values. need reinit at startup.
417 + */
418 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
419 +}
420 +
421 +static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
422 + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
423 +{
424 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
425 + int width;
426 + int ret;
427 +
428 + width = params_width(params);
429 + switch (width) {
430 + case 16:
431 + if (i2s->flags & RALINK_FLAGS_24BIT)
432 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
433 + I2S_REG_CFG0_DATA_24, 0);
434 + break;
435 + case 24:
436 + if (i2s->flags & RALINK_FLAGS_24BIT) {
437 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
438 + I2S_REG_CFG0_DATA_24,
439 + I2S_REG_CFG0_DATA_24);
440 + break;
441 + }
442 + return -EINVAL;
443 + default:
444 + return -EINVAL;
445 + }
446 +
447 + switch (params_channels(params)) {
448 + case 2:
449 + break;
450 + default:
451 + return -EINVAL;
452 + }
453 +
454 + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
455 + /* system endian */
456 +#ifdef SNDRV_LITTLE_ENDIAN
457 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
458 + I2S_REG_CFG0_SYS_BE, 0);
459 +#else
460 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
461 + I2S_REG_CFG0_SYS_BE,
462 + I2S_REG_CFG0_SYS_BE);
463 +#endif
464 +
465 + /* data endian */
466 + switch (params_format(params)) {
467 + case SNDRV_PCM_FORMAT_S16_LE:
468 + case SNDRV_PCM_FORMAT_S24_LE:
469 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
470 + I2S_REG_CFG0_FMT_LE,
471 + I2S_REG_CFG0_FMT_LE);
472 + break;
473 + case SNDRV_PCM_FORMAT_S16_BE:
474 + case SNDRV_PCM_FORMAT_S24_BE:
475 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
476 + I2S_REG_CFG0_FMT_LE, 0);
477 + break;
478 + default:
479 + return -EINVAL;
480 + }
481 + }
482 +
483 + /* setup bclk rate */
484 + if (i2s->flags & RALINK_FLAGS_TXONLY)
485 + ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
486 + else
487 + ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
488 +
489 + return ret;
490 +}
491 +
492 +static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
493 + struct snd_soc_dai *dai)
494 +{
495 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
496 + unsigned int mask, val;
497 +
498 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
499 + mask = I2S_REG_CFG0_TX_EN;
500 + else
501 + mask = I2S_REG_CFG0_RX_EN;
502 +
503 + switch (cmd) {
504 + case SNDRV_PCM_TRIGGER_START:
505 + case SNDRV_PCM_TRIGGER_RESUME:
506 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
507 + val = mask;
508 + break;
509 + case SNDRV_PCM_TRIGGER_STOP:
510 + case SNDRV_PCM_TRIGGER_SUSPEND:
511 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
512 + val = 0;
513 + break;
514 + default:
515 + return -EINVAL;
516 + }
517 +
518 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
519 +
520 + return 0;
521 +}
522 +
523 +static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
524 + struct resource *res)
525 +{
526 + struct snd_dmaengine_dai_dma_data *dma_data;
527 +
528 + /* Playback */
529 + dma_data = &i2s->playback_dma_data;
530 + dma_data->addr = res->start + I2S_REG_WREG;
531 + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
532 + dma_data->maxburst = 1;
533 + dma_data->slave_id = i2s->txdma_req;
534 +
535 + if (i2s->flags & RALINK_FLAGS_TXONLY)
536 + return;
537 +
538 + /* Capture */
539 + dma_data = &i2s->capture_dma_data;
540 + dma_data->addr = res->start + I2S_REG_RREG;
541 + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
542 + dma_data->maxburst = 1;
543 + dma_data->slave_id = i2s->rxdma_req;
544 +}
545 +
546 +static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
547 +{
548 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
549 +
550 + snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
551 + &i2s->capture_dma_data);
552 +
553 + return 0;
554 +}
555 +
556 +static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
557 +{
558 + return 0;
559 +}
560 +
561 +static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
562 + .set_sysclk = ralink_i2s_set_sysclk,
563 + .set_fmt = ralink_i2s_set_fmt,
564 + .startup = ralink_i2s_startup,
565 + .shutdown = ralink_i2s_shutdown,
566 + .hw_params = ralink_i2s_hw_params,
567 + .trigger = ralink_i2s_trigger,
568 +};
569 +
570 +static struct snd_soc_dai_driver ralink_i2s_dai = {
571 + .name = DRV_NAME,
572 + .probe = ralink_i2s_dai_probe,
573 + .remove = ralink_i2s_dai_remove,
574 + .ops = &ralink_i2s_dai_ops,
575 + .capture = {
576 + .stream_name = "I2S Capture",
577 + .channels_min = 2,
578 + .channels_max = 2,
579 + .rate_min = 5512,
580 + .rate_max = 192000,
581 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
582 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
583 + },
584 + .playback = {
585 + .stream_name = "I2S Playback",
586 + .channels_min = 2,
587 + .channels_max = 2,
588 + .rate_min = 5512,
589 + .rate_max = 192000,
590 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
591 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
592 + },
593 + .symmetric_rates = 1,
594 +};
595 +
596 +static struct snd_pcm_hardware ralink_pcm_hardware = {
597 + .info = SNDRV_PCM_INFO_MMAP |
598 + SNDRV_PCM_INFO_MMAP_VALID |
599 + SNDRV_PCM_INFO_INTERLEAVED |
600 + SNDRV_PCM_INFO_BLOCK_TRANSFER,
601 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
602 + .channels_min = 2,
603 + .channels_max = 2,
604 + .period_bytes_min = PAGE_SIZE,
605 + .period_bytes_max = PAGE_SIZE * 2,
606 + .periods_min = 2,
607 + .periods_max = 128,
608 + .buffer_bytes_max = 128 * 1024,
609 + .fifo_size = RALINK_I2S_FIFO_SIZE,
610 +};
611 +
612 +static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
613 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
614 + .pcm_hardware = &ralink_pcm_hardware,
615 + .prealloc_buffer_size = 256 * PAGE_SIZE,
616 +};
617 +
618 +static const struct snd_soc_component_driver ralink_i2s_component = {
619 + .name = DRV_NAME,
620 +};
621 +
622 +static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
623 +{
624 + return true;
625 +}
626 +
627 +static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
628 +{
629 + switch (reg) {
630 + case I2S_REG_INT_STATUS:
631 + case I2S_REG_FF_STATUS:
632 + return true;
633 + }
634 + return false;
635 +}
636 +
637 +static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
638 +{
639 + switch (reg) {
640 + case I2S_REG_FF_STATUS:
641 + case I2S_REG_RREG:
642 + return false;
643 + }
644 + return true;
645 +}
646 +
647 +static const struct regmap_config ralink_i2s_regmap_config = {
648 + .reg_bits = 32,
649 + .reg_stride = 4,
650 + .val_bits = 32,
651 + .writeable_reg = ralink_i2s_writeable_reg,
652 + .readable_reg = ralink_i2s_readable_reg,
653 + .volatile_reg = ralink_i2s_volatile_reg,
654 + .max_register = I2S_REG_DIVINT,
655 +};
656 +
657 +#if (RALINK_I2S_INT_EN)
658 +static irqreturn_t ralink_i2s_irq(int irq, void *devid)
659 +{
660 + struct ralink_i2s *i2s = devid;
661 + u32 status;
662 +
663 + regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
664 + if (unlikely(!status))
665 + return IRQ_NONE;
666 +
667 + /* tx stats */
668 + if (status & I2S_REG_INT_TX_MASK) {
669 + if (status & I2S_REG_INT_TX_THRES)
670 + i2s->txstats.belowthres++;
671 + if (status & I2S_REG_INT_TX_UNRUN)
672 + i2s->txstats.underrun++;
673 + if (status & I2S_REG_INT_TX_OVRUN)
674 + i2s->txstats.overrun++;
675 + if (status & I2S_REG_INT_TX_FAULT)
676 + i2s->txstats.dmafault++;
677 + }
678 +
679 + /* rx stats */
680 + if (status & I2S_REG_INT_RX_MASK) {
681 + if (status & I2S_REG_INT_RX_THRES)
682 + i2s->rxstats.belowthres++;
683 + if (status & I2S_REG_INT_RX_UNRUN)
684 + i2s->rxstats.underrun++;
685 + if (status & I2S_REG_INT_RX_OVRUN)
686 + i2s->rxstats.overrun++;
687 + if (status & I2S_REG_INT_RX_FAULT)
688 + i2s->rxstats.dmafault++;
689 + }
690 +
691 + /* clean status bits */
692 + regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
693 +
694 + return IRQ_HANDLED;
695 +}
696 +#endif
697 +
698 +#if IS_ENABLED(CONFIG_DEBUG_FS)
699 +static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
700 +{
701 + struct ralink_i2s *i2s = s->private;
702 +
703 + seq_printf(s, "tx stats\n");
704 + seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
705 + seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
706 + seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
707 + seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
708 +
709 + seq_printf(s, "rx stats\n");
710 + seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
711 + seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
712 + seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
713 + seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
714 +
715 + ralink_i2s_dump_regs(i2s);
716 +
717 + return 0;
718 +}
719 +
720 +static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
721 +{
722 + return single_open(file, ralink_i2s_stats_show, inode->i_private);
723 +}
724 +
725 +static const struct file_operations ralink_i2s_stats_ops = {
726 + .open = ralink_i2s_stats_open,
727 + .read = seq_read,
728 + .llseek = seq_lseek,
729 + .release = single_release,
730 +};
731 +
732 +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
733 +{
734 + i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
735 + if (!i2s->dbg_dir)
736 + return -ENOMEM;
737 +
738 + i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
739 + i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
740 + if (!i2s->dbg_stats) {
741 + debugfs_remove(i2s->dbg_dir);
742 + return -ENOMEM;
743 + }
744 +
745 + return 0;
746 +}
747 +
748 +static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
749 +{
750 + debugfs_remove(i2s->dbg_stats);
751 + debugfs_remove(i2s->dbg_dir);
752 +}
753 +#else
754 +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
755 +{
756 + return 0;
757 +}
758 +
759 +static inline void ralink_i2s_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
760 +{
761 +}
762 +#endif
763 +
764 +/*
765 + * TODO: these refclk setup functions should use
766 + * clock framework instead. hardcode it now.
767 + */
768 +static void rt3350_refclk_setup(void)
769 +{
770 + uint32_t data;
771 +
772 + /* set refclk output 12Mhz clock */
773 + data = rt_sysc_r32(0x2c);
774 + data |= (0x1 << 8);
775 + rt_sysc_w32(data, 0x2c);
776 +}
777 +
778 +static void rt3883_refclk_setup(void)
779 +{
780 + uint32_t data;
781 +
782 + /* set refclk output 12Mhz clock */
783 + data = rt_sysc_r32(0x2c);
784 + data &= ~(0x3 << 13);
785 + data |= (0x1 << 13);
786 + rt_sysc_w32(data, 0x2c);
787 +}
788 +
789 +static void rt3552_refclk_setup(void)
790 +{
791 + uint32_t data;
792 +
793 + /* set refclk output 12Mhz clock */
794 + data = rt_sysc_r32(0x2c);
795 + data &= ~(0xf << 8);
796 + data |= (0x3 << 8);
797 + rt_sysc_w32(data, 0x2c);
798 +}
799 +
800 +static void mt7620_refclk_setup(void)
801 +{
802 + uint32_t data;
803 +
804 + /* set refclk output 12Mhz clock */
805 + data = rt_sysc_r32(0x2c);
806 + data &= ~(0x7 << 9);
807 + data |= 0x1 << 9;
808 + rt_sysc_w32(data, 0x2c);
809 +}
810 +
811 +static void mt7621_refclk_setup(void)
812 +{
813 + uint32_t data;
814 +
815 + /* set refclk output 12Mhz clock */
816 + data = rt_sysc_r32(0x2c);
817 + data &= ~(0x1f << 18);
818 + data |= (0x19 << 18);
819 + data &= ~(0x1f << 12);
820 + data |= (0x1 << 12);
821 + data &= ~(0x7 << 9);
822 + data |= (0x5 << 9);
823 + rt_sysc_w32(data, 0x2c);
824 +}
825 +
826 +static void mt7628_refclk_setup(void)
827 +{
828 + uint32_t data;
829 +
830 + /* set i2s and refclk digital pad */
831 + data = rt_sysc_r32(0x3c);
832 + data |= 0x1f;
833 + rt_sysc_w32(data, 0x3c);
834 +
835 + /* Adjust REFCLK0's driving strength */
836 + data = rt_sysc_r32(0x1354);
837 + data &= ~(0x1 << 5);
838 + rt_sysc_w32(data, 0x1354);
839 + data = rt_sysc_r32(0x1364);
840 + data |= ~(0x1 << 5);
841 + rt_sysc_w32(data, 0x1364);
842 +
843 + /* set refclk output 12Mhz clock */
844 + data = rt_sysc_r32(0x2c);
845 + data &= ~(0x7 << 9);
846 + data |= 0x1 << 9;
847 + rt_sysc_w32(data, 0x2c);
848 +}
849 +
850 +struct rt_i2s_data {
851 + u32 flags;
852 + void (*refclk_setup)(void);
853 +};
854 +
855 +struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
856 +struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
857 + .refclk_setup = rt3350_refclk_setup };
858 +struct rt_i2s_data rt3883_i2s_data = {
859 + .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
860 + .refclk_setup = rt3883_refclk_setup };
861 +struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
862 +struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
863 +struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
864 +struct rt_i2s_data mt7628_i2s_data = {
865 + .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
866 + RALINK_FLAGS_LEFT_J),
867 + .refclk_setup = mt7628_refclk_setup};
868 +
869 +static const struct of_device_id ralink_i2s_match_table[] = {
870 + { .compatible = "ralink,rt3050-i2s",
871 + .data = (void *)&rt3050_i2s_data },
872 + { .compatible = "ralink,rt3350-i2s",
873 + .data = (void *)&rt3350_i2s_data },
874 + { .compatible = "ralink,rt3883-i2s",
875 + .data = (void *)&rt3883_i2s_data },
876 + { .compatible = "ralink,rt3352-i2s",
877 + .data = (void *)&rt3352_i2s_data },
878 + { .compatible = "mediatek,mt7620-i2s",
879 + .data = (void *)&mt7620_i2s_data },
880 + { .compatible = "mediatek,mt7621-i2s",
881 + .data = (void *)&mt7621_i2s_data },
882 + { .compatible = "mediatek,mt7628-i2s",
883 + .data = (void *)&mt7628_i2s_data },
884 +};
885 +MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
886 +
887 +static int ralink_i2s_probe(struct platform_device *pdev)
888 +{
889 + const struct of_device_id *match;
890 + struct device_node *np = pdev->dev.of_node;
891 + struct ralink_i2s *i2s;
892 + struct resource *res;
893 + int irq, ret;
894 + u32 dma_req;
895 + struct rt_i2s_data *data;
896 +
897 + i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
898 + if (!i2s)
899 + return -ENOMEM;
900 +
901 + platform_set_drvdata(pdev, i2s);
902 + i2s->dev = &pdev->dev;
903 +
904 + match = of_match_device(ralink_i2s_match_table, &pdev->dev);
905 + if (!match)
906 + return -EINVAL;
907 + data = (struct rt_i2s_data *)match->data;
908 + i2s->flags = data->flags;
909 + /* setup out 12Mhz refclk to codec as mclk */
910 + if (data->refclk_setup)
911 + data->refclk_setup();
912 +
913 + if (of_property_read_u32(np, "txdma-req", &dma_req)) {
914 + dev_err(&pdev->dev, "no txdma-req define\n");
915 + return -EINVAL;
916 + }
917 + i2s->txdma_req = (u16)dma_req;
918 + if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
919 + if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
920 + dev_err(&pdev->dev, "no rxdma-req define\n");
921 + return -EINVAL;
922 + }
923 + i2s->rxdma_req = (u16)dma_req;
924 + }
925 +
926 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 + i2s->regs = devm_ioremap_resource(&pdev->dev, res);
928 + if (IS_ERR(i2s->regs))
929 + return PTR_ERR(i2s->regs);
930 +
931 + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
932 + &ralink_i2s_regmap_config);
933 + if (IS_ERR(i2s->regmap)) {
934 + dev_err(&pdev->dev, "regmap init failed\n");
935 + return PTR_ERR(i2s->regmap);
936 + }
937 +
938 + irq = platform_get_irq(pdev, 0);
939 + if (irq < 0) {
940 + dev_err(&pdev->dev, "failed to get irq\n");
941 + return -EINVAL;
942 + }
943 +
944 +#if (RALINK_I2S_INT_EN)
945 + ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
946 + 0, dev_name(&pdev->dev), i2s);
947 + if (ret) {
948 + dev_err(&pdev->dev, "failed to request irq\n");
949 + return ret;
950 + }
951 +#endif
952 +
953 + i2s->clk = devm_clk_get(&pdev->dev, NULL);
954 + if (IS_ERR(i2s->clk)) {
955 + dev_err(&pdev->dev, "no clock defined\n");
956 + return PTR_ERR(i2s->clk);
957 + }
958 +
959 + ret = clk_prepare_enable(i2s->clk);
960 + if (ret)
961 + return ret;
962 +
963 + ralink_i2s_init_dma_data(i2s, res);
964 +
965 + device_reset(&pdev->dev);
966 +
967 + ret = ralink_i2s_debugfs_create(i2s);
968 + if (ret) {
969 + dev_err(&pdev->dev, "create debugfs failed\n");
970 + goto err_clk_disable;
971 + }
972 +
973 + /* enable 24bits support */
974 + if (i2s->flags & RALINK_FLAGS_24BIT) {
975 + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
976 + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
977 + }
978 +
979 + /* enable big endian support */
980 + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
981 + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
982 + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
983 + ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
984 + if (i2s->flags & RALINK_FLAGS_24BIT) {
985 + ralink_i2s_dai.capture.formats |=
986 + SNDRV_PCM_FMTBIT_S24_BE;
987 + ralink_i2s_dai.playback.formats |=
988 + SNDRV_PCM_FMTBIT_S24_BE;
989 + ralink_pcm_hardware.formats |=
990 + SNDRV_PCM_FMTBIT_S24_BE;
991 + }
992 + }
993 +
994 + /* disable capture support */
995 + if (i2s->flags & RALINK_FLAGS_TXONLY)
996 + memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
997 + 0);
998 +
999 + ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
1000 + &ralink_i2s_dai, 1);
1001 + if (ret)
1002 + goto err_debugfs;
1003 +
1004 + ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
1005 + &ralink_dmaengine_pcm_config,
1006 + SND_DMAENGINE_PCM_FLAG_COMPAT);
1007 + if (ret)
1008 + goto err_debugfs;
1009 +
1010 + dev_info(i2s->dev, "mclk %luKHz\n", clk_get_rate(i2s->clk) / 1000000);
1011 +
1012 + return 0;
1013 +
1014 +err_debugfs:
1015 + ralink_i2s_debugfs_remove(i2s);
1016 +
1017 +err_clk_disable:
1018 + clk_disable_unprepare(i2s->clk);
1019 +
1020 + return ret;
1021 +}
1022 +
1023 +static int ralink_i2s_remove(struct platform_device *pdev)
1024 +{
1025 + struct ralink_i2s *i2s = platform_get_drvdata(pdev);
1026 +
1027 + ralink_i2s_debugfs_remove(i2s);
1028 + clk_disable_unprepare(i2s->clk);
1029 +
1030 + return 0;
1031 +}
1032 +
1033 +static struct platform_driver ralink_i2s_driver = {
1034 + .probe = ralink_i2s_probe,
1035 + .remove = ralink_i2s_remove,
1036 + .driver = {
1037 + .name = DRV_NAME,
1038 + .of_match_table = ralink_i2s_match_table,
1039 + },
1040 +};
1041 +module_platform_driver(ralink_i2s_driver);
1042 +
1043 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
1044 +MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
1045 +MODULE_LICENSE("GPL");
1046 +MODULE_ALIAS("platform:" DRV_NAME);