OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2018 John Crispin <john@phrozen.org> |
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11 | */ |
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12 | |||
13 | #include "mtk_offload.h" |
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14 | |||
15 | #define INVALID 0 |
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16 | #define UNBIND 1 |
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17 | #define BIND 2 |
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18 | #define FIN 3 |
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19 | |||
20 | #define IPV4_HNAPT 0 |
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21 | #define IPV4_HNAT 1 |
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22 | |||
23 | static u32 |
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24 | mtk_flow_hash_v4(struct flow_offload_tuple *tuple) |
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25 | { |
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26 | u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port); |
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27 | u32 src = ntohl(tuple->dst_v4.s_addr); |
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28 | u32 dst = ntohl(tuple->src_v4.s_addr); |
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29 | u32 hash = (ports & src) | ((~ports) & dst); |
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30 | u32 hash_23_0 = hash & 0xffffff; |
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31 | u32 hash_31_24 = hash & 0xff000000; |
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32 | |||
33 | hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24)); |
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34 | hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff); |
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35 | hash &= 0x7ff; |
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36 | hash *= 2;; |
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37 | |||
38 | return hash; |
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39 | } |
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40 | |||
41 | static int |
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42 | mtk_foe_prepare_v4(struct mtk_foe_entry *entry, |
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43 | struct flow_offload_tuple *tuple, |
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44 | struct flow_offload_tuple *dest_tuple, |
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45 | struct flow_offload_hw_path *src, |
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46 | struct flow_offload_hw_path *dest) |
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47 | { |
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48 | int is_mcast = !!is_multicast_ether_addr(dest->eth_dest); |
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49 | |||
50 | if (tuple->l4proto == IPPROTO_UDP) |
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51 | entry->ipv4_hnapt.bfib1.udp = 1; |
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52 | |||
53 | entry->ipv4_hnapt.etype = htons(ETH_P_IP); |
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54 | entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT; |
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55 | entry->ipv4_hnapt.iblk2.fqos = 0; |
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56 | entry->ipv4_hnapt.bfib1.ttl = 1; |
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57 | entry->ipv4_hnapt.bfib1.cah = 1; |
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58 | entry->ipv4_hnapt.bfib1.ka = 1; |
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59 | entry->ipv4_hnapt.iblk2.mcast = is_mcast; |
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60 | entry->ipv4_hnapt.iblk2.dscp = 0; |
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61 | entry->ipv4_hnapt.iblk2.port_mg = 0x3f; |
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62 | entry->ipv4_hnapt.iblk2.port_ag = 0x1f; |
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63 | #ifdef CONFIG_NET_MEDIATEK_HW_QOS |
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64 | entry->ipv4_hnapt.iblk2.qid = 1; |
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65 | entry->ipv4_hnapt.iblk2.fqos = 1; |
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66 | #endif |
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67 | #ifdef CONFIG_RALINK |
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68 | entry->ipv4_hnapt.iblk2.dp = 1; |
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69 | if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1)) |
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70 | entry->ipv4_hnapt.iblk2.qid += 8; |
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71 | #else |
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72 | entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1; |
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73 | #endif |
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74 | |||
75 | entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr); |
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76 | entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr); |
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77 | entry->ipv4_hnapt.sport = ntohs(tuple->src_port); |
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78 | entry->ipv4_hnapt.dport = ntohs(tuple->dst_port); |
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79 | |||
80 | entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr); |
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81 | entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr); |
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82 | entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port); |
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83 | entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port); |
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84 | |||
85 | entry->bfib1.state = BIND; |
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86 | |||
87 | if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) { |
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88 | entry->bfib1.psn = 1; |
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89 | entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES); |
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90 | entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid; |
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91 | } |
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92 | |||
93 | if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) { |
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94 | entry->ipv4_hnapt.vlan1 = dest->vlan_id; |
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95 | entry->bfib1.vlan_layer = 1; |
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96 | |||
97 | switch (dest->vlan_proto) { |
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98 | case htons(ETH_P_8021Q): |
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99 | entry->ipv4_hnapt.bfib1.vpm = 1; |
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100 | break; |
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101 | case htons(ETH_P_8021AD): |
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102 | entry->ipv4_hnapt.bfib1.vpm = 2; |
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103 | break; |
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104 | default: |
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105 | return -EINVAL; |
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106 | } |
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107 | } |
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108 | |||
109 | return 0; |
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110 | } |
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111 | |||
112 | static void |
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113 | mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac) |
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114 | { |
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115 | entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac)); |
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116 | entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4])); |
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117 | entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac)); |
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118 | entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4])); |
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119 | } |
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120 | |||
121 | static void |
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122 | mtk_foe_write(struct mtk_eth *eth, u32 hash, |
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123 | struct mtk_foe_entry *entry) |
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124 | { |
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125 | struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table; |
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126 | |||
127 | memcpy(&table[hash], entry, sizeof(*entry)); |
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128 | } |
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129 | |||
130 | int mtk_flow_offload(struct mtk_eth *eth, |
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131 | enum flow_offload_type type, |
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132 | struct flow_offload *flow, |
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133 | struct flow_offload_hw_path *src, |
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134 | struct flow_offload_hw_path *dest) |
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135 | { |
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136 | struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple; |
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137 | struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple; |
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138 | u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff); |
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139 | u32 ohash, rhash; |
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140 | struct mtk_foe_entry orig = { |
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141 | .bfib1.time_stamp = time_stamp, |
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142 | .bfib1.psn = 0, |
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143 | }; |
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144 | struct mtk_foe_entry reply = { |
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145 | .bfib1.time_stamp = time_stamp, |
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146 | .bfib1.psn = 0, |
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147 | }; |
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148 | |||
149 | if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP) |
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150 | return -EINVAL; |
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151 | |||
152 | switch (otuple->l3proto) { |
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153 | case AF_INET: |
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154 | if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) || |
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155 | mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src)) |
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156 | return -EINVAL; |
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157 | |||
158 | ohash = mtk_flow_hash_v4(otuple); |
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159 | rhash = mtk_flow_hash_v4(rtuple); |
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160 | break; |
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161 | |||
162 | case AF_INET6: |
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163 | return -EINVAL; |
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164 | |||
165 | default: |
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166 | return -EINVAL; |
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167 | } |
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168 | |||
169 | if (type == FLOW_OFFLOAD_DEL) { |
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170 | orig.bfib1.state = INVALID; |
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171 | reply.bfib1.state = INVALID; |
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172 | flow = NULL; |
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173 | goto write; |
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174 | } |
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175 | |||
176 | mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest); |
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177 | mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest); |
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178 | |||
179 | write: |
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180 | mtk_foe_write(eth, ohash, &orig); |
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181 | mtk_foe_write(eth, rhash, &reply); |
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182 | rcu_assign_pointer(eth->foe_flow_table[ohash], flow); |
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183 | rcu_assign_pointer(eth->foe_flow_table[rhash], flow); |
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184 | |||
185 | if (type == FLOW_OFFLOAD_DEL) |
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186 | synchronize_rcu(); |
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187 | |||
188 | return 0; |
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189 | } |
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190 | |||
191 | #ifdef CONFIG_NET_MEDIATEK_HW_QOS |
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192 | |||
193 | #define QDMA_TX_SCH_TX 0x1a14 |
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194 | |||
195 | static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate) |
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196 | { |
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197 | int exp = 0, shift = 0; |
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198 | u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX); |
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199 | u32 val = 0; |
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200 | |||
201 | if (rate) |
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202 | val = BIT(11); |
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203 | |||
204 | while (rate > 127) { |
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205 | rate /= 10; |
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206 | exp++; |
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207 | } |
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208 | |||
209 | val |= (rate & 0x7f) << 4; |
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210 | val |= exp & 0xf; |
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211 | if (id) |
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212 | shift = 16; |
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213 | reg &= ~(0xffff << shift); |
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214 | reg |= val << shift; |
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215 | mtk_w32(eth, val, QDMA_TX_SCH_TX); |
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216 | } |
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217 | |||
218 | #define QTX_CFG(x) (0x1800 + (x * 0x10)) |
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219 | #define QTX_SCH(x) (0x1804 + (x * 0x10)) |
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220 | |||
221 | static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate) |
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222 | { |
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223 | int max_exp = 0, min_exp = 0; |
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224 | u32 reg; |
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225 | |||
226 | if (id >= 16) |
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227 | return; |
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228 | |||
229 | reg = mtk_r32(eth, QTX_SCH(id)); |
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230 | reg &= 0x70000000; |
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231 | |||
232 | if (sched) |
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233 | reg |= BIT(31); |
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234 | |||
235 | if (min_rate) |
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236 | reg |= BIT(27); |
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237 | |||
238 | if (max_rate) |
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239 | reg |= BIT(11); |
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240 | |||
241 | while (max_rate > 127) { |
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242 | max_rate /= 10; |
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243 | max_exp++; |
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244 | } |
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245 | |||
246 | while (min_rate > 127) { |
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247 | min_rate /= 10; |
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248 | min_exp++; |
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249 | } |
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250 | |||
251 | reg |= (min_rate & 0x7f) << 20; |
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252 | reg |= (min_exp & 0xf) << 16; |
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253 | reg |= (weight & 0xf) << 12; |
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254 | reg |= (max_rate & 0x7f) << 4; |
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255 | reg |= max_exp & 0xf; |
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256 | mtk_w32(eth, reg, QTX_SCH(id)); |
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257 | |||
258 | resv &= 0xff; |
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259 | reg = mtk_r32(eth, QTX_CFG(id)); |
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260 | reg &= 0xffff0000; |
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261 | reg |= (resv << 8) | resv; |
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262 | mtk_w32(eth, reg, QTX_CFG(id)); |
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263 | } |
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264 | #endif |
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265 | |||
266 | static int mtk_init_foe_table(struct mtk_eth *eth) |
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267 | { |
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268 | if (eth->foe_table) |
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269 | return 0; |
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270 | |||
271 | eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT, |
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272 | sizeof(*eth->foe_flow_table), |
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273 | GFP_KERNEL); |
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274 | if (!eth->foe_flow_table) |
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275 | return -EINVAL; |
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276 | |||
277 | /* map the FOE table */ |
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278 | eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ, |
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279 | ð->foe_table_phys, GFP_KERNEL); |
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280 | if (!eth->foe_table) { |
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281 | dev_err(eth->dev, "failed to allocate foe table\n"); |
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282 | kfree(eth->foe_flow_table); |
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283 | return -ENOMEM; |
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284 | } |
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285 | |||
286 | |||
287 | return 0; |
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288 | } |
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289 | |||
290 | static int mtk_ppe_start(struct mtk_eth *eth) |
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291 | { |
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292 | int ret; |
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293 | |||
294 | ret = mtk_init_foe_table(eth); |
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295 | if (ret) |
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296 | return ret; |
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297 | |||
298 | /* tell the PPE about the tables base address */ |
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299 | mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE); |
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300 | |||
301 | /* flush the table */ |
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302 | memset(eth->foe_table, 0, MTK_PPE_TBL_SZ); |
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303 | |||
304 | /* setup hashing */ |
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305 | mtk_m32(eth, |
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306 | MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK, |
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307 | MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K, |
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308 | MTK_REG_PPE_TB_CFG); |
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309 | |||
310 | /* set the default hashing seed */ |
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311 | mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED); |
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312 | |||
313 | /* each foe entry is 64bytes and is setup by cpu forwarding*/ |
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314 | mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK | |
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315 | MTK_PPE_TB_CFG_SMA_MASK, |
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316 | MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU, |
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317 | MTK_REG_PPE_TB_CFG); |
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318 | |||
319 | /* set ip proto */ |
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320 | mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK); |
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321 | |||
322 | /* setup caching */ |
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323 | mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL); |
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324 | mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN, |
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325 | MTK_REG_PPE_CAH_CTRL); |
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326 | |||
327 | /* enable FOE */ |
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328 | mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN | |
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329 | MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN | |
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330 | MTK_PPE_FLOW_CFG_IPV4_GREK_EN, |
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331 | MTK_REG_PPE_FLOW_CFG); |
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332 | |||
333 | /* setup flow entry un/bind aging */ |
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334 | mtk_m32(eth, 0, |
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335 | MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE | |
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336 | MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE | |
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337 | MTK_PPE_TB_CFG_TCP_AGE, |
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338 | MTK_REG_PPE_TB_CFG); |
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339 | |||
340 | mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK, |
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341 | MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA, |
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342 | MTK_REG_PPE_UNB_AGE); |
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343 | mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK | |
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344 | MTK_PPE_BND_AGE0_UDP_DLTA_MASK, |
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345 | MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA, |
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346 | MTK_REG_PPE_BND_AGE0); |
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347 | mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK | |
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348 | MTK_PPE_BND_AGE1_TCP_DLTA_MASK, |
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349 | MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA, |
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350 | MTK_REG_PPE_BND_AGE1); |
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351 | |||
352 | /* setup flow entry keep alive */ |
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353 | mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK, MTK_PPE_TB_CFG_KA, |
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354 | MTK_REG_PPE_TB_CFG); |
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355 | mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA); |
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356 | |||
357 | /* setup flow entry rate limit */ |
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358 | mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0); |
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359 | mtk_w32(eth, MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1); |
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360 | mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 1, MTK_REG_PPE_BNDR); |
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361 | |||
362 | /* enable the PPE */ |
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363 | mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG); |
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364 | |||
365 | #ifdef CONFIG_RALINK |
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366 | /* set the default forwarding port to QDMA */ |
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367 | mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT); |
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368 | #else |
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369 | /* set the default forwarding port to QDMA */ |
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370 | mtk_w32(eth, 0x55555555, MTK_REG_PPE_DFT_CPORT); |
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371 | #endif |
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372 | |||
373 | /* drop packets with TTL=0 */ |
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374 | mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG); |
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375 | |||
376 | /* send all traffic from gmac to the ppe */ |
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377 | mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0)); |
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378 | mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1)); |
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379 | |||
380 | dev_info(eth->dev, "PPE started\n"); |
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381 | |||
382 | #ifdef CONFIG_NET_MEDIATEK_HW_QOS |
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383 | mtk_ppe_scheduler(eth, 0, 500000); |
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384 | mtk_ppe_scheduler(eth, 1, 500000); |
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385 | mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0); |
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386 | mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0); |
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387 | mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0); |
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388 | mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0); |
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389 | #endif |
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390 | |||
391 | return 0; |
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392 | } |
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393 | |||
394 | static int mtk_ppe_busy_wait(struct mtk_eth *eth) |
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395 | { |
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396 | unsigned long t_start = jiffies; |
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397 | u32 r = 0; |
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398 | |||
399 | while (1) { |
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400 | r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG); |
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401 | if (!(r & MTK_PPE_GLO_CFG_BUSY)) |
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402 | return 0; |
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403 | if (time_after(jiffies, t_start + HZ)) |
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404 | break; |
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405 | usleep_range(10, 20); |
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406 | } |
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407 | |||
408 | dev_err(eth->dev, "ppe: table busy timeout - resetting\n"); |
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409 | reset_control_reset(eth->rst_ppe); |
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410 | |||
411 | return -ETIMEDOUT; |
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412 | } |
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413 | |||
414 | static int mtk_ppe_stop(struct mtk_eth *eth) |
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415 | { |
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416 | u32 r1 = 0, r2 = 0; |
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417 | int i; |
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418 | |||
419 | /* discard all traffic while we disable the PPE */ |
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420 | mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0)); |
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421 | mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1)); |
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422 | |||
423 | if (mtk_ppe_busy_wait(eth)) |
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424 | return -ETIMEDOUT; |
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425 | |||
426 | /* invalidate all flow table entries */ |
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427 | for (i = 0; i < MTK_PPE_ENTRY_CNT; i++) |
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428 | eth->foe_table[i].bfib1.state = FOE_STATE_INVALID; |
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429 | |||
430 | /* disable caching */ |
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431 | mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL); |
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432 | mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0, |
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433 | MTK_REG_PPE_CAH_CTRL); |
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434 | |||
435 | /* flush cache has to be ahead of hnat diable --*/ |
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436 | mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG); |
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437 | |||
438 | /* disable FOE */ |
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439 | mtk_m32(eth, |
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440 | MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN | |
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441 | MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN | |
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442 | MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE, |
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443 | 0, MTK_REG_PPE_FLOW_CFG); |
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444 | |||
445 | /* disable FOE aging */ |
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446 | mtk_m32(eth, 0, |
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447 | MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE | |
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448 | MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE | |
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449 | MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG); |
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450 | |||
451 | r1 = mtk_r32(eth, 0x100); |
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452 | r2 = mtk_r32(eth, 0x10c); |
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453 | |||
454 | dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2); |
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455 | |||
456 | if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) || |
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457 | ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) { |
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458 | dev_info(eth->dev, "reset pse\n"); |
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459 | mtk_w32(eth, 0x1, 0x4); |
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460 | } |
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461 | |||
462 | /* set the foe entry base address to 0 */ |
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463 | mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE); |
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464 | |||
465 | if (mtk_ppe_busy_wait(eth)) |
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466 | return -ETIMEDOUT; |
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467 | |||
468 | /* send all traffic back to the DMA engine */ |
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469 | #ifdef CONFIG_RALINK |
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470 | mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0)); |
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471 | mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1)); |
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472 | #else |
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473 | mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(0)); |
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474 | mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(1)); |
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475 | #endif |
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476 | return 0; |
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477 | } |
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478 | |||
479 | static void mtk_offload_keepalive(struct fe_priv *eth, unsigned int hash) |
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480 | { |
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481 | struct flow_offload *flow; |
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482 | |||
483 | rcu_read_lock(); |
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484 | flow = rcu_dereference(eth->foe_flow_table[hash]); |
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485 | if (flow) |
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486 | flow->timeout = jiffies + 30 * HZ; |
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487 | rcu_read_unlock(); |
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488 | } |
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489 | |||
490 | int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4) |
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491 | { |
||
492 | unsigned int hash; |
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493 | |||
494 | switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) { |
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495 | case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR: |
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496 | case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR: |
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497 | case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR: |
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498 | hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4); |
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499 | mtk_offload_keepalive(eth, hash); |
||
500 | return -1; |
||
501 | case MTK_CPU_REASON_PACKET_SAMPLING: |
||
502 | return -1; |
||
503 | default: |
||
504 | return 0; |
||
505 | } |
||
506 | } |
||
507 | |||
508 | int mtk_ppe_probe(struct mtk_eth *eth) |
||
509 | { |
||
510 | int err; |
||
511 | |||
512 | err = mtk_ppe_start(eth); |
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513 | if (err) |
||
514 | return err; |
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515 | |||
516 | err = mtk_ppe_debugfs_init(eth); |
||
517 | if (err) |
||
518 | return err; |
||
519 | |||
520 | return 0; |
||
521 | } |
||
522 | |||
523 | void mtk_ppe_remove(struct mtk_eth *eth) |
||
524 | { |
||
525 | mtk_ppe_stop(eth); |
||
526 | } |