OpenWrt – Blame information for rev 4
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4 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #ifndef FE_ETH_H |
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16 | #define FE_ETH_H |
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17 | |||
18 | #include <linux/mii.h> |
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19 | #include <linux/interrupt.h> |
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20 | #include <linux/netdevice.h> |
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21 | #include <linux/dma-mapping.h> |
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22 | #include <linux/phy.h> |
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23 | #include <linux/ethtool.h> |
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24 | #include <linux/version.h> |
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25 | |||
26 | enum fe_reg { |
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27 | FE_REG_PDMA_GLO_CFG = 0, |
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28 | FE_REG_PDMA_RST_CFG, |
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29 | FE_REG_DLY_INT_CFG, |
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30 | FE_REG_TX_BASE_PTR0, |
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31 | FE_REG_TX_MAX_CNT0, |
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32 | FE_REG_TX_CTX_IDX0, |
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33 | FE_REG_TX_DTX_IDX0, |
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34 | FE_REG_RX_BASE_PTR0, |
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35 | FE_REG_RX_MAX_CNT0, |
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36 | FE_REG_RX_CALC_IDX0, |
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37 | FE_REG_RX_DRX_IDX0, |
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38 | FE_REG_FE_INT_ENABLE, |
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39 | FE_REG_FE_INT_STATUS, |
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40 | FE_REG_FE_DMA_VID_BASE, |
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41 | FE_REG_FE_COUNTER_BASE, |
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42 | FE_REG_FE_RST_GL, |
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43 | FE_REG_FE_INT_STATUS2, |
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44 | FE_REG_COUNT |
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45 | }; |
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46 | |||
47 | enum fe_work_flag { |
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48 | FE_FLAG_RESET_PENDING, |
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49 | FE_FLAG_MAX |
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50 | }; |
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51 | |||
52 | #define MTK_FE_DRV_VERSION "0.1.2" |
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53 | |||
54 | /* power of 2 to let NEXT_TX_DESP_IDX work */ |
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55 | #define NUM_DMA_DESC BIT(10) |
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56 | #define MAX_DMA_DESC 0xfff |
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57 | |||
58 | #define FE_DELAY_EN_INT 0x80 |
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59 | #define FE_DELAY_MAX_INT 0x04 |
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60 | #define FE_DELAY_MAX_TOUT 0x04 |
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61 | #define FE_DELAY_TIME 20 |
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62 | #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \ |
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63 | FE_DELAY_MAX_TOUT) |
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64 | #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN) |
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65 | #define FE_PSE_FQFC_CFG_INIT 0x80504000 |
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66 | #define FE_PSE_FQFC_CFG_256Q 0xff908000 |
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67 | |||
68 | /* interrupt bits */ |
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69 | #define FE_CNT_PPE_AF BIT(31) |
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70 | #define FE_CNT_GDM_AF BIT(29) |
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71 | #define FE_PSE_P2_FC BIT(26) |
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72 | #define FE_PSE_BUF_DROP BIT(24) |
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73 | #define FE_GDM_OTHER_DROP BIT(23) |
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74 | #define FE_PSE_P1_FC BIT(22) |
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75 | #define FE_PSE_P0_FC BIT(21) |
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76 | #define FE_PSE_FQ_EMPTY BIT(20) |
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77 | #define FE_GE1_STA_CHG BIT(18) |
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78 | #define FE_TX_COHERENT BIT(17) |
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79 | #define FE_RX_COHERENT BIT(16) |
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80 | #define FE_TX_DONE_INT3 BIT(11) |
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81 | #define FE_TX_DONE_INT2 BIT(10) |
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82 | #define FE_TX_DONE_INT1 BIT(9) |
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83 | #define FE_TX_DONE_INT0 BIT(8) |
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84 | #define FE_RX_DONE_INT0 BIT(2) |
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85 | #define FE_TX_DLY_INT BIT(1) |
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86 | #define FE_RX_DLY_INT BIT(0) |
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87 | |||
88 | #define FE_RX_DONE_INT FE_RX_DONE_INT0 |
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89 | #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \ |
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90 | FE_TX_DONE_INT2 | FE_TX_DONE_INT3) |
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91 | |||
92 | #define RT5350_RX_DLY_INT BIT(30) |
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93 | #define RT5350_TX_DLY_INT BIT(28) |
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94 | #define RT5350_RX_DONE_INT1 BIT(17) |
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95 | #define RT5350_RX_DONE_INT0 BIT(16) |
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96 | #define RT5350_TX_DONE_INT3 BIT(3) |
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97 | #define RT5350_TX_DONE_INT2 BIT(2) |
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98 | #define RT5350_TX_DONE_INT1 BIT(1) |
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99 | #define RT5350_TX_DONE_INT0 BIT(0) |
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100 | |||
101 | #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1) |
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102 | #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \ |
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103 | RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3) |
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104 | |||
105 | /* registers */ |
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106 | #define FE_FE_OFFSET 0x0000 |
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107 | #define FE_GDMA_OFFSET 0x0020 |
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108 | #define FE_PSE_OFFSET 0x0040 |
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109 | #define FE_GDMA2_OFFSET 0x0060 |
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110 | #define FE_CDMA_OFFSET 0x0080 |
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111 | #define FE_DMA_VID0 0x00a8 |
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112 | #define FE_PDMA_OFFSET 0x0100 |
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113 | #define FE_PPE_OFFSET 0x0200 |
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114 | #define FE_CMTABLE_OFFSET 0x0400 |
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115 | #define FE_POLICYTABLE_OFFSET 0x1000 |
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116 | |||
117 | #define RT5350_PDMA_OFFSET 0x0800 |
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118 | #define RT5350_SDM_OFFSET 0x0c00 |
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119 | |||
120 | #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00) |
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121 | #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04) |
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122 | #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08) |
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123 | #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C) |
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124 | #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10) |
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125 | #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14) |
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126 | #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18) |
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127 | #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C) |
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128 | |||
129 | #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00) |
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130 | #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04) |
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131 | #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08) |
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132 | #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C) |
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133 | #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10) |
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134 | |||
135 | #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00) |
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136 | #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04) |
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137 | #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08) |
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138 | #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C) |
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139 | #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10) |
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140 | |||
141 | #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00) |
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142 | #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04) |
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143 | #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08) |
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144 | #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C) |
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145 | |||
146 | #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00) |
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147 | #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04) |
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148 | |||
149 | #ifdef CONFIG_SOC_MT7621 |
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150 | #define MT7620A_GDMA_OFFSET 0x0500 |
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151 | #else |
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152 | #define MT7620A_GDMA_OFFSET 0x0600 |
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153 | #endif |
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154 | #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00) |
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155 | #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04) |
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156 | #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08) |
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157 | #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C) |
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158 | #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10) |
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159 | |||
160 | #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00) |
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161 | #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04) |
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162 | #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08) |
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163 | #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C) |
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164 | #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10) |
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165 | #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14) |
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166 | #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18) |
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167 | #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C) |
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168 | #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20) |
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169 | #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24) |
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170 | #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28) |
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171 | #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C) |
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172 | #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30) |
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173 | #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34) |
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174 | #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38) |
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175 | #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C) |
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176 | #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100) |
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177 | #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104) |
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178 | #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108) |
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179 | #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C) |
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180 | #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110) |
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181 | #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114) |
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182 | #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118) |
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183 | #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C) |
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184 | #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204) |
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185 | #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208) |
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186 | #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c) |
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187 | #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220) |
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188 | #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228) |
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189 | #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280) |
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190 | |||
191 | #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00) |
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192 | #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04) |
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193 | #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08) |
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194 | #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C) |
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195 | #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10) |
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196 | #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14) |
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197 | #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18) |
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198 | #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C) |
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199 | #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20) |
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200 | #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24) |
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201 | #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28) |
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202 | #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C) |
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203 | #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30) |
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204 | #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34) |
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205 | #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38) |
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206 | #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C) |
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207 | #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40) |
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208 | #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44) |
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209 | #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48) |
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210 | #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C) |
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211 | #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50) |
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212 | #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54) |
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213 | #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58) |
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214 | #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C) |
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215 | #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60) |
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216 | #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64) |
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217 | #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68) |
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218 | #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C) |
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219 | |||
220 | /* Switch DMA configuration */ |
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221 | #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) |
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222 | #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) |
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223 | #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) |
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224 | #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) |
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225 | #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) |
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226 | #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) |
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227 | #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) |
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228 | #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) |
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229 | #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) |
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230 | #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) |
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231 | |||
232 | #define RT5350_SDM_ICS_EN BIT(16) |
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233 | #define RT5350_SDM_TCS_EN BIT(17) |
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234 | #define RT5350_SDM_UCS_EN BIT(18) |
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235 | |||
236 | /* MDIO_CFG register bits */ |
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237 | #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29) |
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238 | #define FE_MDIO_CFG_GP1_BP_EN BIT(16) |
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239 | #define FE_MDIO_CFG_GP1_FRC_EN BIT(15) |
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240 | #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13) |
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241 | #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13) |
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242 | #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13) |
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243 | #define FE_MDIO_CFG_GP1_DUPLEX BIT(12) |
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244 | #define FE_MDIO_CFG_GP1_FC_TX BIT(11) |
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245 | #define FE_MDIO_CFG_GP1_FC_RX BIT(10) |
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246 | #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9) |
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247 | #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8) |
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248 | #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) |
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249 | #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) |
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250 | #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) |
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251 | #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) |
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252 | #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5) |
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253 | #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4) |
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254 | #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) |
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255 | #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) |
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256 | #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) |
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257 | #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) |
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258 | #define FE_MDIO_CFG_TX_CLK_SKEW_0 0 |
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259 | #define FE_MDIO_CFG_TX_CLK_SKEW_200 1 |
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260 | #define FE_MDIO_CFG_TX_CLK_SKEW_400 2 |
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261 | #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3 |
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262 | |||
263 | /* uni-cast port */ |
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264 | #define FE_GDM1_JMB_LEN_MASK 0xf |
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265 | #define FE_GDM1_JMB_LEN_SHIFT 28 |
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266 | #define FE_GDM1_ICS_EN BIT(22) |
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267 | #define FE_GDM1_TCS_EN BIT(21) |
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268 | #define FE_GDM1_UCS_EN BIT(20) |
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269 | #define FE_GDM1_JMB_EN BIT(19) |
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270 | #define FE_GDM1_STRPCRC BIT(16) |
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271 | #define FE_GDM1_UFRC_P_CPU (0 << 12) |
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272 | #define FE_GDM1_UFRC_P_GDMA1 (1 << 12) |
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273 | #define FE_GDM1_UFRC_P_PPE (6 << 12) |
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274 | |||
275 | /* checksums */ |
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276 | #define FE_ICS_GEN_EN BIT(2) |
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277 | #define FE_UCS_GEN_EN BIT(1) |
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278 | #define FE_TCS_GEN_EN BIT(0) |
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279 | |||
280 | /* dma ring */ |
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281 | #define FE_PST_DRX_IDX0 BIT(16) |
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282 | #define FE_PST_DTX_IDX3 BIT(3) |
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283 | #define FE_PST_DTX_IDX2 BIT(2) |
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284 | #define FE_PST_DTX_IDX1 BIT(1) |
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285 | #define FE_PST_DTX_IDX0 BIT(0) |
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286 | |||
287 | #define FE_RX_2B_OFFSET BIT(31) |
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288 | #define FE_TX_WB_DDONE BIT(6) |
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289 | #define FE_RX_DMA_BUSY BIT(3) |
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290 | #define FE_TX_DMA_BUSY BIT(1) |
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291 | #define FE_RX_DMA_EN BIT(2) |
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292 | #define FE_TX_DMA_EN BIT(0) |
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293 | |||
294 | #define FE_PDMA_SIZE_4DWORDS (0 << 4) |
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295 | #define FE_PDMA_SIZE_8DWORDS (1 << 4) |
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296 | #define FE_PDMA_SIZE_16DWORDS (2 << 4) |
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297 | |||
298 | #define FE_US_CYC_CNT_MASK 0xff |
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299 | #define FE_US_CYC_CNT_SHIFT 0x8 |
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300 | #define FE_US_CYC_CNT_DIVISOR 1000000 |
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301 | |||
302 | /* rxd2 */ |
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303 | #define RX_DMA_DONE BIT(31) |
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304 | #define RX_DMA_LSO BIT(30) |
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305 | #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) |
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306 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) |
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307 | #define RX_DMA_TAG BIT(15) |
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308 | /* rxd3 */ |
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309 | #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff) |
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310 | #define RX_DMA_VID(_x) ((_x) & 0xffff) |
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311 | /* rxd4 */ |
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312 | #define RX_DMA_L4VALID BIT(30) |
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313 | |||
314 | struct fe_rx_dma { |
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315 | unsigned int rxd1; |
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316 | unsigned int rxd2; |
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317 | unsigned int rxd3; |
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318 | unsigned int rxd4; |
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319 | } __packed __aligned(4); |
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320 | |||
321 | #define TX_DMA_BUF_LEN 0x3fff |
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322 | #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16) |
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323 | #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16) |
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324 | #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) |
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325 | #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN) |
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326 | #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) |
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327 | #define TX_DMA_LS1 BIT(14) |
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328 | #define TX_DMA_LS0 BIT(30) |
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329 | #define TX_DMA_DONE BIT(31) |
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330 | |||
331 | #define TX_DMA_INS_VLAN_MT7621 BIT(16) |
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332 | #define TX_DMA_INS_VLAN BIT(7) |
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333 | #define TX_DMA_INS_PPPOE BIT(12) |
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334 | #define TX_DMA_QN(_x) ((_x) << 16) |
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335 | #define TX_DMA_PN(_x) ((_x) << 24) |
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336 | #define TX_DMA_QN_MASK TX_DMA_QN(0x7) |
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337 | #define TX_DMA_PN_MASK TX_DMA_PN(0x7) |
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338 | #define TX_DMA_UDF BIT(20) |
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339 | #define TX_DMA_CHKSUM (0x7 << 29) |
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340 | #define TX_DMA_TSO BIT(28) |
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341 | |||
342 | /* frame engine counters */ |
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343 | #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00) |
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344 | #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300) |
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345 | #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40) |
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346 | |||
347 | /* phy device flags */ |
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348 | #define FE_PHY_FLAG_PORT BIT(0) |
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349 | #define FE_PHY_FLAG_ATTACH BIT(1) |
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350 | |||
351 | struct fe_tx_dma { |
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352 | unsigned int txd1; |
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353 | unsigned int txd2; |
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354 | unsigned int txd3; |
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355 | unsigned int txd4; |
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356 | } __packed __aligned(4); |
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357 | |||
358 | struct fe_priv; |
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359 | |||
360 | struct fe_phy { |
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361 | /* make sure that phy operations are atomic */ |
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362 | spinlock_t lock; |
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363 | |||
364 | struct phy_device *phy[8]; |
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365 | struct device_node *phy_node[8]; |
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366 | const __be32 *phy_fixed[8]; |
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367 | int duplex[8]; |
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368 | int speed[8]; |
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369 | int tx_fc[8]; |
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370 | int rx_fc[8]; |
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371 | int (*connect)(struct fe_priv *priv); |
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372 | void (*disconnect)(struct fe_priv *priv); |
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373 | void (*start)(struct fe_priv *priv); |
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374 | void (*stop)(struct fe_priv *priv); |
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375 | }; |
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376 | |||
377 | struct fe_soc_data { |
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378 | const u16 *reg_table; |
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379 | |||
380 | void (*init_data)(struct fe_soc_data *data, struct net_device *netdev); |
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381 | void (*reset_fe)(void); |
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382 | void (*set_mac)(struct fe_priv *priv, unsigned char *mac); |
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383 | int (*fwd_config)(struct fe_priv *priv); |
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384 | void (*tx_dma)(struct fe_tx_dma *txd); |
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385 | int (*switch_init)(struct fe_priv *priv); |
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386 | int (*switch_config)(struct fe_priv *priv); |
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387 | void (*port_init)(struct fe_priv *priv, struct device_node *port); |
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388 | int (*has_carrier)(struct fe_priv *priv); |
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389 | int (*mdio_init)(struct fe_priv *priv); |
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390 | void (*mdio_cleanup)(struct fe_priv *priv); |
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391 | int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, |
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392 | u16 val); |
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393 | int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg); |
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394 | void (*mdio_adjust_link)(struct fe_priv *priv, int port); |
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395 | |||
396 | void *swpriv; |
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397 | u32 pdma_glo_cfg; |
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398 | u32 rx_int; |
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399 | u32 tx_int; |
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400 | u32 status_int; |
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401 | u32 checksum_bit; |
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402 | }; |
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403 | |||
404 | #define FE_FLAG_PADDING_64B BIT(0) |
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405 | #define FE_FLAG_PADDING_BUG BIT(1) |
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406 | #define FE_FLAG_JUMBO_FRAME BIT(2) |
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407 | #define FE_FLAG_RX_2B_OFFSET BIT(3) |
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408 | #define FE_FLAG_RX_SG_DMA BIT(4) |
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409 | #define FE_FLAG_RX_VLAN_CTAG BIT(5) |
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410 | #define FE_FLAG_NAPI_WEIGHT BIT(6) |
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411 | #define FE_FLAG_CALIBRATE_CLK BIT(7) |
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412 | #define FE_FLAG_HAS_SWITCH BIT(8) |
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413 | |||
414 | #define FE_STAT_REG_DECLARE \ |
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415 | _FE(tx_bytes) \ |
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416 | _FE(tx_packets) \ |
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417 | _FE(tx_skip) \ |
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418 | _FE(tx_collisions) \ |
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419 | _FE(rx_bytes) \ |
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420 | _FE(rx_packets) \ |
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421 | _FE(rx_overflow) \ |
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422 | _FE(rx_fcs_errors) \ |
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423 | _FE(rx_short_errors) \ |
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424 | _FE(rx_long_errors) \ |
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425 | _FE(rx_checksum_errors) \ |
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426 | _FE(rx_flow_control_packets) |
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427 | |||
428 | struct fe_hw_stats { |
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429 | /* make sure that stats operations are atomic */ |
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430 | spinlock_t stats_lock; |
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431 | |||
432 | struct u64_stats_sync syncp; |
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433 | #define _FE(x) u64 x; |
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434 | FE_STAT_REG_DECLARE |
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435 | #undef _FE |
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436 | }; |
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437 | |||
438 | enum fe_tx_flags { |
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439 | FE_TX_FLAGS_SINGLE0 = 0x01, |
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440 | FE_TX_FLAGS_PAGE0 = 0x02, |
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441 | FE_TX_FLAGS_PAGE1 = 0x04, |
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442 | }; |
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443 | |||
444 | struct fe_tx_buf { |
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445 | struct sk_buff *skb; |
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446 | u32 flags; |
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447 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); |
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448 | DEFINE_DMA_UNMAP_LEN(dma_len0); |
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449 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); |
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450 | DEFINE_DMA_UNMAP_LEN(dma_len1); |
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451 | }; |
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452 | |||
453 | struct fe_tx_ring { |
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454 | struct fe_tx_dma *tx_dma; |
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455 | struct fe_tx_buf *tx_buf; |
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456 | dma_addr_t tx_phys; |
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457 | u16 tx_ring_size; |
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458 | u16 tx_free_idx; |
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459 | u16 tx_next_idx; |
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460 | u16 tx_thresh; |
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461 | }; |
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462 | |||
463 | struct fe_rx_ring { |
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464 | struct page_frag_cache frag_cache; |
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465 | struct fe_rx_dma *rx_dma; |
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466 | u8 **rx_data; |
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467 | dma_addr_t rx_phys; |
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468 | u16 rx_ring_size; |
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469 | u16 frag_size; |
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470 | u16 rx_buf_size; |
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471 | u16 rx_calc_idx; |
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472 | }; |
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473 | |||
474 | struct fe_priv { |
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475 | /* make sure that register operations are atomic */ |
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476 | spinlock_t page_lock; |
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477 | |||
478 | struct fe_soc_data *soc; |
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479 | struct net_device *netdev; |
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480 | struct device_node *switch_np; |
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481 | u32 msg_enable; |
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482 | u32 flags; |
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483 | |||
484 | struct device *dev; |
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485 | unsigned long sysclk; |
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486 | |||
487 | struct fe_rx_ring rx_ring; |
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488 | struct napi_struct rx_napi; |
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489 | |||
490 | struct fe_tx_ring tx_ring; |
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491 | |||
492 | struct fe_phy *phy; |
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493 | struct mii_bus *mii_bus; |
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494 | struct phy_device *phy_dev; |
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495 | u32 phy_flags; |
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496 | |||
497 | int link[8]; |
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498 | |||
499 | struct fe_hw_stats *hw_stats; |
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500 | unsigned long vlan_map; |
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501 | struct work_struct pending_work; |
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502 | DECLARE_BITMAP(pending_flags, FE_FLAG_MAX); |
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503 | |||
504 | struct reset_control *rst_ppe; |
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505 | struct mtk_foe_entry *foe_table; |
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506 | dma_addr_t foe_table_phys; |
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507 | struct flow_offload __rcu **foe_flow_table; |
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508 | }; |
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509 | |||
510 | extern const struct of_device_id of_fe_match[]; |
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511 | |||
512 | void fe_w32(u32 val, unsigned reg); |
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513 | void fe_m32(struct fe_priv *priv, u32 clear, u32 set, unsigned reg); |
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514 | u32 fe_r32(unsigned reg); |
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515 | |||
516 | int fe_set_clock_cycle(struct fe_priv *priv); |
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517 | void fe_csum_config(struct fe_priv *priv); |
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518 | void fe_stats_update(struct fe_priv *priv); |
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519 | void fe_fwd_config(struct fe_priv *priv); |
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520 | void fe_reg_w32(u32 val, enum fe_reg reg); |
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521 | u32 fe_reg_r32(enum fe_reg reg); |
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522 | |||
523 | void fe_reset(u32 reset_bits); |
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524 | |||
525 | static inline void *priv_netdev(struct fe_priv *priv) |
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526 | { |
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527 | return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN); |
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528 | } |
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529 | |||
530 | int mtk_ppe_probe(struct fe_priv *eth); |
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531 | void mtk_ppe_remove(struct fe_priv *eth); |
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532 | int mtk_flow_offload(struct fe_priv *eth, |
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533 | enum flow_offload_type type, |
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534 | struct flow_offload *flow, |
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535 | struct flow_offload_hw_path *src, |
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536 | struct flow_offload_hw_path *dest); |
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537 | int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4); |
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538 | |||
539 | |||
540 | #endif /* FE_ETH_H */ |