OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #include <linux/module.h> |
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16 | #include <linux/kernel.h> |
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17 | #include <linux/types.h> |
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18 | #include <linux/dma-mapping.h> |
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19 | #include <linux/init.h> |
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20 | #include <linux/skbuff.h> |
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21 | #include <linux/etherdevice.h> |
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22 | #include <linux/ethtool.h> |
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23 | #include <linux/platform_device.h> |
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24 | #include <linux/of_device.h> |
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25 | #include <linux/clk.h> |
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26 | #include <linux/of_net.h> |
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27 | #include <linux/of_mdio.h> |
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28 | #include <linux/if_vlan.h> |
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29 | #include <linux/reset.h> |
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30 | #include <linux/tcp.h> |
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31 | #include <linux/io.h> |
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32 | #include <linux/bug.h> |
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33 | #include <linux/netfilter.h> |
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34 | #include <net/netfilter/nf_flow_table.h> |
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35 | |||
36 | #include <asm/mach-ralink/ralink_regs.h> |
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37 | |||
38 | #include "mtk_eth_soc.h" |
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39 | #include "mdio.h" |
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40 | #include "ethtool.h" |
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41 | |||
42 | #define MAX_RX_LENGTH 1536 |
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43 | #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
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44 | #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN) |
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45 | #define DMA_DUMMY_DESC 0xffffffff |
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46 | #define FE_DEFAULT_MSG_ENABLE \ |
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47 | (NETIF_MSG_DRV | \ |
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48 | NETIF_MSG_PROBE | \ |
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49 | NETIF_MSG_LINK | \ |
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50 | NETIF_MSG_TIMER | \ |
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51 | NETIF_MSG_IFDOWN | \ |
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52 | NETIF_MSG_IFUP | \ |
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53 | NETIF_MSG_RX_ERR | \ |
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54 | NETIF_MSG_TX_ERR) |
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55 | |||
56 | #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) |
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57 | #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1)) |
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58 | #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1)) |
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59 | #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1)) |
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60 | |||
61 | #define SYSC_REG_RSTCTRL 0x34 |
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62 | |||
63 | static int fe_msg_level = -1; |
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64 | module_param_named(msg_level, fe_msg_level, int, 0); |
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65 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); |
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66 | |||
67 | static const u16 fe_reg_table_default[FE_REG_COUNT] = { |
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68 | [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG, |
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69 | [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG, |
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70 | [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG, |
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71 | [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0, |
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72 | [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0, |
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73 | [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0, |
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74 | [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0, |
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75 | [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0, |
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76 | [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0, |
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77 | [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0, |
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78 | [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0, |
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79 | [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE, |
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80 | [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS, |
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81 | [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0, |
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82 | [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT, |
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83 | [FE_REG_FE_RST_GL] = FE_FE_RST_GL, |
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84 | }; |
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85 | |||
86 | static const u16 *fe_reg_table = fe_reg_table_default; |
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87 | |||
88 | struct fe_work_t { |
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89 | int bitnr; |
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90 | void (*action)(struct fe_priv *); |
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91 | }; |
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92 | |||
93 | static void __iomem *fe_base; |
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94 | |||
95 | void fe_w32(u32 val, unsigned reg) |
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96 | { |
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97 | __raw_writel(val, fe_base + reg); |
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98 | } |
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99 | |||
100 | u32 fe_r32(unsigned reg) |
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101 | { |
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102 | return __raw_readl(fe_base + reg); |
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103 | } |
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104 | |||
105 | void fe_reg_w32(u32 val, enum fe_reg reg) |
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106 | { |
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107 | fe_w32(val, fe_reg_table[reg]); |
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108 | } |
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109 | |||
110 | u32 fe_reg_r32(enum fe_reg reg) |
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111 | { |
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112 | return fe_r32(fe_reg_table[reg]); |
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113 | } |
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114 | |||
115 | void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg) |
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116 | { |
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117 | u32 val; |
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118 | |||
119 | spin_lock(ð->page_lock); |
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120 | val = __raw_readl(fe_base + reg); |
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121 | val &= ~clear; |
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122 | val |= set; |
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123 | __raw_writel(val, fe_base + reg); |
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124 | spin_unlock(ð->page_lock); |
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125 | } |
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126 | |||
127 | void fe_reset(u32 reset_bits) |
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128 | { |
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129 | u32 t; |
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130 | |||
131 | t = rt_sysc_r32(SYSC_REG_RSTCTRL); |
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132 | t |= reset_bits; |
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133 | rt_sysc_w32(t, SYSC_REG_RSTCTRL); |
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134 | usleep_range(10, 20); |
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135 | |||
136 | t &= ~reset_bits; |
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137 | rt_sysc_w32(t, SYSC_REG_RSTCTRL); |
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138 | usleep_range(10, 20); |
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139 | } |
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140 | |||
141 | static inline void fe_int_disable(u32 mask) |
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142 | { |
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143 | fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask, |
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144 | FE_REG_FE_INT_ENABLE); |
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145 | /* flush write */ |
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146 | fe_reg_r32(FE_REG_FE_INT_ENABLE); |
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147 | } |
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148 | |||
149 | static inline void fe_int_enable(u32 mask) |
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150 | { |
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151 | fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask, |
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152 | FE_REG_FE_INT_ENABLE); |
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153 | /* flush write */ |
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154 | fe_reg_r32(FE_REG_FE_INT_ENABLE); |
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155 | } |
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156 | |||
157 | static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac) |
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158 | { |
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159 | unsigned long flags; |
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160 | |||
161 | spin_lock_irqsave(&priv->page_lock, flags); |
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162 | fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH); |
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163 | fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], |
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164 | FE_GDMA1_MAC_ADRL); |
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165 | spin_unlock_irqrestore(&priv->page_lock, flags); |
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166 | } |
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167 | |||
168 | static int fe_set_mac_address(struct net_device *dev, void *p) |
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169 | { |
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170 | int ret = eth_mac_addr(dev, p); |
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171 | |||
172 | if (!ret) { |
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173 | struct fe_priv *priv = netdev_priv(dev); |
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174 | |||
175 | if (priv->soc->set_mac) |
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176 | priv->soc->set_mac(priv, dev->dev_addr); |
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177 | else |
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178 | fe_hw_set_macaddr(priv, p); |
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179 | } |
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180 | |||
181 | return ret; |
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182 | } |
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183 | |||
184 | static inline int fe_max_frag_size(int mtu) |
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185 | { |
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186 | /* make sure buf_size will be at least MAX_RX_LENGTH */ |
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187 | if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH) |
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188 | mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN; |
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189 | |||
190 | return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) + |
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191 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
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192 | } |
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193 | |||
194 | static inline int fe_max_buf_size(int frag_size) |
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195 | { |
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196 | int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - |
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197 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
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198 | |||
199 | BUG_ON(buf_size < MAX_RX_LENGTH); |
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200 | return buf_size; |
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201 | } |
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202 | |||
203 | static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd) |
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204 | { |
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205 | rxd->rxd1 = dma_rxd->rxd1; |
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206 | rxd->rxd2 = dma_rxd->rxd2; |
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207 | rxd->rxd3 = dma_rxd->rxd3; |
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208 | rxd->rxd4 = dma_rxd->rxd4; |
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209 | } |
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210 | |||
211 | static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd) |
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212 | { |
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213 | dma_txd->txd1 = txd->txd1; |
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214 | dma_txd->txd3 = txd->txd3; |
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215 | dma_txd->txd4 = txd->txd4; |
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216 | /* clean dma done flag last */ |
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217 | dma_txd->txd2 = txd->txd2; |
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218 | } |
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219 | |||
220 | static void fe_clean_rx(struct fe_priv *priv) |
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221 | { |
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222 | struct fe_rx_ring *ring = &priv->rx_ring; |
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223 | struct page *page; |
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224 | int i; |
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225 | |||
226 | if (ring->rx_data) { |
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227 | for (i = 0; i < ring->rx_ring_size; i++) |
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228 | if (ring->rx_data[i]) { |
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229 | if (ring->rx_dma && ring->rx_dma[i].rxd1) |
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230 | dma_unmap_single(&priv->netdev->dev, |
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231 | ring->rx_dma[i].rxd1, |
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232 | ring->rx_buf_size, |
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233 | DMA_FROM_DEVICE); |
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234 | skb_free_frag(ring->rx_data[i]); |
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235 | } |
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236 | |||
237 | kfree(ring->rx_data); |
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238 | ring->rx_data = NULL; |
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239 | } |
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240 | |||
241 | if (ring->rx_dma) { |
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242 | dma_free_coherent(&priv->netdev->dev, |
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243 | ring->rx_ring_size * sizeof(*ring->rx_dma), |
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244 | ring->rx_dma, |
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245 | ring->rx_phys); |
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246 | ring->rx_dma = NULL; |
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247 | } |
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248 | |||
249 | if (!ring->frag_cache.va) |
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250 | return; |
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251 | |||
252 | page = virt_to_page(ring->frag_cache.va); |
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253 | __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias); |
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254 | memset(&ring->frag_cache, 0, sizeof(ring->frag_cache)); |
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255 | } |
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256 | |||
257 | static int fe_alloc_rx(struct fe_priv *priv) |
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258 | { |
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259 | struct net_device *netdev = priv->netdev; |
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260 | struct fe_rx_ring *ring = &priv->rx_ring; |
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261 | int i, pad; |
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262 | |||
263 | ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data), |
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264 | GFP_KERNEL); |
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265 | if (!ring->rx_data) |
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266 | goto no_rx_mem; |
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267 | |||
268 | for (i = 0; i < ring->rx_ring_size; i++) { |
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269 | ring->rx_data[i] = page_frag_alloc(&ring->frag_cache, |
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270 | ring->frag_size, |
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271 | GFP_KERNEL); |
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272 | if (!ring->rx_data[i]) |
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273 | goto no_rx_mem; |
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274 | } |
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275 | |||
276 | ring->rx_dma = dma_alloc_coherent(&netdev->dev, |
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277 | ring->rx_ring_size * sizeof(*ring->rx_dma), |
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278 | &ring->rx_phys, |
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279 | GFP_ATOMIC | __GFP_ZERO); |
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280 | if (!ring->rx_dma) |
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281 | goto no_rx_mem; |
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282 | |||
283 | if (priv->flags & FE_FLAG_RX_2B_OFFSET) |
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284 | pad = 0; |
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285 | else |
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286 | pad = NET_IP_ALIGN; |
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287 | for (i = 0; i < ring->rx_ring_size; i++) { |
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288 | dma_addr_t dma_addr = dma_map_single(&netdev->dev, |
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289 | ring->rx_data[i] + NET_SKB_PAD + pad, |
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290 | ring->rx_buf_size, |
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291 | DMA_FROM_DEVICE); |
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292 | if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) |
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293 | goto no_rx_mem; |
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294 | ring->rx_dma[i].rxd1 = (unsigned int)dma_addr; |
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295 | |||
296 | if (priv->flags & FE_FLAG_RX_SG_DMA) |
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297 | ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size); |
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298 | else |
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299 | ring->rx_dma[i].rxd2 = RX_DMA_LSO; |
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300 | } |
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301 | ring->rx_calc_idx = ring->rx_ring_size - 1; |
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302 | /* make sure that all changes to the dma ring are flushed before we |
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303 | * continue |
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304 | */ |
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305 | wmb(); |
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306 | |||
307 | fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0); |
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308 | fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0); |
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309 | fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0); |
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310 | fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG); |
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311 | |||
312 | return 0; |
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313 | |||
314 | no_rx_mem: |
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315 | return -ENOMEM; |
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316 | } |
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317 | |||
318 | static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf) |
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319 | { |
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320 | if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) { |
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321 | dma_unmap_single(dev, |
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322 | dma_unmap_addr(tx_buf, dma_addr0), |
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323 | dma_unmap_len(tx_buf, dma_len0), |
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324 | DMA_TO_DEVICE); |
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325 | } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) { |
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326 | dma_unmap_page(dev, |
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327 | dma_unmap_addr(tx_buf, dma_addr0), |
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328 | dma_unmap_len(tx_buf, dma_len0), |
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329 | DMA_TO_DEVICE); |
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330 | } |
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331 | if (tx_buf->flags & FE_TX_FLAGS_PAGE1) |
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332 | dma_unmap_page(dev, |
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333 | dma_unmap_addr(tx_buf, dma_addr1), |
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334 | dma_unmap_len(tx_buf, dma_len1), |
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335 | DMA_TO_DEVICE); |
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336 | |||
337 | tx_buf->flags = 0; |
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338 | if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC)) |
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339 | dev_kfree_skb_any(tx_buf->skb); |
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340 | tx_buf->skb = NULL; |
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341 | } |
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342 | |||
343 | static void fe_clean_tx(struct fe_priv *priv) |
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344 | { |
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345 | int i; |
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346 | struct device *dev = &priv->netdev->dev; |
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347 | struct fe_tx_ring *ring = &priv->tx_ring; |
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348 | |||
349 | if (ring->tx_buf) { |
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350 | for (i = 0; i < ring->tx_ring_size; i++) |
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351 | fe_txd_unmap(dev, &ring->tx_buf[i]); |
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352 | kfree(ring->tx_buf); |
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353 | ring->tx_buf = NULL; |
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354 | } |
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355 | |||
356 | if (ring->tx_dma) { |
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357 | dma_free_coherent(dev, |
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358 | ring->tx_ring_size * sizeof(*ring->tx_dma), |
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359 | ring->tx_dma, |
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360 | ring->tx_phys); |
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361 | ring->tx_dma = NULL; |
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362 | } |
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363 | |||
364 | netdev_reset_queue(priv->netdev); |
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365 | } |
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366 | |||
367 | static int fe_alloc_tx(struct fe_priv *priv) |
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368 | { |
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369 | int i; |
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370 | struct fe_tx_ring *ring = &priv->tx_ring; |
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371 | |||
372 | ring->tx_free_idx = 0; |
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373 | ring->tx_next_idx = 0; |
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374 | ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, |
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375 | MAX_SKB_FRAGS); |
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376 | |||
377 | ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf), |
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378 | GFP_KERNEL); |
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379 | if (!ring->tx_buf) |
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380 | goto no_tx_mem; |
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381 | |||
382 | ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev, |
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383 | ring->tx_ring_size * sizeof(*ring->tx_dma), |
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384 | &ring->tx_phys, |
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385 | GFP_ATOMIC | __GFP_ZERO); |
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386 | if (!ring->tx_dma) |
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387 | goto no_tx_mem; |
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388 | |||
389 | for (i = 0; i < ring->tx_ring_size; i++) { |
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390 | if (priv->soc->tx_dma) |
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391 | priv->soc->tx_dma(&ring->tx_dma[i]); |
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392 | ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF; |
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393 | } |
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394 | /* make sure that all changes to the dma ring are flushed before we |
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395 | * continue |
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396 | */ |
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397 | wmb(); |
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398 | |||
399 | fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0); |
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400 | fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0); |
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401 | fe_reg_w32(0, FE_REG_TX_CTX_IDX0); |
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402 | fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG); |
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403 | |||
404 | return 0; |
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405 | |||
406 | no_tx_mem: |
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407 | return -ENOMEM; |
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408 | } |
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409 | |||
410 | static int fe_init_dma(struct fe_priv *priv) |
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411 | { |
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412 | int err; |
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413 | |||
414 | err = fe_alloc_tx(priv); |
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415 | if (err) |
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416 | return err; |
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417 | |||
418 | err = fe_alloc_rx(priv); |
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419 | if (err) |
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420 | return err; |
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421 | |||
422 | return 0; |
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423 | } |
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424 | |||
425 | static void fe_free_dma(struct fe_priv *priv) |
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426 | { |
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427 | fe_clean_tx(priv); |
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428 | fe_clean_rx(priv); |
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429 | } |
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430 | |||
431 | void fe_stats_update(struct fe_priv *priv) |
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432 | { |
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433 | struct fe_hw_stats *hwstats = priv->hw_stats; |
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434 | unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE]; |
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435 | u64 stats; |
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436 | |||
437 | u64_stats_update_begin(&hwstats->syncp); |
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438 | |||
439 | if (IS_ENABLED(CONFIG_SOC_MT7621)) { |
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440 | hwstats->rx_bytes += fe_r32(base); |
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441 | stats = fe_r32(base + 0x04); |
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442 | if (stats) |
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443 | hwstats->rx_bytes += (stats << 32); |
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444 | hwstats->rx_packets += fe_r32(base + 0x08); |
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445 | hwstats->rx_overflow += fe_r32(base + 0x10); |
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446 | hwstats->rx_fcs_errors += fe_r32(base + 0x14); |
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447 | hwstats->rx_short_errors += fe_r32(base + 0x18); |
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448 | hwstats->rx_long_errors += fe_r32(base + 0x1c); |
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449 | hwstats->rx_checksum_errors += fe_r32(base + 0x20); |
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450 | hwstats->rx_flow_control_packets += fe_r32(base + 0x24); |
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451 | hwstats->tx_skip += fe_r32(base + 0x28); |
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452 | hwstats->tx_collisions += fe_r32(base + 0x2c); |
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453 | hwstats->tx_bytes += fe_r32(base + 0x30); |
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454 | stats = fe_r32(base + 0x34); |
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455 | if (stats) |
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456 | hwstats->tx_bytes += (stats << 32); |
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457 | hwstats->tx_packets += fe_r32(base + 0x38); |
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458 | } else { |
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459 | hwstats->tx_bytes += fe_r32(base); |
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460 | hwstats->tx_packets += fe_r32(base + 0x04); |
||
461 | hwstats->tx_skip += fe_r32(base + 0x08); |
||
462 | hwstats->tx_collisions += fe_r32(base + 0x0c); |
||
463 | hwstats->rx_bytes += fe_r32(base + 0x20); |
||
464 | hwstats->rx_packets += fe_r32(base + 0x24); |
||
465 | hwstats->rx_overflow += fe_r32(base + 0x28); |
||
466 | hwstats->rx_fcs_errors += fe_r32(base + 0x2c); |
||
467 | hwstats->rx_short_errors += fe_r32(base + 0x30); |
||
468 | hwstats->rx_long_errors += fe_r32(base + 0x34); |
||
469 | hwstats->rx_checksum_errors += fe_r32(base + 0x38); |
||
470 | hwstats->rx_flow_control_packets += fe_r32(base + 0x3c); |
||
471 | } |
||
472 | |||
473 | u64_stats_update_end(&hwstats->syncp); |
||
474 | } |
||
475 | |||
476 | static void fe_get_stats64(struct net_device *dev, |
||
477 | struct rtnl_link_stats64 *storage) |
||
478 | { |
||
479 | struct fe_priv *priv = netdev_priv(dev); |
||
480 | struct fe_hw_stats *hwstats = priv->hw_stats; |
||
481 | unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE]; |
||
482 | unsigned int start; |
||
483 | |||
484 | if (!base) { |
||
485 | netdev_stats_to_stats64(storage, &dev->stats); |
||
486 | return; |
||
487 | } |
||
488 | |||
489 | if (netif_running(dev) && netif_device_present(dev)) { |
||
490 | if (spin_trylock_bh(&hwstats->stats_lock)) { |
||
491 | fe_stats_update(priv); |
||
492 | spin_unlock_bh(&hwstats->stats_lock); |
||
493 | } |
||
494 | } |
||
495 | |||
496 | do { |
||
497 | start = u64_stats_fetch_begin_irq(&hwstats->syncp); |
||
498 | storage->rx_packets = hwstats->rx_packets; |
||
499 | storage->tx_packets = hwstats->tx_packets; |
||
500 | storage->rx_bytes = hwstats->rx_bytes; |
||
501 | storage->tx_bytes = hwstats->tx_bytes; |
||
502 | storage->collisions = hwstats->tx_collisions; |
||
503 | storage->rx_length_errors = hwstats->rx_short_errors + |
||
504 | hwstats->rx_long_errors; |
||
505 | storage->rx_over_errors = hwstats->rx_overflow; |
||
506 | storage->rx_crc_errors = hwstats->rx_fcs_errors; |
||
507 | storage->rx_errors = hwstats->rx_checksum_errors; |
||
508 | storage->tx_aborted_errors = hwstats->tx_skip; |
||
509 | } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); |
||
510 | |||
511 | storage->tx_errors = priv->netdev->stats.tx_errors; |
||
512 | storage->rx_dropped = priv->netdev->stats.rx_dropped; |
||
513 | storage->tx_dropped = priv->netdev->stats.tx_dropped; |
||
514 | } |
||
515 | |||
516 | static int fe_vlan_rx_add_vid(struct net_device *dev, |
||
517 | __be16 proto, u16 vid) |
||
518 | { |
||
519 | struct fe_priv *priv = netdev_priv(dev); |
||
520 | u32 idx = (vid & 0xf); |
||
521 | u32 vlan_cfg; |
||
522 | |||
523 | if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) && |
||
524 | (dev->features & NETIF_F_HW_VLAN_CTAG_TX))) |
||
525 | return 0; |
||
526 | |||
527 | if (test_bit(idx, &priv->vlan_map)) { |
||
528 | netdev_warn(dev, "disable tx vlan offload\n"); |
||
529 | dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
||
530 | netdev_update_features(dev); |
||
531 | } else { |
||
532 | vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] + |
||
533 | ((idx >> 1) << 2)); |
||
534 | if (idx & 0x1) { |
||
535 | vlan_cfg &= 0xffff; |
||
536 | vlan_cfg |= (vid << 16); |
||
537 | } else { |
||
538 | vlan_cfg &= 0xffff0000; |
||
539 | vlan_cfg |= vid; |
||
540 | } |
||
541 | fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] + |
||
542 | ((idx >> 1) << 2)); |
||
543 | set_bit(idx, &priv->vlan_map); |
||
544 | } |
||
545 | |||
546 | return 0; |
||
547 | } |
||
548 | |||
549 | static int fe_vlan_rx_kill_vid(struct net_device *dev, |
||
550 | __be16 proto, u16 vid) |
||
551 | { |
||
552 | struct fe_priv *priv = netdev_priv(dev); |
||
553 | u32 idx = (vid & 0xf); |
||
554 | |||
555 | if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) && |
||
556 | (dev->features & NETIF_F_HW_VLAN_CTAG_TX))) |
||
557 | return 0; |
||
558 | |||
559 | clear_bit(idx, &priv->vlan_map); |
||
560 | |||
561 | return 0; |
||
562 | } |
||
563 | |||
564 | static inline u32 fe_empty_txd(struct fe_tx_ring *ring) |
||
565 | { |
||
566 | barrier(); |
||
567 | return (u32)(ring->tx_ring_size - |
||
568 | ((ring->tx_next_idx - ring->tx_free_idx) & |
||
569 | (ring->tx_ring_size - 1))); |
||
570 | } |
||
571 | |||
572 | static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev, |
||
573 | int tx_num, struct fe_tx_ring *ring) |
||
574 | { |
||
575 | struct fe_priv *priv = netdev_priv(dev); |
||
576 | struct skb_frag_struct *frag; |
||
577 | struct fe_tx_dma txd, *ptxd; |
||
578 | struct fe_tx_buf *tx_buf; |
||
579 | dma_addr_t mapped_addr; |
||
580 | unsigned int nr_frags; |
||
581 | u32 def_txd4; |
||
582 | int i, j, k, frag_size, frag_map_size, offset; |
||
583 | |||
584 | tx_buf = &ring->tx_buf[ring->tx_next_idx]; |
||
585 | memset(tx_buf, 0, sizeof(*tx_buf)); |
||
586 | memset(&txd, 0, sizeof(txd)); |
||
587 | nr_frags = skb_shinfo(skb)->nr_frags; |
||
588 | |||
589 | /* init tx descriptor */ |
||
590 | if (priv->soc->tx_dma) |
||
591 | priv->soc->tx_dma(&txd); |
||
592 | else |
||
593 | txd.txd4 = TX_DMA_DESP4_DEF; |
||
594 | def_txd4 = txd.txd4; |
||
595 | |||
596 | /* TX Checksum offload */ |
||
597 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
||
598 | txd.txd4 |= TX_DMA_CHKSUM; |
||
599 | |||
600 | /* VLAN header offload */ |
||
601 | if (skb_vlan_tag_present(skb)) { |
||
602 | u16 tag = skb_vlan_tag_get(skb); |
||
603 | |||
604 | if (IS_ENABLED(CONFIG_SOC_MT7621)) |
||
605 | txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag; |
||
606 | else |
||
607 | txd.txd4 |= TX_DMA_INS_VLAN | |
||
608 | ((tag >> VLAN_PRIO_SHIFT) << 4) | |
||
609 | (tag & 0xF); |
||
610 | } |
||
611 | |||
612 | /* TSO: fill MSS info in tcp checksum field */ |
||
613 | if (skb_is_gso(skb)) { |
||
614 | if (skb_cow_head(skb, 0)) { |
||
615 | netif_warn(priv, tx_err, dev, |
||
616 | "GSO expand head fail.\n"); |
||
617 | goto err_out; |
||
618 | } |
||
619 | if (skb_shinfo(skb)->gso_type & |
||
620 | (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
||
621 | txd.txd4 |= TX_DMA_TSO; |
||
622 | tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); |
||
623 | } |
||
624 | } |
||
625 | |||
626 | mapped_addr = dma_map_single(&dev->dev, skb->data, |
||
627 | skb_headlen(skb), DMA_TO_DEVICE); |
||
628 | if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) |
||
629 | goto err_out; |
||
630 | txd.txd1 = mapped_addr; |
||
631 | txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb)); |
||
632 | |||
633 | tx_buf->flags |= FE_TX_FLAGS_SINGLE0; |
||
634 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
||
635 | dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb)); |
||
636 | |||
637 | /* TX SG offload */ |
||
638 | j = ring->tx_next_idx; |
||
639 | k = 0; |
||
640 | for (i = 0; i < nr_frags; i++) { |
||
641 | offset = 0; |
||
642 | frag = &skb_shinfo(skb)->frags[i]; |
||
643 | frag_size = skb_frag_size(frag); |
||
644 | |||
645 | while (frag_size > 0) { |
||
646 | frag_map_size = min(frag_size, TX_DMA_BUF_LEN); |
||
647 | mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset, |
||
648 | frag_map_size, |
||
649 | DMA_TO_DEVICE); |
||
650 | if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) |
||
651 | goto err_dma; |
||
652 | |||
653 | if (k & 0x1) { |
||
654 | j = NEXT_TX_DESP_IDX(j); |
||
655 | txd.txd1 = mapped_addr; |
||
656 | txd.txd2 = TX_DMA_PLEN0(frag_map_size); |
||
657 | txd.txd4 = def_txd4; |
||
658 | |||
659 | tx_buf = &ring->tx_buf[j]; |
||
660 | memset(tx_buf, 0, sizeof(*tx_buf)); |
||
661 | |||
662 | tx_buf->flags |= FE_TX_FLAGS_PAGE0; |
||
663 | dma_unmap_addr_set(tx_buf, dma_addr0, |
||
664 | mapped_addr); |
||
665 | dma_unmap_len_set(tx_buf, dma_len0, |
||
666 | frag_map_size); |
||
667 | } else { |
||
668 | txd.txd3 = mapped_addr; |
||
669 | txd.txd2 |= TX_DMA_PLEN1(frag_map_size); |
||
670 | |||
671 | tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC; |
||
672 | tx_buf->flags |= FE_TX_FLAGS_PAGE1; |
||
673 | dma_unmap_addr_set(tx_buf, dma_addr1, |
||
674 | mapped_addr); |
||
675 | dma_unmap_len_set(tx_buf, dma_len1, |
||
676 | frag_map_size); |
||
677 | |||
678 | if (!((i == (nr_frags - 1)) && |
||
679 | (frag_map_size == frag_size))) { |
||
680 | fe_set_txd(&txd, &ring->tx_dma[j]); |
||
681 | memset(&txd, 0, sizeof(txd)); |
||
682 | } |
||
683 | } |
||
684 | frag_size -= frag_map_size; |
||
685 | offset += frag_map_size; |
||
686 | k++; |
||
687 | } |
||
688 | } |
||
689 | |||
690 | /* set last segment */ |
||
691 | if (k & 0x1) |
||
692 | txd.txd2 |= TX_DMA_LS1; |
||
693 | else |
||
694 | txd.txd2 |= TX_DMA_LS0; |
||
695 | fe_set_txd(&txd, &ring->tx_dma[j]); |
||
696 | |||
697 | /* store skb to cleanup */ |
||
698 | tx_buf->skb = skb; |
||
699 | |||
700 | netdev_sent_queue(dev, skb->len); |
||
701 | skb_tx_timestamp(skb); |
||
702 | |||
703 | ring->tx_next_idx = NEXT_TX_DESP_IDX(j); |
||
704 | /* make sure that all changes to the dma ring are flushed before we |
||
705 | * continue |
||
706 | */ |
||
707 | wmb(); |
||
708 | if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) { |
||
709 | netif_stop_queue(dev); |
||
710 | smp_mb(); |
||
711 | if (unlikely(fe_empty_txd(ring) > ring->tx_thresh)) |
||
712 | netif_wake_queue(dev); |
||
713 | } |
||
714 | |||
715 | if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) |
||
716 | fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0); |
||
717 | |||
718 | return 0; |
||
719 | |||
720 | err_dma: |
||
721 | j = ring->tx_next_idx; |
||
722 | for (i = 0; i < tx_num; i++) { |
||
723 | ptxd = &ring->tx_dma[j]; |
||
724 | tx_buf = &ring->tx_buf[j]; |
||
725 | |||
726 | /* unmap dma */ |
||
727 | fe_txd_unmap(&dev->dev, tx_buf); |
||
728 | |||
729 | ptxd->txd2 = TX_DMA_DESP2_DEF; |
||
730 | j = NEXT_TX_DESP_IDX(j); |
||
731 | } |
||
732 | /* make sure that all changes to the dma ring are flushed before we |
||
733 | * continue |
||
734 | */ |
||
735 | wmb(); |
||
736 | |||
737 | err_out: |
||
738 | return -1; |
||
739 | } |
||
740 | |||
741 | static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) |
||
742 | { |
||
743 | unsigned int len; |
||
744 | int ret; |
||
745 | |||
746 | ret = 0; |
||
747 | if (unlikely(skb->len < VLAN_ETH_ZLEN)) { |
||
748 | if ((priv->flags & FE_FLAG_PADDING_64B) && |
||
749 | !(priv->flags & FE_FLAG_PADDING_BUG)) |
||
750 | return ret; |
||
751 | |||
752 | if (skb_vlan_tag_present(skb)) |
||
753 | len = ETH_ZLEN; |
||
754 | else if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) |
||
755 | len = VLAN_ETH_ZLEN; |
||
756 | else if (!(priv->flags & FE_FLAG_PADDING_64B)) |
||
757 | len = ETH_ZLEN; |
||
758 | else |
||
759 | return ret; |
||
760 | |||
761 | if (skb->len < len) { |
||
762 | ret = skb_pad(skb, len - skb->len); |
||
763 | if (ret < 0) |
||
764 | return ret; |
||
765 | skb->len = len; |
||
766 | skb_set_tail_pointer(skb, len); |
||
767 | } |
||
768 | } |
||
769 | |||
770 | return ret; |
||
771 | } |
||
772 | |||
773 | static inline int fe_cal_txd_req(struct sk_buff *skb) |
||
774 | { |
||
775 | int i, nfrags; |
||
776 | struct skb_frag_struct *frag; |
||
777 | |||
778 | nfrags = 1; |
||
779 | if (skb_is_gso(skb)) { |
||
780 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
||
781 | frag = &skb_shinfo(skb)->frags[i]; |
||
782 | nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN); |
||
783 | } |
||
784 | } else { |
||
785 | nfrags += skb_shinfo(skb)->nr_frags; |
||
786 | } |
||
787 | |||
788 | return DIV_ROUND_UP(nfrags, 2); |
||
789 | } |
||
790 | |||
791 | static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev) |
||
792 | { |
||
793 | struct fe_priv *priv = netdev_priv(dev); |
||
794 | struct fe_tx_ring *ring = &priv->tx_ring; |
||
795 | struct net_device_stats *stats = &dev->stats; |
||
796 | int tx_num; |
||
797 | int len = skb->len; |
||
798 | |||
799 | if (fe_skb_padto(skb, priv)) { |
||
800 | netif_warn(priv, tx_err, dev, "tx padding failed!\n"); |
||
801 | return NETDEV_TX_OK; |
||
802 | } |
||
803 | |||
804 | tx_num = fe_cal_txd_req(skb); |
||
805 | if (unlikely(fe_empty_txd(ring) <= tx_num)) { |
||
806 | netif_stop_queue(dev); |
||
807 | netif_err(priv, tx_queued, dev, |
||
808 | "Tx Ring full when queue awake!\n"); |
||
809 | return NETDEV_TX_BUSY; |
||
810 | } |
||
811 | |||
812 | if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) { |
||
813 | stats->tx_dropped++; |
||
814 | } else { |
||
815 | stats->tx_packets++; |
||
816 | stats->tx_bytes += len; |
||
817 | } |
||
818 | |||
819 | return NETDEV_TX_OK; |
||
820 | } |
||
821 | |||
822 | static int fe_poll_rx(struct napi_struct *napi, int budget, |
||
823 | struct fe_priv *priv, u32 rx_intr) |
||
824 | { |
||
825 | struct net_device *netdev = priv->netdev; |
||
826 | struct net_device_stats *stats = &netdev->stats; |
||
827 | struct fe_soc_data *soc = priv->soc; |
||
828 | struct fe_rx_ring *ring = &priv->rx_ring; |
||
829 | int idx = ring->rx_calc_idx; |
||
830 | u32 checksum_bit; |
||
831 | struct sk_buff *skb; |
||
832 | u8 *data, *new_data; |
||
833 | struct fe_rx_dma *rxd, trxd; |
||
834 | int done = 0, pad; |
||
835 | |||
836 | if (netdev->features & NETIF_F_RXCSUM) |
||
837 | checksum_bit = soc->checksum_bit; |
||
838 | else |
||
839 | checksum_bit = 0; |
||
840 | |||
841 | if (priv->flags & FE_FLAG_RX_2B_OFFSET) |
||
842 | pad = 0; |
||
843 | else |
||
844 | pad = NET_IP_ALIGN; |
||
845 | |||
846 | while (done < budget) { |
||
847 | unsigned int pktlen; |
||
848 | dma_addr_t dma_addr; |
||
849 | |||
850 | idx = NEXT_RX_DESP_IDX(idx); |
||
851 | rxd = &ring->rx_dma[idx]; |
||
852 | data = ring->rx_data[idx]; |
||
853 | |||
854 | fe_get_rxd(&trxd, rxd); |
||
855 | if (!(trxd.rxd2 & RX_DMA_DONE)) |
||
856 | break; |
||
857 | |||
858 | /* alloc new buffer */ |
||
859 | new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size, |
||
860 | GFP_ATOMIC); |
||
861 | if (unlikely(!new_data)) { |
||
862 | stats->rx_dropped++; |
||
863 | goto release_desc; |
||
864 | } |
||
865 | dma_addr = dma_map_single(&netdev->dev, |
||
866 | new_data + NET_SKB_PAD + pad, |
||
867 | ring->rx_buf_size, |
||
868 | DMA_FROM_DEVICE); |
||
869 | if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) { |
||
870 | skb_free_frag(new_data); |
||
871 | goto release_desc; |
||
872 | } |
||
873 | |||
874 | /* receive data */ |
||
875 | skb = build_skb(data, ring->frag_size); |
||
876 | if (unlikely(!skb)) { |
||
877 | skb_free_frag(new_data); |
||
878 | goto release_desc; |
||
879 | } |
||
880 | skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); |
||
881 | |||
882 | dma_unmap_single(&netdev->dev, trxd.rxd1, |
||
883 | ring->rx_buf_size, DMA_FROM_DEVICE); |
||
884 | pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); |
||
885 | skb->dev = netdev; |
||
886 | skb_put(skb, pktlen); |
||
887 | if (trxd.rxd4 & checksum_bit) |
||
888 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
||
889 | else |
||
890 | skb_checksum_none_assert(skb); |
||
891 | skb->protocol = eth_type_trans(skb, netdev); |
||
892 | |||
893 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
894 | if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) { |
||
895 | #endif |
||
896 | stats->rx_packets++; |
||
897 | stats->rx_bytes += pktlen; |
||
898 | |||
899 | napi_gro_receive(napi, skb); |
||
900 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
901 | } else { |
||
902 | dev_kfree_skb(skb); |
||
903 | } |
||
904 | #endif |
||
905 | ring->rx_data[idx] = new_data; |
||
906 | rxd->rxd1 = (unsigned int)dma_addr; |
||
907 | |||
908 | release_desc: |
||
909 | if (priv->flags & FE_FLAG_RX_SG_DMA) |
||
910 | rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size); |
||
911 | else |
||
912 | rxd->rxd2 = RX_DMA_LSO; |
||
913 | |||
914 | ring->rx_calc_idx = idx; |
||
915 | /* make sure that all changes to the dma ring are flushed before |
||
916 | * we continue |
||
917 | */ |
||
918 | wmb(); |
||
919 | fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0); |
||
920 | done++; |
||
921 | } |
||
922 | |||
923 | if (done < budget) |
||
924 | fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS); |
||
925 | |||
926 | return done; |
||
927 | } |
||
928 | |||
929 | static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr, |
||
930 | int *tx_again) |
||
931 | { |
||
932 | struct net_device *netdev = priv->netdev; |
||
933 | struct device *dev = &netdev->dev; |
||
934 | unsigned int bytes_compl = 0; |
||
935 | struct sk_buff *skb; |
||
936 | struct fe_tx_buf *tx_buf; |
||
937 | int done = 0; |
||
938 | u32 idx, hwidx; |
||
939 | struct fe_tx_ring *ring = &priv->tx_ring; |
||
940 | |||
941 | idx = ring->tx_free_idx; |
||
942 | hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0); |
||
943 | |||
944 | while ((idx != hwidx) && budget) { |
||
945 | tx_buf = &ring->tx_buf[idx]; |
||
946 | skb = tx_buf->skb; |
||
947 | |||
948 | if (!skb) |
||
949 | break; |
||
950 | |||
951 | if (skb != (struct sk_buff *)DMA_DUMMY_DESC) { |
||
952 | bytes_compl += skb->len; |
||
953 | done++; |
||
954 | budget--; |
||
955 | } |
||
956 | fe_txd_unmap(dev, tx_buf); |
||
957 | idx = NEXT_TX_DESP_IDX(idx); |
||
958 | } |
||
959 | ring->tx_free_idx = idx; |
||
960 | |||
961 | if (idx == hwidx) { |
||
962 | /* read hw index again make sure no new tx packet */ |
||
963 | hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0); |
||
964 | if (idx == hwidx) |
||
965 | fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS); |
||
966 | else |
||
967 | *tx_again = 1; |
||
968 | } else { |
||
969 | *tx_again = 1; |
||
970 | } |
||
971 | |||
972 | if (done) { |
||
973 | netdev_completed_queue(netdev, done, bytes_compl); |
||
974 | smp_mb(); |
||
975 | if (unlikely(netif_queue_stopped(netdev) && |
||
976 | (fe_empty_txd(ring) > ring->tx_thresh))) |
||
977 | netif_wake_queue(netdev); |
||
978 | } |
||
979 | |||
980 | return done; |
||
981 | } |
||
982 | |||
983 | static int fe_poll(struct napi_struct *napi, int budget) |
||
984 | { |
||
985 | struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi); |
||
986 | struct fe_hw_stats *hwstat = priv->hw_stats; |
||
987 | int tx_done, rx_done, tx_again; |
||
988 | u32 status, fe_status, status_reg, mask; |
||
989 | u32 tx_intr, rx_intr, status_intr; |
||
990 | |||
991 | status = fe_reg_r32(FE_REG_FE_INT_STATUS); |
||
992 | fe_status = status; |
||
993 | tx_intr = priv->soc->tx_int; |
||
994 | rx_intr = priv->soc->rx_int; |
||
995 | status_intr = priv->soc->status_int; |
||
996 | tx_done = 0; |
||
997 | rx_done = 0; |
||
998 | tx_again = 0; |
||
999 | |||
1000 | if (fe_reg_table[FE_REG_FE_INT_STATUS2]) { |
||
1001 | fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2); |
||
1002 | status_reg = FE_REG_FE_INT_STATUS2; |
||
1003 | } else { |
||
1004 | status_reg = FE_REG_FE_INT_STATUS; |
||
1005 | } |
||
1006 | |||
1007 | if (status & tx_intr) |
||
1008 | tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again); |
||
1009 | |||
1010 | if (status & rx_intr) |
||
1011 | rx_done = fe_poll_rx(napi, budget, priv, rx_intr); |
||
1012 | |||
1013 | if (unlikely(fe_status & status_intr)) { |
||
1014 | if (hwstat && spin_trylock(&hwstat->stats_lock)) { |
||
1015 | fe_stats_update(priv); |
||
1016 | spin_unlock(&hwstat->stats_lock); |
||
1017 | } |
||
1018 | fe_reg_w32(status_intr, status_reg); |
||
1019 | } |
||
1020 | |||
1021 | if (unlikely(netif_msg_intr(priv))) { |
||
1022 | mask = fe_reg_r32(FE_REG_FE_INT_ENABLE); |
||
1023 | netdev_info(priv->netdev, |
||
1024 | "done tx %d, rx %d, intr 0x%08x/0x%x\n", |
||
1025 | tx_done, rx_done, status, mask); |
||
1026 | } |
||
1027 | |||
1028 | if (!tx_again && (rx_done < budget)) { |
||
1029 | status = fe_reg_r32(FE_REG_FE_INT_STATUS); |
||
1030 | if (status & (tx_intr | rx_intr)) { |
||
1031 | /* let napi poll again */ |
||
1032 | rx_done = budget; |
||
1033 | goto poll_again; |
||
1034 | } |
||
1035 | |||
1036 | napi_complete_done(napi, rx_done); |
||
1037 | fe_int_enable(tx_intr | rx_intr); |
||
1038 | } else { |
||
1039 | rx_done = budget; |
||
1040 | } |
||
1041 | |||
1042 | poll_again: |
||
1043 | return rx_done; |
||
1044 | } |
||
1045 | |||
1046 | static void fe_tx_timeout(struct net_device *dev) |
||
1047 | { |
||
1048 | struct fe_priv *priv = netdev_priv(dev); |
||
1049 | struct fe_tx_ring *ring = &priv->tx_ring; |
||
1050 | |||
1051 | priv->netdev->stats.tx_errors++; |
||
1052 | netif_err(priv, tx_err, dev, |
||
1053 | "transmit timed out\n"); |
||
1054 | netif_info(priv, drv, dev, "dma_cfg:%08x\n", |
||
1055 | fe_reg_r32(FE_REG_PDMA_GLO_CFG)); |
||
1056 | netif_info(priv, drv, dev, "tx_ring=%d, " |
||
1057 | "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", |
||
1058 | 0, fe_reg_r32(FE_REG_TX_BASE_PTR0), |
||
1059 | fe_reg_r32(FE_REG_TX_MAX_CNT0), |
||
1060 | fe_reg_r32(FE_REG_TX_CTX_IDX0), |
||
1061 | fe_reg_r32(FE_REG_TX_DTX_IDX0), |
||
1062 | ring->tx_free_idx, |
||
1063 | ring->tx_next_idx); |
||
1064 | netif_info(priv, drv, dev, |
||
1065 | "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n", |
||
1066 | 0, fe_reg_r32(FE_REG_RX_BASE_PTR0), |
||
1067 | fe_reg_r32(FE_REG_RX_MAX_CNT0), |
||
1068 | fe_reg_r32(FE_REG_RX_CALC_IDX0), |
||
1069 | fe_reg_r32(FE_REG_RX_DRX_IDX0)); |
||
1070 | |||
1071 | if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags)) |
||
1072 | schedule_work(&priv->pending_work); |
||
1073 | } |
||
1074 | |||
1075 | static irqreturn_t fe_handle_irq(int irq, void *dev) |
||
1076 | { |
||
1077 | struct fe_priv *priv = netdev_priv(dev); |
||
1078 | u32 status, int_mask; |
||
1079 | |||
1080 | status = fe_reg_r32(FE_REG_FE_INT_STATUS); |
||
1081 | |||
1082 | if (unlikely(!status)) |
||
1083 | return IRQ_NONE; |
||
1084 | |||
1085 | int_mask = (priv->soc->rx_int | priv->soc->tx_int); |
||
1086 | if (likely(status & int_mask)) { |
||
1087 | if (likely(napi_schedule_prep(&priv->rx_napi))) { |
||
1088 | fe_int_disable(int_mask); |
||
1089 | __napi_schedule(&priv->rx_napi); |
||
1090 | } |
||
1091 | } else { |
||
1092 | fe_reg_w32(status, FE_REG_FE_INT_STATUS); |
||
1093 | } |
||
1094 | |||
1095 | return IRQ_HANDLED; |
||
1096 | } |
||
1097 | |||
1098 | #ifdef CONFIG_NET_POLL_CONTROLLER |
||
1099 | static void fe_poll_controller(struct net_device *dev) |
||
1100 | { |
||
1101 | struct fe_priv *priv = netdev_priv(dev); |
||
1102 | u32 int_mask = priv->soc->tx_int | priv->soc->rx_int; |
||
1103 | |||
1104 | fe_int_disable(int_mask); |
||
1105 | fe_handle_irq(dev->irq, dev); |
||
1106 | fe_int_enable(int_mask); |
||
1107 | } |
||
1108 | #endif |
||
1109 | |||
1110 | int fe_set_clock_cycle(struct fe_priv *priv) |
||
1111 | { |
||
1112 | unsigned long sysclk = priv->sysclk; |
||
1113 | |||
1114 | sysclk /= FE_US_CYC_CNT_DIVISOR; |
||
1115 | sysclk <<= FE_US_CYC_CNT_SHIFT; |
||
1116 | |||
1117 | fe_w32((fe_r32(FE_FE_GLO_CFG) & |
||
1118 | ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | |
||
1119 | sysclk, |
||
1120 | FE_FE_GLO_CFG); |
||
1121 | return 0; |
||
1122 | } |
||
1123 | |||
1124 | void fe_fwd_config(struct fe_priv *priv) |
||
1125 | { |
||
1126 | u32 fwd_cfg; |
||
1127 | |||
1128 | fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG); |
||
1129 | |||
1130 | /* disable jumbo frame */ |
||
1131 | if (priv->flags & FE_FLAG_JUMBO_FRAME) |
||
1132 | fwd_cfg &= ~FE_GDM1_JMB_EN; |
||
1133 | |||
1134 | /* set unicast/multicast/broadcast frame to cpu */ |
||
1135 | fwd_cfg &= ~0xffff; |
||
1136 | |||
1137 | fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG); |
||
1138 | } |
||
1139 | |||
1140 | static void fe_rxcsum_config(bool enable) |
||
1141 | { |
||
1142 | if (enable) |
||
1143 | fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | |
||
1144 | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN), |
||
1145 | FE_GDMA1_FWD_CFG); |
||
1146 | else |
||
1147 | fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN | |
||
1148 | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN), |
||
1149 | FE_GDMA1_FWD_CFG); |
||
1150 | } |
||
1151 | |||
1152 | static void fe_txcsum_config(bool enable) |
||
1153 | { |
||
1154 | if (enable) |
||
1155 | fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | |
||
1156 | FE_TCS_GEN_EN | FE_UCS_GEN_EN), |
||
1157 | FE_CDMA_CSG_CFG); |
||
1158 | else |
||
1159 | fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN | |
||
1160 | FE_TCS_GEN_EN | FE_UCS_GEN_EN), |
||
1161 | FE_CDMA_CSG_CFG); |
||
1162 | } |
||
1163 | |||
1164 | void fe_csum_config(struct fe_priv *priv) |
||
1165 | { |
||
1166 | struct net_device *dev = priv_netdev(priv); |
||
1167 | |||
1168 | fe_txcsum_config((dev->features & NETIF_F_IP_CSUM)); |
||
1169 | fe_rxcsum_config((dev->features & NETIF_F_RXCSUM)); |
||
1170 | } |
||
1171 | |||
1172 | static int fe_hw_init(struct net_device *dev) |
||
1173 | { |
||
1174 | struct fe_priv *priv = netdev_priv(dev); |
||
1175 | int i, err; |
||
1176 | |||
1177 | err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0, |
||
1178 | dev_name(priv->dev), dev); |
||
1179 | if (err) |
||
1180 | return err; |
||
1181 | |||
1182 | if (priv->soc->set_mac) |
||
1183 | priv->soc->set_mac(priv, dev->dev_addr); |
||
1184 | else |
||
1185 | fe_hw_set_macaddr(priv, dev->dev_addr); |
||
1186 | |||
1187 | /* disable delay interrupt */ |
||
1188 | fe_reg_w32(0, FE_REG_DLY_INT_CFG); |
||
1189 | |||
1190 | fe_int_disable(priv->soc->tx_int | priv->soc->rx_int); |
||
1191 | |||
1192 | /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */ |
||
1193 | if (fe_reg_table[FE_REG_FE_DMA_VID_BASE]) |
||
1194 | for (i = 0; i < 16; i += 2) |
||
1195 | fe_w32(((i + 1) << 16) + i, |
||
1196 | fe_reg_table[FE_REG_FE_DMA_VID_BASE] + |
||
1197 | (i * 2)); |
||
1198 | |||
1199 | if (priv->soc->fwd_config(priv)) |
||
1200 | netdev_err(dev, "unable to get clock\n"); |
||
1201 | |||
1202 | if (fe_reg_table[FE_REG_FE_RST_GL]) { |
||
1203 | fe_reg_w32(1, FE_REG_FE_RST_GL); |
||
1204 | fe_reg_w32(0, FE_REG_FE_RST_GL); |
||
1205 | } |
||
1206 | |||
1207 | return 0; |
||
1208 | } |
||
1209 | |||
1210 | static int fe_open(struct net_device *dev) |
||
1211 | { |
||
1212 | struct fe_priv *priv = netdev_priv(dev); |
||
1213 | unsigned long flags; |
||
1214 | u32 val; |
||
1215 | int err; |
||
1216 | |||
1217 | err = fe_init_dma(priv); |
||
1218 | if (err) { |
||
1219 | fe_free_dma(priv); |
||
1220 | return err; |
||
1221 | } |
||
1222 | |||
1223 | spin_lock_irqsave(&priv->page_lock, flags); |
||
1224 | |||
1225 | val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN; |
||
1226 | if (priv->flags & FE_FLAG_RX_2B_OFFSET) |
||
1227 | val |= FE_RX_2B_OFFSET; |
||
1228 | val |= priv->soc->pdma_glo_cfg; |
||
1229 | fe_reg_w32(val, FE_REG_PDMA_GLO_CFG); |
||
1230 | |||
1231 | spin_unlock_irqrestore(&priv->page_lock, flags); |
||
1232 | |||
1233 | if (priv->phy) |
||
1234 | priv->phy->start(priv); |
||
1235 | |||
1236 | if (priv->soc->has_carrier && priv->soc->has_carrier(priv)) |
||
1237 | netif_carrier_on(dev); |
||
1238 | |||
1239 | napi_enable(&priv->rx_napi); |
||
1240 | fe_int_enable(priv->soc->tx_int | priv->soc->rx_int); |
||
1241 | netif_start_queue(dev); |
||
1242 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
1243 | mtk_ppe_probe(priv); |
||
1244 | #endif |
||
1245 | |||
1246 | return 0; |
||
1247 | } |
||
1248 | |||
1249 | static int fe_stop(struct net_device *dev) |
||
1250 | { |
||
1251 | struct fe_priv *priv = netdev_priv(dev); |
||
1252 | unsigned long flags; |
||
1253 | int i; |
||
1254 | |||
1255 | netif_tx_disable(dev); |
||
1256 | fe_int_disable(priv->soc->tx_int | priv->soc->rx_int); |
||
1257 | napi_disable(&priv->rx_napi); |
||
1258 | |||
1259 | if (priv->phy) |
||
1260 | priv->phy->stop(priv); |
||
1261 | |||
1262 | spin_lock_irqsave(&priv->page_lock, flags); |
||
1263 | |||
1264 | fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) & |
||
1265 | ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN), |
||
1266 | FE_REG_PDMA_GLO_CFG); |
||
1267 | spin_unlock_irqrestore(&priv->page_lock, flags); |
||
1268 | |||
1269 | /* wait dma stop */ |
||
1270 | for (i = 0; i < 10; i++) { |
||
1271 | if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) & |
||
1272 | (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) { |
||
1273 | msleep(20); |
||
1274 | continue; |
||
1275 | } |
||
1276 | break; |
||
1277 | } |
||
1278 | |||
1279 | fe_free_dma(priv); |
||
1280 | |||
1281 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
1282 | mtk_ppe_remove(priv); |
||
1283 | #endif |
||
1284 | |||
1285 | return 0; |
||
1286 | } |
||
1287 | |||
1288 | static int __init fe_init(struct net_device *dev) |
||
1289 | { |
||
1290 | struct fe_priv *priv = netdev_priv(dev); |
||
1291 | struct device_node *port; |
||
1292 | const char *mac_addr; |
||
1293 | int err; |
||
1294 | |||
1295 | priv->soc->reset_fe(); |
||
1296 | |||
1297 | if (priv->soc->switch_init) |
||
1298 | if (priv->soc->switch_init(priv)) { |
||
1299 | netdev_err(dev, "failed to initialize switch core\n"); |
||
1300 | return -ENODEV; |
||
1301 | } |
||
1302 | |||
1303 | mac_addr = of_get_mac_address(priv->dev->of_node); |
||
1304 | if (mac_addr) |
||
1305 | ether_addr_copy(dev->dev_addr, mac_addr); |
||
1306 | |||
1307 | /* If the mac address is invalid, use random mac address */ |
||
1308 | if (!is_valid_ether_addr(dev->dev_addr)) { |
||
1309 | random_ether_addr(dev->dev_addr); |
||
1310 | dev_err(priv->dev, "generated random MAC address %pM\n", |
||
1311 | dev->dev_addr); |
||
1312 | } |
||
1313 | |||
1314 | err = fe_mdio_init(priv); |
||
1315 | if (err) |
||
1316 | return err; |
||
1317 | |||
1318 | if (priv->soc->port_init) |
||
1319 | for_each_child_of_node(priv->dev->of_node, port) |
||
1320 | if (of_device_is_compatible(port, "mediatek,eth-port") && |
||
1321 | of_device_is_available(port)) |
||
1322 | priv->soc->port_init(priv, port); |
||
1323 | |||
1324 | if (priv->phy) { |
||
1325 | err = priv->phy->connect(priv); |
||
1326 | if (err) |
||
1327 | goto err_phy_disconnect; |
||
1328 | } |
||
1329 | |||
1330 | err = fe_hw_init(dev); |
||
1331 | if (err) |
||
1332 | goto err_phy_disconnect; |
||
1333 | |||
1334 | if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config) |
||
1335 | priv->soc->switch_config(priv); |
||
1336 | |||
1337 | return 0; |
||
1338 | |||
1339 | err_phy_disconnect: |
||
1340 | if (priv->phy) |
||
1341 | priv->phy->disconnect(priv); |
||
1342 | fe_mdio_cleanup(priv); |
||
1343 | |||
1344 | return err; |
||
1345 | } |
||
1346 | |||
1347 | static void fe_uninit(struct net_device *dev) |
||
1348 | { |
||
1349 | struct fe_priv *priv = netdev_priv(dev); |
||
1350 | |||
1351 | if (priv->phy) |
||
1352 | priv->phy->disconnect(priv); |
||
1353 | fe_mdio_cleanup(priv); |
||
1354 | |||
1355 | fe_reg_w32(0, FE_REG_FE_INT_ENABLE); |
||
1356 | free_irq(dev->irq, dev); |
||
1357 | } |
||
1358 | |||
1359 | static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
||
1360 | { |
||
1361 | struct fe_priv *priv = netdev_priv(dev); |
||
1362 | |||
1363 | if (!priv->phy_dev) |
||
1364 | return -ENODEV; |
||
1365 | |||
1366 | switch (cmd) { |
||
1367 | case SIOCETHTOOL: |
||
1368 | return phy_ethtool_ioctl(priv->phy_dev, |
||
1369 | (void *) ifr->ifr_data); |
||
1370 | case SIOCGMIIPHY: |
||
1371 | case SIOCGMIIREG: |
||
1372 | case SIOCSMIIREG: |
||
1373 | return phy_mii_ioctl(priv->phy_dev, ifr, cmd); |
||
1374 | default: |
||
1375 | break; |
||
1376 | } |
||
1377 | |||
1378 | return -EOPNOTSUPP; |
||
1379 | } |
||
1380 | |||
1381 | static int fe_change_mtu(struct net_device *dev, int new_mtu) |
||
1382 | { |
||
1383 | struct fe_priv *priv = netdev_priv(dev); |
||
1384 | int frag_size, old_mtu; |
||
1385 | u32 fwd_cfg; |
||
1386 | |||
1387 | if (!(priv->flags & FE_FLAG_JUMBO_FRAME)) |
||
1388 | return eth_change_mtu(dev, new_mtu); |
||
1389 | |||
1390 | if (IS_ENABLED(CONFIG_SOC_MT7621)) |
||
1391 | if (new_mtu > 2048) |
||
1392 | return -EINVAL; |
||
1393 | |||
1394 | frag_size = fe_max_frag_size(new_mtu); |
||
1395 | if (new_mtu < 68 || frag_size > PAGE_SIZE) |
||
1396 | return -EINVAL; |
||
1397 | |||
1398 | old_mtu = dev->mtu; |
||
1399 | dev->mtu = new_mtu; |
||
1400 | |||
1401 | /* return early if the buffer sizes will not change */ |
||
1402 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) |
||
1403 | return 0; |
||
1404 | if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN) |
||
1405 | return 0; |
||
1406 | |||
1407 | if (new_mtu <= ETH_DATA_LEN) |
||
1408 | priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN); |
||
1409 | else |
||
1410 | priv->rx_ring.frag_size = PAGE_SIZE; |
||
1411 | priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size); |
||
1412 | |||
1413 | if (!netif_running(dev)) |
||
1414 | return 0; |
||
1415 | |||
1416 | fe_stop(dev); |
||
1417 | if (!IS_ENABLED(CONFIG_SOC_MT7621)) { |
||
1418 | fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG); |
||
1419 | if (new_mtu <= ETH_DATA_LEN) { |
||
1420 | fwd_cfg &= ~FE_GDM1_JMB_EN; |
||
1421 | } else { |
||
1422 | fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT); |
||
1423 | fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) << |
||
1424 | FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN; |
||
1425 | } |
||
1426 | fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG); |
||
1427 | } |
||
1428 | |||
1429 | return fe_open(dev); |
||
1430 | } |
||
1431 | |||
1432 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
1433 | static int |
||
1434 | fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow, |
||
1435 | struct flow_offload_hw_path *src, |
||
1436 | struct flow_offload_hw_path *dest) |
||
1437 | { |
||
1438 | struct fe_priv *priv; |
||
1439 | |||
1440 | if (src->dev != dest->dev) |
||
1441 | return -EINVAL; |
||
1442 | |||
1443 | priv = netdev_priv(src->dev); |
||
1444 | |||
1445 | return mtk_flow_offload(priv, type, flow, src, dest); |
||
1446 | } |
||
1447 | #endif |
||
1448 | |||
1449 | static const struct net_device_ops fe_netdev_ops = { |
||
1450 | .ndo_init = fe_init, |
||
1451 | .ndo_uninit = fe_uninit, |
||
1452 | .ndo_open = fe_open, |
||
1453 | .ndo_stop = fe_stop, |
||
1454 | .ndo_start_xmit = fe_start_xmit, |
||
1455 | .ndo_set_mac_address = fe_set_mac_address, |
||
1456 | .ndo_validate_addr = eth_validate_addr, |
||
1457 | .ndo_do_ioctl = fe_do_ioctl, |
||
1458 | .ndo_change_mtu = fe_change_mtu, |
||
1459 | .ndo_tx_timeout = fe_tx_timeout, |
||
1460 | .ndo_get_stats64 = fe_get_stats64, |
||
1461 | .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid, |
||
1462 | .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid, |
||
1463 | #ifdef CONFIG_NET_POLL_CONTROLLER |
||
1464 | .ndo_poll_controller = fe_poll_controller, |
||
1465 | #endif |
||
1466 | #ifdef CONFIG_NET_MEDIATEK_OFFLOAD |
||
1467 | .ndo_flow_offload = fe_flow_offload, |
||
1468 | #endif |
||
1469 | }; |
||
1470 | |||
1471 | static void fe_reset_pending(struct fe_priv *priv) |
||
1472 | { |
||
1473 | struct net_device *dev = priv->netdev; |
||
1474 | int err; |
||
1475 | |||
1476 | rtnl_lock(); |
||
1477 | fe_stop(dev); |
||
1478 | |||
1479 | err = fe_open(dev); |
||
1480 | if (err) { |
||
1481 | netif_alert(priv, ifup, dev, |
||
1482 | "Driver up/down cycle failed, closing device.\n"); |
||
1483 | dev_close(dev); |
||
1484 | } |
||
1485 | rtnl_unlock(); |
||
1486 | } |
||
1487 | |||
1488 | static const struct fe_work_t fe_work[] = { |
||
1489 | {FE_FLAG_RESET_PENDING, fe_reset_pending}, |
||
1490 | }; |
||
1491 | |||
1492 | static void fe_pending_work(struct work_struct *work) |
||
1493 | { |
||
1494 | struct fe_priv *priv = container_of(work, struct fe_priv, pending_work); |
||
1495 | int i; |
||
1496 | bool pending; |
||
1497 | |||
1498 | for (i = 0; i < ARRAY_SIZE(fe_work); i++) { |
||
1499 | pending = test_and_clear_bit(fe_work[i].bitnr, |
||
1500 | priv->pending_flags); |
||
1501 | if (pending) |
||
1502 | fe_work[i].action(priv); |
||
1503 | } |
||
1504 | } |
||
1505 | |||
1506 | static int fe_probe(struct platform_device *pdev) |
||
1507 | { |
||
1508 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
1509 | const struct of_device_id *match; |
||
1510 | struct fe_soc_data *soc; |
||
1511 | struct net_device *netdev; |
||
1512 | struct fe_priv *priv; |
||
1513 | struct clk *sysclk; |
||
1514 | int err, napi_weight; |
||
1515 | |||
1516 | device_reset(&pdev->dev); |
||
1517 | |||
1518 | match = of_match_device(of_fe_match, &pdev->dev); |
||
1519 | soc = (struct fe_soc_data *)match->data; |
||
1520 | |||
1521 | if (soc->reg_table) |
||
1522 | fe_reg_table = soc->reg_table; |
||
1523 | else |
||
1524 | soc->reg_table = fe_reg_table; |
||
1525 | |||
1526 | fe_base = devm_ioremap_resource(&pdev->dev, res); |
||
1527 | if (IS_ERR(fe_base)) { |
||
1528 | err = -EADDRNOTAVAIL; |
||
1529 | goto err_out; |
||
1530 | } |
||
1531 | |||
1532 | netdev = alloc_etherdev(sizeof(*priv)); |
||
1533 | if (!netdev) { |
||
1534 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); |
||
1535 | err = -ENOMEM; |
||
1536 | goto err_iounmap; |
||
1537 | } |
||
1538 | |||
1539 | SET_NETDEV_DEV(netdev, &pdev->dev); |
||
1540 | netdev->netdev_ops = &fe_netdev_ops; |
||
1541 | netdev->base_addr = (unsigned long)fe_base; |
||
1542 | |||
1543 | netdev->irq = platform_get_irq(pdev, 0); |
||
1544 | if (netdev->irq < 0) { |
||
1545 | dev_err(&pdev->dev, "no IRQ resource found\n"); |
||
1546 | err = -ENXIO; |
||
1547 | goto err_free_dev; |
||
1548 | } |
||
1549 | |||
1550 | if (soc->init_data) |
||
1551 | soc->init_data(soc, netdev); |
||
1552 | netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX; |
||
1553 | netdev->features |= netdev->hw_features; |
||
1554 | |||
1555 | /* fake rx vlan filter func. to support tx vlan offload func */ |
||
1556 | if (fe_reg_table[FE_REG_FE_DMA_VID_BASE]) |
||
1557 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
||
1558 | |||
1559 | priv = netdev_priv(netdev); |
||
1560 | spin_lock_init(&priv->page_lock); |
||
1561 | if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) { |
||
1562 | priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL); |
||
1563 | if (!priv->hw_stats) { |
||
1564 | err = -ENOMEM; |
||
1565 | goto err_free_dev; |
||
1566 | } |
||
1567 | spin_lock_init(&priv->hw_stats->stats_lock); |
||
1568 | } |
||
1569 | |||
1570 | sysclk = devm_clk_get(&pdev->dev, NULL); |
||
1571 | if (!IS_ERR(sysclk)) { |
||
1572 | priv->sysclk = clk_get_rate(sysclk); |
||
1573 | } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) { |
||
1574 | dev_err(&pdev->dev, "this soc needs a clk for calibration\n"); |
||
1575 | err = -ENXIO; |
||
1576 | goto err_free_dev; |
||
1577 | } |
||
1578 | |||
1579 | priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0); |
||
1580 | if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) { |
||
1581 | dev_err(&pdev->dev, "failed to read switch phandle\n"); |
||
1582 | err = -ENODEV; |
||
1583 | goto err_free_dev; |
||
1584 | } |
||
1585 | |||
1586 | priv->netdev = netdev; |
||
1587 | priv->dev = &pdev->dev; |
||
1588 | priv->soc = soc; |
||
1589 | priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE); |
||
1590 | priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN); |
||
1591 | priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size); |
||
1592 | priv->tx_ring.tx_ring_size = NUM_DMA_DESC; |
||
1593 | priv->rx_ring.rx_ring_size = NUM_DMA_DESC; |
||
1594 | INIT_WORK(&priv->pending_work, fe_pending_work); |
||
1595 | u64_stats_init(&priv->hw_stats->syncp); |
||
1596 | |||
1597 | napi_weight = 16; |
||
1598 | if (priv->flags & FE_FLAG_NAPI_WEIGHT) { |
||
1599 | napi_weight *= 4; |
||
1600 | priv->tx_ring.tx_ring_size *= 4; |
||
1601 | priv->rx_ring.rx_ring_size *= 4; |
||
1602 | } |
||
1603 | netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight); |
||
1604 | fe_set_ethtool_ops(netdev); |
||
1605 | |||
1606 | err = register_netdev(netdev); |
||
1607 | if (err) { |
||
1608 | dev_err(&pdev->dev, "error bringing up device\n"); |
||
1609 | goto err_free_dev; |
||
1610 | } |
||
1611 | |||
1612 | platform_set_drvdata(pdev, netdev); |
||
1613 | |||
1614 | netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n", |
||
1615 | netdev->base_addr, netdev->irq); |
||
1616 | |||
1617 | return 0; |
||
1618 | |||
1619 | err_free_dev: |
||
1620 | free_netdev(netdev); |
||
1621 | err_iounmap: |
||
1622 | devm_iounmap(&pdev->dev, fe_base); |
||
1623 | err_out: |
||
1624 | return err; |
||
1625 | } |
||
1626 | |||
1627 | static int fe_remove(struct platform_device *pdev) |
||
1628 | { |
||
1629 | struct net_device *dev = platform_get_drvdata(pdev); |
||
1630 | struct fe_priv *priv = netdev_priv(dev); |
||
1631 | |||
1632 | netif_napi_del(&priv->rx_napi); |
||
1633 | kfree(priv->hw_stats); |
||
1634 | |||
1635 | cancel_work_sync(&priv->pending_work); |
||
1636 | |||
1637 | unregister_netdev(dev); |
||
1638 | free_netdev(dev); |
||
1639 | platform_set_drvdata(pdev, NULL); |
||
1640 | |||
1641 | return 0; |
||
1642 | } |
||
1643 | |||
1644 | static struct platform_driver fe_driver = { |
||
1645 | .probe = fe_probe, |
||
1646 | .remove = fe_remove, |
||
1647 | .driver = { |
||
1648 | .name = "mtk_soc_eth", |
||
1649 | .owner = THIS_MODULE, |
||
1650 | .of_match_table = of_fe_match, |
||
1651 | }, |
||
1652 | }; |
||
1653 | |||
1654 | module_platform_driver(fe_driver); |
||
1655 | |||
1656 | MODULE_LICENSE("GPL"); |
||
1657 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
||
1658 | MODULE_DESCRIPTION("Ethernet driver for Ralink SoC"); |
||
1659 | MODULE_VERSION(MTK_FE_DRV_VERSION); |