OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* |
2 | * This program is free software; you can redistribute it and/or |
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3 | * modify it under the terms of the GNU General Public License |
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4 | * as published by the Free Software Foundation; either version 2 |
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5 | * of the License, or (at your option) any later version. |
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6 | * |
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7 | * This program is distributed in the hope that it will be useful, |
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8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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10 | * GNU General Public License for more details. |
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11 | * |
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12 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
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13 | * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com> |
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14 | */ |
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15 | |||
16 | #ifndef _MT7530_H__ |
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17 | #define _MT7530_H__ |
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18 | |||
19 | #define MT7620_MIB_COUNTER_BASE_PORT 0x4000 |
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20 | #define MT7620_MIB_COUNTER_PORT_OFFSET 0x100 |
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21 | #define MT7620_MIB_COUNTER_BASE 0x1010 |
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22 | |||
23 | /* PPE Accounting Group #0 Byte Counter */ |
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24 | #define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000 |
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25 | |||
26 | /* PPE Accounting Group #0 Packet Counter */ |
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27 | #define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004 |
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28 | |||
29 | /* PPE Accounting Group #63 Byte Counter */ |
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30 | #define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8 |
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31 | |||
32 | /* PPE Accounting Group #63 Packet Counter */ |
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33 | #define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC |
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34 | |||
35 | /* PPE Meter Group #0 */ |
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36 | #define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200 |
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37 | |||
38 | /* PPE Meter Group #63 */ |
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39 | #define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC |
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40 | |||
41 | /* Transmit good byte count for CPU GDM */ |
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42 | #define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300 |
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43 | |||
44 | /* Transmit good packet count for CPU GDM (exclude flow control frames) */ |
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45 | #define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304 |
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46 | |||
47 | /* Transmit abort count for CPU GDM */ |
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48 | #define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308 |
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49 | |||
50 | /* Transmit collision count for CPU GDM */ |
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51 | #define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C |
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52 | |||
53 | /* Received good byte count for CPU GDM */ |
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54 | #define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320 |
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55 | |||
56 | /* Received good packet count for CPU GDM (exclude flow control frame) */ |
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57 | #define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324 |
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58 | |||
59 | /* Received overflow error packet count for CPU GDM */ |
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60 | #define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328 |
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61 | |||
62 | /* Received FCS error packet count for CPU GDM */ |
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63 | #define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C |
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64 | |||
65 | /* Received too short error packet count for CPU GDM */ |
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66 | #define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330 |
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67 | |||
68 | /* Received too long error packet count for CPU GDM */ |
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69 | #define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334 |
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70 | |||
71 | /* Received IP/TCP/UDP checksum error packet count for CPU GDM */ |
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72 | #define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338 |
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73 | |||
74 | /* Received flow control pkt count for CPU GDM */ |
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75 | #define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C |
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76 | |||
77 | /* Transmit good byte count for PPE GDM */ |
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78 | #define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340 |
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79 | |||
80 | /* Transmit good packet count for PPE GDM (exclude flow control frames) */ |
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81 | #define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344 |
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82 | |||
83 | /* Transmit abort count for PPE GDM */ |
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84 | #define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348 |
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85 | |||
86 | /* Transmit collision count for PPE GDM */ |
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87 | #define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C |
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88 | |||
89 | /* Received good byte count for PPE GDM */ |
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90 | #define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360 |
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91 | |||
92 | /* Received good packet count for PPE GDM (exclude flow control frame) */ |
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93 | #define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364 |
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94 | |||
95 | /* Received overflow error packet count for PPE GDM */ |
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96 | #define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368 |
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97 | |||
98 | /* Received FCS error packet count for PPE GDM */ |
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99 | #define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C |
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100 | |||
101 | /* Received too short error packet count for PPE GDM */ |
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102 | #define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370 |
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103 | |||
104 | /* Received too long error packet count for PPE GDM */ |
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105 | #define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374 |
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106 | |||
107 | /* Received IP/TCP/UDP checksum error packet count for PPE GDM */ |
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108 | #define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378 |
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109 | |||
110 | /* Received flow control pkt count for PPE GDM */ |
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111 | #define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C |
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112 | |||
113 | /* Tx Packet Counter of Port n */ |
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114 | #define MT7620_MIB_STATS_PORT_TGPCN 0x10 |
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115 | |||
116 | /* Tx Bad Octet Counter of Port n */ |
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117 | #define MT7620_MIB_STATS_PORT_TBOCN 0x14 |
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118 | |||
119 | /* Tx Good Octet Counter of Port n */ |
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120 | #define MT7620_MIB_STATS_PORT_TGOCN 0x18 |
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121 | |||
122 | /* Tx Event Packet Counter of Port n */ |
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123 | #define MT7620_MIB_STATS_PORT_TEPCN 0x1C |
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124 | |||
125 | /* Rx Packet Counter of Port n */ |
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126 | #define MT7620_MIB_STATS_PORT_RGPCN 0x20 |
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127 | |||
128 | /* Rx Bad Octet Counter of Port n */ |
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129 | #define MT7620_MIB_STATS_PORT_RBOCN 0x24 |
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130 | |||
131 | /* Rx Good Octet Counter of Port n */ |
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132 | #define MT7620_MIB_STATS_PORT_RGOCN 0x28 |
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133 | |||
134 | /* Rx Event Packet Counter of Port n */ |
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135 | #define MT7620_MIB_STATS_PORT_REPC1N 0x2C |
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136 | |||
137 | /* Rx Event Packet Counter of Port n */ |
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138 | #define MT7620_MIB_STATS_PORT_REPC2N 0x30 |
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139 | |||
140 | #define MT7621_MIB_COUNTER_BASE 0x4000 |
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141 | #define MT7621_MIB_COUNTER_PORT_OFFSET 0x100 |
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142 | #define MT7621_STATS_TDPC 0x00 |
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143 | #define MT7621_STATS_TCRC 0x04 |
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144 | #define MT7621_STATS_TUPC 0x08 |
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145 | #define MT7621_STATS_TMPC 0x0C |
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146 | #define MT7621_STATS_TBPC 0x10 |
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147 | #define MT7621_STATS_TCEC 0x14 |
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148 | #define MT7621_STATS_TSCEC 0x18 |
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149 | #define MT7621_STATS_TMCEC 0x1C |
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150 | #define MT7621_STATS_TDEC 0x20 |
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151 | #define MT7621_STATS_TLCEC 0x24 |
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152 | #define MT7621_STATS_TXCEC 0x28 |
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153 | #define MT7621_STATS_TPPC 0x2C |
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154 | #define MT7621_STATS_TL64PC 0x30 |
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155 | #define MT7621_STATS_TL65PC 0x34 |
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156 | #define MT7621_STATS_TL128PC 0x38 |
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157 | #define MT7621_STATS_TL256PC 0x3C |
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158 | #define MT7621_STATS_TL512PC 0x40 |
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159 | #define MT7621_STATS_TL1024PC 0x44 |
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160 | #define MT7621_STATS_TOC 0x48 |
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161 | #define MT7621_STATS_RDPC 0x60 |
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162 | #define MT7621_STATS_RFPC 0x64 |
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163 | #define MT7621_STATS_RUPC 0x68 |
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164 | #define MT7621_STATS_RMPC 0x6C |
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165 | #define MT7621_STATS_RBPC 0x70 |
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166 | #define MT7621_STATS_RAEPC 0x74 |
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167 | #define MT7621_STATS_RCEPC 0x78 |
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168 | #define MT7621_STATS_RUSPC 0x7C |
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169 | #define MT7621_STATS_RFEPC 0x80 |
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170 | #define MT7621_STATS_ROSPC 0x84 |
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171 | #define MT7621_STATS_RJEPC 0x88 |
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172 | #define MT7621_STATS_RPPC 0x8C |
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173 | #define MT7621_STATS_RL64PC 0x90 |
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174 | #define MT7621_STATS_RL65PC 0x94 |
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175 | #define MT7621_STATS_RL128PC 0x98 |
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176 | #define MT7621_STATS_RL256PC 0x9C |
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177 | #define MT7621_STATS_RL512PC 0xA0 |
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178 | #define MT7621_STATS_RL1024PC 0xA4 |
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179 | #define MT7621_STATS_ROC 0xA8 |
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180 | #define MT7621_STATS_RDPC_CTRL 0xB0 |
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181 | #define MT7621_STATS_RDPC_ING 0xB4 |
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182 | #define MT7621_STATS_RDPC_ARL 0xB8 |
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183 | |||
184 | int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan); |
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185 | |||
186 | #endif |