OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #include <linux/module.h> |
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16 | #include <linux/kernel.h> |
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17 | #include <linux/types.h> |
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18 | |||
19 | #include "mtk_eth_soc.h" |
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20 | #include "gsw_mt7620.h" |
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21 | #include "mdio.h" |
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22 | |||
23 | static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw) |
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24 | { |
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25 | unsigned long t_start = jiffies; |
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26 | |||
27 | while (1) { |
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28 | if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS)) |
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29 | return 0; |
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30 | if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) |
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31 | break; |
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32 | } |
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33 | |||
34 | dev_err(gsw->dev, "mdio: MDIO timeout\n"); |
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35 | return -1; |
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36 | } |
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37 | |||
38 | u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, |
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39 | u32 phy_register, u32 write_data) |
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40 | { |
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41 | if (mt7620_mii_busy_wait(gsw)) |
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42 | return -1; |
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43 | |||
44 | write_data &= 0xffff; |
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45 | |||
46 | mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE | |
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47 | (phy_register << GSW_MDIO_REG_SHIFT) | |
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48 | (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data, |
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49 | MT7620A_GSW_REG_PIAC); |
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50 | |||
51 | if (mt7620_mii_busy_wait(gsw)) |
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52 | return -1; |
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53 | |||
54 | return 0; |
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55 | } |
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56 | |||
57 | u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg) |
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58 | { |
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59 | u32 d; |
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60 | |||
61 | if (mt7620_mii_busy_wait(gsw)) |
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62 | return 0xffff; |
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63 | |||
64 | mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ | |
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65 | (phy_reg << GSW_MDIO_REG_SHIFT) | |
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66 | (phy_addr << GSW_MDIO_ADDR_SHIFT), |
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67 | MT7620A_GSW_REG_PIAC); |
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68 | |||
69 | if (mt7620_mii_busy_wait(gsw)) |
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70 | return 0xffff; |
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71 | |||
72 | d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff; |
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73 | |||
74 | return d; |
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75 | } |
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76 | |||
77 | int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) |
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78 | { |
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79 | struct fe_priv *priv = bus->priv; |
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80 | struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; |
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81 | |||
82 | return _mt7620_mii_write(gsw, phy_addr, phy_reg, val); |
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83 | } |
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84 | |||
85 | int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) |
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86 | { |
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87 | struct fe_priv *priv = bus->priv; |
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88 | struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; |
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89 | |||
90 | return _mt7620_mii_read(gsw, phy_addr, phy_reg); |
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91 | } |
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92 | |||
93 | void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val) |
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94 | { |
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95 | _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff); |
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96 | _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff); |
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97 | _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16); |
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98 | } |
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99 | |||
100 | u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg) |
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101 | { |
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102 | u16 high, low; |
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103 | |||
104 | _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff); |
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105 | low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf); |
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106 | high = _mt7620_mii_read(gsw, 0x1f, 0x10); |
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107 | |||
108 | return (high << 16) | (low & 0xffff); |
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109 | } |
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110 | |||
111 | static unsigned char *fe_speed_str(int speed) |
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112 | { |
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113 | switch (speed) { |
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114 | case 2: |
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115 | case SPEED_1000: |
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116 | return "1000"; |
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117 | case 1: |
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118 | case SPEED_100: |
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119 | return "100"; |
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120 | case 0: |
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121 | case SPEED_10: |
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122 | return "10"; |
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123 | } |
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124 | |||
125 | return "? "; |
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126 | } |
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127 | |||
128 | int mt7620_has_carrier(struct fe_priv *priv) |
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129 | { |
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130 | struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; |
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131 | int i; |
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132 | |||
133 | for (i = 0; i < GSW_PORT6; i++) |
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134 | if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1) |
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135 | return 1; |
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136 | return 0; |
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137 | } |
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138 | |||
139 | |||
140 | void mt7620_handle_carrier(struct fe_priv *priv) |
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141 | { |
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142 | if (!priv->phy) |
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143 | return; |
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144 | |||
145 | if (mt7620_has_carrier(priv)) |
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146 | netif_carrier_on(priv->netdev); |
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147 | else |
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148 | netif_carrier_off(priv->netdev); |
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149 | } |
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150 | |||
151 | void mt7620_print_link_state(struct fe_priv *priv, int port, int link, |
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152 | int speed, int duplex) |
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153 | { |
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154 | if (link) |
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155 | netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n", |
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156 | port, fe_speed_str(speed), |
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157 | (duplex) ? "Full" : "Half"); |
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158 | else |
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159 | netdev_info(priv->netdev, "port %d link down\n", port); |
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160 | } |
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161 | |||
162 | void mt7620_mdio_link_adjust(struct fe_priv *priv, int port) |
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163 | { |
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164 | mt7620_print_link_state(priv, port, priv->link[port], |
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165 | priv->phy->speed[port], |
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166 | (priv->phy->duplex[port] == DUPLEX_FULL)); |
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167 | mt7620_handle_carrier(priv); |
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168 | } |