OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #include <linux/module.h> |
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16 | #include <linux/kernel.h> |
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17 | #include <linux/types.h> |
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18 | #include <linux/platform_device.h> |
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19 | #include <linux/of_device.h> |
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20 | #include <linux/of_irq.h> |
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21 | |||
22 | #include <ralink_regs.h> |
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23 | |||
24 | #include "mtk_eth_soc.h" |
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25 | #include "gsw_mt7620.h" |
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26 | |||
27 | void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg) |
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28 | { |
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29 | iowrite32(val, gsw->base + reg); |
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30 | } |
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31 | |||
32 | u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg) |
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33 | { |
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34 | return ioread32(gsw->base + reg); |
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35 | } |
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36 | |||
37 | static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv) |
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38 | { |
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39 | struct fe_priv *priv = (struct fe_priv *)_priv; |
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40 | struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; |
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41 | u32 status; |
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42 | int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3); |
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43 | |||
44 | status = mtk_switch_r32(gsw, GSW_REG_ISR); |
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45 | if (status & PORT_IRQ_ST_CHG) |
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46 | for (i = 0; i <= max; i++) { |
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47 | u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)); |
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48 | int link = status & 0x1; |
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49 | |||
50 | if (link != priv->link[i]) |
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51 | mt7620_print_link_state(priv, i, link, |
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52 | (status >> 2) & 3, |
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53 | (status & 0x2)); |
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54 | |||
55 | priv->link[i] = link; |
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56 | } |
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57 | mt7620_handle_carrier(priv); |
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58 | mtk_switch_w32(gsw, status, GSW_REG_ISR); |
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59 | |||
60 | return IRQ_HANDLED; |
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61 | } |
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62 | |||
63 | static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np) |
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64 | { |
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65 | u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1; |
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66 | |||
67 | rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); |
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68 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); |
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69 | |||
70 | /* Enable MIB stats */ |
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71 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN); |
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72 | |||
73 | if (of_property_read_bool(np, "mediatek,mt7530")) { |
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74 | u32 val; |
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75 | |||
76 | /* turn off ephy and set phy base addr to 12 */ |
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77 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) | |
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78 | (0x1f << 24) | (0xc << 16), |
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79 | GSW_REG_GPC1); |
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80 | |||
81 | /* set MT7530 central align */ |
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82 | val = mt7530_mdio_r32(gsw, 0x7830); |
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83 | val &= ~BIT(0); |
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84 | val |= BIT(1); |
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85 | mt7530_mdio_w32(gsw, 0x7830, val); |
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86 | |||
87 | val = mt7530_mdio_r32(gsw, 0x7a40); |
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88 | val &= ~BIT(30); |
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89 | mt7530_mdio_w32(gsw, 0x7a40, val); |
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90 | |||
91 | mt7530_mdio_w32(gsw, 0x7a78, 0x855); |
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92 | } else { |
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93 | /* global page 4 */ |
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94 | _mt7620_mii_write(gsw, 1, 31, 0x4000); |
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95 | |||
96 | _mt7620_mii_write(gsw, 1, 17, 0x7444); |
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97 | if (is_BGA) |
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98 | _mt7620_mii_write(gsw, 1, 19, 0x0114); |
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99 | else |
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100 | _mt7620_mii_write(gsw, 1, 19, 0x0117); |
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101 | |||
102 | _mt7620_mii_write(gsw, 1, 22, 0x10cf); |
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103 | _mt7620_mii_write(gsw, 1, 25, 0x6212); |
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104 | _mt7620_mii_write(gsw, 1, 26, 0x0777); |
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105 | _mt7620_mii_write(gsw, 1, 29, 0x4000); |
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106 | _mt7620_mii_write(gsw, 1, 28, 0xc077); |
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107 | _mt7620_mii_write(gsw, 1, 24, 0x0000); |
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108 | |||
109 | /* global page 3 */ |
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110 | _mt7620_mii_write(gsw, 1, 31, 0x3000); |
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111 | _mt7620_mii_write(gsw, 1, 17, 0x4838); |
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112 | |||
113 | /* global page 2 */ |
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114 | _mt7620_mii_write(gsw, 1, 31, 0x2000); |
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115 | if (is_BGA) { |
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116 | _mt7620_mii_write(gsw, 1, 21, 0x0515); |
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117 | _mt7620_mii_write(gsw, 1, 22, 0x0053); |
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118 | _mt7620_mii_write(gsw, 1, 23, 0x00bf); |
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119 | _mt7620_mii_write(gsw, 1, 24, 0x0aaf); |
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120 | _mt7620_mii_write(gsw, 1, 25, 0x0fad); |
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121 | _mt7620_mii_write(gsw, 1, 26, 0x0fc1); |
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122 | } else { |
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123 | _mt7620_mii_write(gsw, 1, 21, 0x0517); |
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124 | _mt7620_mii_write(gsw, 1, 22, 0x0fd2); |
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125 | _mt7620_mii_write(gsw, 1, 23, 0x00bf); |
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126 | _mt7620_mii_write(gsw, 1, 24, 0x0aab); |
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127 | _mt7620_mii_write(gsw, 1, 25, 0x00ae); |
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128 | _mt7620_mii_write(gsw, 1, 26, 0x0fff); |
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129 | } |
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130 | /* global page 1 */ |
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131 | _mt7620_mii_write(gsw, 1, 31, 0x1000); |
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132 | _mt7620_mii_write(gsw, 1, 17, 0xe7f8); |
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133 | } |
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134 | |||
135 | /* global page 0 */ |
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136 | _mt7620_mii_write(gsw, 1, 31, 0x8000); |
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137 | _mt7620_mii_write(gsw, 0, 30, 0xa000); |
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138 | _mt7620_mii_write(gsw, 1, 30, 0xa000); |
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139 | _mt7620_mii_write(gsw, 2, 30, 0xa000); |
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140 | _mt7620_mii_write(gsw, 3, 30, 0xa000); |
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141 | |||
142 | _mt7620_mii_write(gsw, 0, 4, 0x05e1); |
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143 | _mt7620_mii_write(gsw, 1, 4, 0x05e1); |
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144 | _mt7620_mii_write(gsw, 2, 4, 0x05e1); |
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145 | _mt7620_mii_write(gsw, 3, 4, 0x05e1); |
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146 | |||
147 | /* global page 2 */ |
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148 | _mt7620_mii_write(gsw, 1, 31, 0xa000); |
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149 | _mt7620_mii_write(gsw, 0, 16, 0x1111); |
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150 | _mt7620_mii_write(gsw, 1, 16, 0x1010); |
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151 | _mt7620_mii_write(gsw, 2, 16, 0x1515); |
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152 | _mt7620_mii_write(gsw, 3, 16, 0x0f0f); |
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153 | |||
154 | /* CPU Port6 Force Link 1G, FC ON */ |
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155 | mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6)); |
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156 | |||
157 | /* Set Port 6 as CPU Port */ |
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158 | mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010); |
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159 | |||
160 | /* setup port 4 */ |
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161 | if (gsw->port4 == PORT4_EPHY) { |
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162 | u32 val = rt_sysc_r32(SYSC_REG_CFG1); |
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163 | |||
164 | val |= 3 << 14; |
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165 | rt_sysc_w32(val, SYSC_REG_CFG1); |
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166 | _mt7620_mii_write(gsw, 4, 30, 0xa000); |
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167 | _mt7620_mii_write(gsw, 4, 4, 0x05e1); |
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168 | _mt7620_mii_write(gsw, 4, 16, 0x1313); |
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169 | _mt7620_mii_write(gsw, 4, 0, 0x3100); |
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170 | pr_info("gsw: setting port4 to ephy mode\n"); |
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171 | } |
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172 | } |
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173 | |||
174 | static const struct of_device_id mediatek_gsw_match[] = { |
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175 | { .compatible = "mediatek,mt7620-gsw" }, |
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176 | {}, |
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177 | }; |
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178 | MODULE_DEVICE_TABLE(of, mediatek_gsw_match); |
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179 | |||
180 | int mtk_gsw_init(struct fe_priv *priv) |
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181 | { |
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182 | struct device_node *np = priv->switch_np; |
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183 | struct platform_device *pdev = of_find_device_by_node(np); |
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184 | struct mt7620_gsw *gsw; |
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185 | |||
186 | if (!pdev) |
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187 | return -ENODEV; |
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188 | |||
189 | if (!of_device_is_compatible(np, mediatek_gsw_match->compatible)) |
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190 | return -EINVAL; |
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191 | |||
192 | gsw = platform_get_drvdata(pdev); |
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193 | priv->soc->swpriv = gsw; |
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194 | |||
195 | mt7620_hw_init(gsw, np); |
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196 | |||
197 | if (gsw->irq) { |
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198 | request_irq(gsw->irq, gsw_interrupt_mt7620, 0, |
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199 | "gsw", priv); |
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200 | mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR); |
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201 | } |
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202 | |||
203 | return 0; |
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204 | } |
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205 | |||
206 | static int mt7620_gsw_probe(struct platform_device *pdev) |
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207 | { |
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208 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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209 | const char *port4 = NULL; |
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210 | struct mt7620_gsw *gsw; |
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211 | struct device_node *np = pdev->dev.of_node; |
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212 | |||
213 | gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL); |
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214 | if (!gsw) |
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215 | return -ENOMEM; |
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216 | |||
217 | gsw->base = devm_ioremap_resource(&pdev->dev, res); |
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218 | if (IS_ERR(gsw->base)) |
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219 | return PTR_ERR(gsw->base); |
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220 | |||
221 | gsw->dev = &pdev->dev; |
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222 | |||
223 | of_property_read_string(np, "mediatek,port4", &port4); |
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224 | if (port4 && !strcmp(port4, "ephy")) |
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225 | gsw->port4 = PORT4_EPHY; |
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226 | else if (port4 && !strcmp(port4, "gmac")) |
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227 | gsw->port4 = PORT4_EXT; |
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228 | else |
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229 | gsw->port4 = PORT4_EPHY; |
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230 | |||
231 | gsw->irq = platform_get_irq(pdev, 0); |
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232 | |||
233 | platform_set_drvdata(pdev, gsw); |
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234 | |||
235 | return 0; |
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236 | } |
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237 | |||
238 | static int mt7620_gsw_remove(struct platform_device *pdev) |
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239 | { |
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240 | platform_set_drvdata(pdev, NULL); |
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241 | |||
242 | return 0; |
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243 | } |
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244 | |||
245 | static struct platform_driver gsw_driver = { |
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246 | .probe = mt7620_gsw_probe, |
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247 | .remove = mt7620_gsw_remove, |
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248 | .driver = { |
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249 | .name = "mt7620-gsw", |
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250 | .owner = THIS_MODULE, |
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251 | .of_match_table = mediatek_gsw_match, |
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252 | }, |
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253 | }; |
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254 | |||
255 | module_platform_driver(gsw_driver); |
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256 | |||
257 | MODULE_LICENSE("GPL"); |
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258 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
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259 | MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC"); |
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260 | MODULE_VERSION(MTK_FE_DRV_VERSION); |