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4 office 1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 */
10 /* MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35  
36 #ifndef MT6575_SD_H
37 #define MT6575_SD_H
38  
39 #include <linux/bitops.h>
40 #include <linux/interrupt.h>
41 #include <linux/mmc/host.h>
42  
43 // #include <mach/mt6575_reg_base.h> /* --- by chhung */
44  
45 /*--------------------------------------------------------------------------*/
46 /* Common Macro */
47 /*--------------------------------------------------------------------------*/
48 #define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
49  
50 /*--------------------------------------------------------------------------*/
51 /* Common Definition */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_FIFO_SZ (128)
54 #define MSDC_FIFO_THD (64) // (128)
55 #define MSDC_NUM (4)
56  
57 #define MSDC_MS (0)
58 #define MSDC_SDMMC (1)
59  
60 #define MSDC_MODE_UNKNOWN (0)
61 #define MSDC_MODE_PIO (1)
62 #define MSDC_MODE_DMA_BASIC (2)
63 #define MSDC_MODE_DMA_DESC (3)
64 #define MSDC_MODE_DMA_ENHANCED (4)
65 #define MSDC_MODE_MMC_STREAM (5)
66  
67 #define MSDC_BUS_1BITS (0)
68 #define MSDC_BUS_4BITS (1)
69 #define MSDC_BUS_8BITS (2)
70  
71 #define MSDC_BRUST_8B (3)
72 #define MSDC_BRUST_16B (4)
73 #define MSDC_BRUST_32B (5)
74 #define MSDC_BRUST_64B (6)
75  
76 #define MSDC_PIN_PULL_NONE (0)
77 #define MSDC_PIN_PULL_DOWN (1)
78 #define MSDC_PIN_PULL_UP (2)
79 #define MSDC_PIN_KEEP (3)
80  
81 #define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
82 #define MSDC_MIN_SCLK (260000)
83  
84 #define MSDC_AUTOCMD12 (0x0001)
85 #define MSDC_AUTOCMD23 (0x0002)
86 #define MSDC_AUTOCMD19 (0x0003)
87  
88 #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
89 #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
90  
91 enum {
92 RESP_NONE = 0,
93 RESP_R1,
94 RESP_R2,
95 RESP_R3,
96 RESP_R4,
97 RESP_R5,
98 RESP_R6,
99 RESP_R7,
100 RESP_R1B
101 };
102  
103 /*--------------------------------------------------------------------------*/
104 /* Register Offset */
105 /*--------------------------------------------------------------------------*/
106 #define OFFSET_MSDC_CFG (0x0)
107 #define OFFSET_MSDC_IOCON (0x04)
108 #define OFFSET_MSDC_PS (0x08)
109 #define OFFSET_MSDC_INT (0x0c)
110 #define OFFSET_MSDC_INTEN (0x10)
111 #define OFFSET_MSDC_FIFOCS (0x14)
112 #define OFFSET_MSDC_TXDATA (0x18)
113 #define OFFSET_MSDC_RXDATA (0x1c)
114 #define OFFSET_SDC_CFG (0x30)
115 #define OFFSET_SDC_CMD (0x34)
116 #define OFFSET_SDC_ARG (0x38)
117 #define OFFSET_SDC_STS (0x3c)
118 #define OFFSET_SDC_RESP0 (0x40)
119 #define OFFSET_SDC_RESP1 (0x44)
120 #define OFFSET_SDC_RESP2 (0x48)
121 #define OFFSET_SDC_RESP3 (0x4c)
122 #define OFFSET_SDC_BLK_NUM (0x50)
123 #define OFFSET_SDC_CSTS (0x58)
124 #define OFFSET_SDC_CSTS_EN (0x5c)
125 #define OFFSET_SDC_DCRC_STS (0x60)
126 #define OFFSET_EMMC_CFG0 (0x70)
127 #define OFFSET_EMMC_CFG1 (0x74)
128 #define OFFSET_EMMC_STS (0x78)
129 #define OFFSET_EMMC_IOCON (0x7c)
130 #define OFFSET_SDC_ACMD_RESP (0x80)
131 #define OFFSET_SDC_ACMD19_TRG (0x84)
132 #define OFFSET_SDC_ACMD19_STS (0x88)
133 #define OFFSET_MSDC_DMA_SA (0x90)
134 #define OFFSET_MSDC_DMA_CA (0x94)
135 #define OFFSET_MSDC_DMA_CTRL (0x98)
136 #define OFFSET_MSDC_DMA_CFG (0x9c)
137 #define OFFSET_MSDC_DBG_SEL (0xa0)
138 #define OFFSET_MSDC_DBG_OUT (0xa4)
139 #define OFFSET_MSDC_PATCH_BIT (0xb0)
140 #define OFFSET_MSDC_PATCH_BIT1 (0xb4)
141 #define OFFSET_MSDC_PAD_CTL0 (0xe0)
142 #define OFFSET_MSDC_PAD_CTL1 (0xe4)
143 #define OFFSET_MSDC_PAD_CTL2 (0xe8)
144 #define OFFSET_MSDC_PAD_TUNE (0xec)
145 #define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
146 #define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
147 #define OFFSET_MSDC_HW_DBG (0xf8)
148 #define OFFSET_MSDC_VERSION (0x100)
149 #define OFFSET_MSDC_ECO_VER (0x104)
150  
151 /*--------------------------------------------------------------------------*/
152 /* Register Address */
153 /*--------------------------------------------------------------------------*/
154  
155 /* common register */
156 #define MSDC_CFG REG_ADDR(MSDC_CFG)
157 #define MSDC_IOCON REG_ADDR(MSDC_IOCON)
158 #define MSDC_PS REG_ADDR(MSDC_PS)
159 #define MSDC_INT REG_ADDR(MSDC_INT)
160 #define MSDC_INTEN REG_ADDR(MSDC_INTEN)
161 #define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
162 #define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
163 #define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
164 #define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
165  
166 /* sdmmc register */
167 #define SDC_CFG REG_ADDR(SDC_CFG)
168 #define SDC_CMD REG_ADDR(SDC_CMD)
169 #define SDC_ARG REG_ADDR(SDC_ARG)
170 #define SDC_STS REG_ADDR(SDC_STS)
171 #define SDC_RESP0 REG_ADDR(SDC_RESP0)
172 #define SDC_RESP1 REG_ADDR(SDC_RESP1)
173 #define SDC_RESP2 REG_ADDR(SDC_RESP2)
174 #define SDC_RESP3 REG_ADDR(SDC_RESP3)
175 #define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
176 #define SDC_CSTS REG_ADDR(SDC_CSTS)
177 #define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
178 #define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
179  
180 /* emmc register*/
181 #define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
182 #define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
183 #define EMMC_STS REG_ADDR(EMMC_STS)
184 #define EMMC_IOCON REG_ADDR(EMMC_IOCON)
185  
186 /* auto command register */
187 #define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
188 #define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
189 #define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
190  
191 /* dma register */
192 #define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
193 #define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
194 #define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
195 #define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
196  
197 /* pad ctrl register */
198 #define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
199 #define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
200 #define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
201  
202 /* data read delay */
203 #define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
204 #define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
205  
206 /* debug register */
207 #define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
208 #define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
209  
210 /* misc register */
211 #define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
212 #define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
213 #define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
214 #define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
215 #define MSDC_VERSION REG_ADDR(MSDC_VERSION)
216 #define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
217  
218 /*--------------------------------------------------------------------------*/
219 /* Register Mask */
220 /*--------------------------------------------------------------------------*/
221  
222 /* MSDC_CFG mask */
223 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
224 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
225 #define MSDC_CFG_RST (0x1 << 2) /* RW */
226 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
227 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
228 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
229 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
230 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
231 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
232 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
233  
234 /* MSDC_IOCON mask */
235 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
236 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
237 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
238 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
239 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
240 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
241 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
242 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
243 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
244 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
245 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
246 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
247 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
248 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
249 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
250  
251 /* MSDC_PS mask */
252 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
253 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
254 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
255 #define MSDC_PS_DAT (0xff << 16) /* R */
256 #define MSDC_PS_CMD (0x1 << 24) /* R */
257 #define MSDC_PS_WP (0x1UL<< 31) /* R */
258  
259 /* MSDC_INT mask */
260 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
261 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
262 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
263 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
264 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
265 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
266 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
267 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
268 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
269 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
270 #define MSDC_INT_CSTA (0x1 << 11) /* R */
271 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
272 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
273 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
274 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
275 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
276  
277 /* MSDC_INTEN mask */
278 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
279 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
280 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
281 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
282 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
283 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
284 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
285 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
286 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
287 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
288 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
289 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
290 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
291 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
292 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
293 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
294  
295 /* MSDC_FIFOCS mask */
296 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
297 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
298 #define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
299  
300 /* SDC_CFG mask */
301 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
302 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
303 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
304 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
305 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
306 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
307 #define SDC_CFG_DTOC (0xffUL << 24) /* RW */
308  
309 /* SDC_CMD mask */
310 #define SDC_CMD_OPC (0x3f << 0) /* RW */
311 #define SDC_CMD_BRK (0x1 << 6) /* RW */
312 #define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
313 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
314 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
315 #define SDC_CMD_RW (0x1 << 13) /* RW */
316 #define SDC_CMD_STOP (0x1 << 14) /* RW */
317 #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
318 #define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
319 #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
320 #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
321  
322 /* SDC_STS mask */
323 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
324 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
325 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
326  
327 /* SDC_DCRC_STS mask */
328 #define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
329 #define SDC_DCRC_STS_POS (0xff << 0) /* RO */
330  
331 /* EMMC_CFG0 mask */
332 #define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
333 #define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
334 #define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
335 #define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
336 #define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
337 #define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
338  
339 /* EMMC_CFG1 mask */
340 #define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
341 #define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
342  
343 /* EMMC_STS mask */
344 #define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
345 #define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
346 #define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
347 #define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
348 #define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
349 #define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
350 #define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
351  
352 /* EMMC_IOCON mask */
353 #define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
354  
355 /* SDC_ACMD19_TRG mask */
356 #define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
357  
358 /* MSDC_DMA_CTRL mask */
359 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
360 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
361 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
362 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
363 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
364 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
365 #define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
366  
367 /* MSDC_DMA_CFG mask */
368 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
369 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
370 #define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
371 #define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
372  
373 /* MSDC_PATCH_BIT mask */
374 #define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
375 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
376 #define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
377 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
378 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
379 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
380 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
381 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
382 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
383 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
384 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
385 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
386  
387 /* MSDC_PATCH_BIT1 mask */
388 #define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
389 #define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
390  
391 /* MSDC_PAD_CTL0 mask */
392 #define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
393 #define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
394 #define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
395 #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
396 #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
397 #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
398 #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
399 #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
400 #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
401  
402 /* MSDC_PAD_CTL1 mask */
403 #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
404 #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
405 #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
406 #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
407 #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
408 #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
409 #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
410 #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
411 #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
412  
413 /* MSDC_PAD_CTL2 mask */
414 #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
415 #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
416 #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
417 #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
418 #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
419 #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
420 #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
421 #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
422 #define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
423  
424 /* MSDC_PAD_TUNE mask */
425 #define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
426 #define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
427 #define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
428 #define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
429 #define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
430  
431 /* MSDC_DAT_RDDLY0/1 mask */
432 #define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
433 #define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
434 #define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
435 #define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
436  
437 #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
438 #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
439 #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
440 #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
441  
442 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
443 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
444 #define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
445 #define CARD_READY_FOR_DATA (1<<8)
446 #define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
447  
448 /*--------------------------------------------------------------------------*/
449 /* Descriptor Structure */
450 /*--------------------------------------------------------------------------*/
451 typedef struct {
452 u32 hwo:1; /* could be changed by hw */
453 u32 bdp:1;
454 u32 rsv0:6;
455 u32 chksum:8;
456 u32 intr:1;
457 u32 rsv1:15;
458 void *next;
459 void *ptr;
460 u32 buflen:16;
461 u32 extlen:8;
462 u32 rsv2:8;
463 u32 arg;
464 u32 blknum;
465 u32 cmd;
466 } gpd_t;
467  
468 typedef struct {
469 u32 eol:1;
470 u32 rsv0:7;
471 u32 chksum:8;
472 u32 rsv1:1;
473 u32 blkpad:1;
474 u32 dwpad:1;
475 u32 rsv2:13;
476 void *next;
477 void *ptr;
478 u32 buflen:16;
479 u32 rsv3:16;
480 } bd_t;
481  
482 /*--------------------------------------------------------------------------*/
483 /* Register Debugging Structure */
484 /*--------------------------------------------------------------------------*/
485  
486 typedef struct {
487 u32 msdc:1;
488 u32 ckpwn:1;
489 u32 rst:1;
490 u32 pio:1;
491 u32 ckdrven:1;
492 u32 start18v:1;
493 u32 pass18v:1;
494 u32 ckstb:1;
495 u32 ckdiv:8;
496 u32 ckmod:2;
497 u32 pad:14;
498 } msdc_cfg_reg;
499 typedef struct {
500 u32 sdr104cksel:1;
501 u32 rsmpl:1;
502 u32 dsmpl:1;
503 u32 ddlysel:1;
504 u32 ddr50ckd:1;
505 u32 dsplsel:1;
506 u32 pad1:10;
507 u32 d0spl:1;
508 u32 d1spl:1;
509 u32 d2spl:1;
510 u32 d3spl:1;
511 u32 d4spl:1;
512 u32 d5spl:1;
513 u32 d6spl:1;
514 u32 d7spl:1;
515 u32 riscsz:1;
516 u32 pad2:7;
517 } msdc_iocon_reg;
518 typedef struct {
519 u32 cden:1;
520 u32 cdsts:1;
521 u32 pad1:10;
522 u32 cddebounce:4;
523 u32 dat:8;
524 u32 cmd:1;
525 u32 pad2:6;
526 u32 wp:1;
527 } msdc_ps_reg;
528 typedef struct {
529 u32 mmcirq:1;
530 u32 cdsc:1;
531 u32 pad1:1;
532 u32 atocmdrdy:1;
533 u32 atocmdtmo:1;
534 u32 atocmdcrc:1;
535 u32 dmaqempty:1;
536 u32 sdioirq:1;
537 u32 cmdrdy:1;
538 u32 cmdtmo:1;
539 u32 rspcrc:1;
540 u32 csta:1;
541 u32 xfercomp:1;
542 u32 dxferdone:1;
543 u32 dattmo:1;
544 u32 datcrc:1;
545 u32 atocmd19done:1;
546 u32 pad2:15;
547 } msdc_int_reg;
548 typedef struct {
549 u32 mmcirq:1;
550 u32 cdsc:1;
551 u32 pad1:1;
552 u32 atocmdrdy:1;
553 u32 atocmdtmo:1;
554 u32 atocmdcrc:1;
555 u32 dmaqempty:1;
556 u32 sdioirq:1;
557 u32 cmdrdy:1;
558 u32 cmdtmo:1;
559 u32 rspcrc:1;
560 u32 csta:1;
561 u32 xfercomp:1;
562 u32 dxferdone:1;
563 u32 dattmo:1;
564 u32 datcrc:1;
565 u32 atocmd19done:1;
566 u32 pad2:15;
567 } msdc_inten_reg;
568 typedef struct {
569 u32 rxcnt:8;
570 u32 pad1:8;
571 u32 txcnt:8;
572 u32 pad2:7;
573 u32 clr:1;
574 } msdc_fifocs_reg;
575 typedef struct {
576 u32 val;
577 } msdc_txdat_reg;
578 typedef struct {
579 u32 val;
580 } msdc_rxdat_reg;
581 typedef struct {
582 u32 sdiowkup:1;
583 u32 inswkup:1;
584 u32 pad1:14;
585 u32 buswidth:2;
586 u32 pad2:1;
587 u32 sdio:1;
588 u32 sdioide:1;
589 u32 intblkgap:1;
590 u32 pad4:2;
591 u32 dtoc:8;
592 } sdc_cfg_reg;
593 typedef struct {
594 u32 cmd:6;
595 u32 brk:1;
596 u32 rsptyp:3;
597 u32 pad1:1;
598 u32 dtype:2;
599 u32 rw:1;
600 u32 stop:1;
601 u32 goirq:1;
602 u32 blklen:12;
603 u32 atocmd:2;
604 u32 volswth:1;
605 u32 pad2:1;
606 } sdc_cmd_reg;
607 typedef struct {
608 u32 arg;
609 } sdc_arg_reg;
610 typedef struct {
611 u32 sdcbusy:1;
612 u32 cmdbusy:1;
613 u32 pad:29;
614 u32 swrcmpl:1;
615 } sdc_sts_reg;
616 typedef struct {
617 u32 val;
618 } sdc_resp0_reg;
619 typedef struct {
620 u32 val;
621 } sdc_resp1_reg;
622 typedef struct {
623 u32 val;
624 } sdc_resp2_reg;
625 typedef struct {
626 u32 val;
627 } sdc_resp3_reg;
628 typedef struct {
629 u32 num;
630 } sdc_blknum_reg;
631 typedef struct {
632 u32 sts;
633 } sdc_csts_reg;
634 typedef struct {
635 u32 sts;
636 } sdc_cstsen_reg;
637 typedef struct {
638 u32 datcrcsts:8;
639 u32 ddrcrcsts:4;
640 u32 pad:20;
641 } sdc_datcrcsts_reg;
642 typedef struct {
643 u32 bootstart:1;
644 u32 bootstop:1;
645 u32 bootmode:1;
646 u32 pad1:9;
647 u32 bootwaidly:3;
648 u32 bootsupp:1;
649 u32 pad2:16;
650 } emmc_cfg0_reg;
651 typedef struct {
652 u32 bootcrctmc:16;
653 u32 pad:4;
654 u32 bootacktmc:12;
655 } emmc_cfg1_reg;
656 typedef struct {
657 u32 bootcrcerr:1;
658 u32 bootackerr:1;
659 u32 bootdattmo:1;
660 u32 bootacktmo:1;
661 u32 bootupstate:1;
662 u32 bootackrcv:1;
663 u32 bootdatrcv:1;
664 u32 pad:25;
665 } emmc_sts_reg;
666 typedef struct {
667 u32 bootrst:1;
668 u32 pad:31;
669 } emmc_iocon_reg;
670 typedef struct {
671 u32 val;
672 } msdc_acmd_resp_reg;
673 typedef struct {
674 u32 tunesel:4;
675 u32 pad:28;
676 } msdc_acmd19_trg_reg;
677 typedef struct {
678 u32 val;
679 } msdc_acmd19_sts_reg;
680 typedef struct {
681 u32 addr;
682 } msdc_dma_sa_reg;
683 typedef struct {
684 u32 addr;
685 } msdc_dma_ca_reg;
686 typedef struct {
687 u32 start:1;
688 u32 stop:1;
689 u32 resume:1;
690 u32 pad1:5;
691 u32 mode:1;
692 u32 pad2:1;
693 u32 lastbuf:1;
694 u32 pad3:1;
695 u32 brustsz:3;
696 u32 pad4:1;
697 u32 xfersz:16;
698 } msdc_dma_ctrl_reg;
699 typedef struct {
700 u32 status:1;
701 u32 decsen:1;
702 u32 pad1:2;
703 u32 bdcsen:1;
704 u32 gpdcsen:1;
705 u32 pad2:26;
706 } msdc_dma_cfg_reg;
707 typedef struct {
708 u32 sel:16;
709 u32 pad2:16;
710 } msdc_dbg_sel_reg;
711 typedef struct {
712 u32 val;
713 } msdc_dbg_out_reg;
714 typedef struct {
715 u32 clkdrvn:3;
716 u32 rsv0:1;
717 u32 clkdrvp:3;
718 u32 rsv1:1;
719 u32 clksr:1;
720 u32 rsv2:7;
721 u32 clkpd:1;
722 u32 clkpu:1;
723 u32 clksmt:1;
724 u32 clkies:1;
725 u32 clktdsel:4;
726 u32 clkrdsel:8;
727 } msdc_pad_ctl0_reg;
728 typedef struct {
729 u32 cmddrvn:3;
730 u32 rsv0:1;
731 u32 cmddrvp:3;
732 u32 rsv1:1;
733 u32 cmdsr:1;
734 u32 rsv2:7;
735 u32 cmdpd:1;
736 u32 cmdpu:1;
737 u32 cmdsmt:1;
738 u32 cmdies:1;
739 u32 cmdtdsel:4;
740 u32 cmdrdsel:8;
741 } msdc_pad_ctl1_reg;
742 typedef struct {
743 u32 datdrvn:3;
744 u32 rsv0:1;
745 u32 datdrvp:3;
746 u32 rsv1:1;
747 u32 datsr:1;
748 u32 rsv2:7;
749 u32 datpd:1;
750 u32 datpu:1;
751 u32 datsmt:1;
752 u32 daties:1;
753 u32 dattdsel:4;
754 u32 datrdsel:8;
755 } msdc_pad_ctl2_reg;
756 typedef struct {
757 u32 wrrxdly:3;
758 u32 pad1:5;
759 u32 rdrxdly:8;
760 u32 pad2:16;
761 } msdc_pad_tune_reg;
762 typedef struct {
763 u32 dat0:5;
764 u32 rsv0:3;
765 u32 dat1:5;
766 u32 rsv1:3;
767 u32 dat2:5;
768 u32 rsv2:3;
769 u32 dat3:5;
770 u32 rsv3:3;
771 } msdc_dat_rddly0;
772 typedef struct {
773 u32 dat4:5;
774 u32 rsv4:3;
775 u32 dat5:5;
776 u32 rsv5:3;
777 u32 dat6:5;
778 u32 rsv6:3;
779 u32 dat7:5;
780 u32 rsv7:3;
781 } msdc_dat_rddly1;
782 typedef struct {
783 u32 dbg0sel:8;
784 u32 dbg1sel:6;
785 u32 pad1:2;
786 u32 dbg2sel:6;
787 u32 pad2:2;
788 u32 dbg3sel:6;
789 u32 pad3:2;
790 } msdc_hw_dbg_reg;
791 typedef struct {
792 u32 val;
793 } msdc_version_reg;
794 typedef struct {
795 u32 val;
796 } msdc_eco_ver_reg;
797  
798 struct msdc_regs {
799 msdc_cfg_reg msdc_cfg; /* base+0x00h */
800 msdc_iocon_reg msdc_iocon; /* base+0x04h */
801 msdc_ps_reg msdc_ps; /* base+0x08h */
802 msdc_int_reg msdc_int; /* base+0x0ch */
803 msdc_inten_reg msdc_inten; /* base+0x10h */
804 msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
805 msdc_txdat_reg msdc_txdat; /* base+0x18h */
806 msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
807 u32 rsv1[4];
808 sdc_cfg_reg sdc_cfg; /* base+0x30h */
809 sdc_cmd_reg sdc_cmd; /* base+0x34h */
810 sdc_arg_reg sdc_arg; /* base+0x38h */
811 sdc_sts_reg sdc_sts; /* base+0x3ch */
812 sdc_resp0_reg sdc_resp0; /* base+0x40h */
813 sdc_resp1_reg sdc_resp1; /* base+0x44h */
814 sdc_resp2_reg sdc_resp2; /* base+0x48h */
815 sdc_resp3_reg sdc_resp3; /* base+0x4ch */
816 sdc_blknum_reg sdc_blknum; /* base+0x50h */
817 u32 rsv2[1];
818 sdc_csts_reg sdc_csts; /* base+0x58h */
819 sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
820 sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
821 u32 rsv3[3];
822 emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
823 emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
824 emmc_sts_reg emmc_sts; /* base+0x78h */
825 emmc_iocon_reg emmc_iocon; /* base+0x7ch */
826 msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
827 msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
828 msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
829 u32 rsv4[1];
830 msdc_dma_sa_reg dma_sa; /* base+0x90h */
831 msdc_dma_ca_reg dma_ca; /* base+0x94h */
832 msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
833 msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
834 msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
835 msdc_dbg_out_reg dbg_out; /* base+0xa4h */
836 u32 rsv5[2];
837 u32 patch0; /* base+0xb0h */
838 u32 patch1; /* base+0xb4h */
839 u32 rsv6[10];
840 msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
841 msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
842 msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
843 msdc_pad_tune_reg pad_tune; /* base+0xech */
844 msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
845 msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
846 msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
847 u32 rsv7[1];
848 msdc_version_reg version; /* base+0x100h */
849 msdc_eco_ver_reg eco_ver; /* base+0x104h */
850 };
851  
852 struct scatterlist_ex {
853 u32 cmd;
854 u32 arg;
855 u32 sglen;
856 struct scatterlist *sg;
857 };
858  
859 #define DMA_FLAG_NONE (0x00000000)
860 #define DMA_FLAG_EN_CHKSUM (0x00000001)
861 #define DMA_FLAG_PAD_BLOCK (0x00000002)
862 #define DMA_FLAG_PAD_DWORD (0x00000004)
863  
864 struct msdc_dma {
865 u32 flags; /* flags */
866 u32 xfersz; /* xfer size in bytes */
867 u32 sglen; /* size of scatter list */
868 u32 blklen; /* block size */
869 struct scatterlist *sg; /* I/O scatter list */
870 struct scatterlist_ex *esg; /* extended I/O scatter list */
871 u8 mode; /* dma mode */
872 u8 burstsz; /* burst size */
873 u8 intr; /* dma done interrupt */
874 u8 padding; /* padding */
875 u32 cmd; /* enhanced mode command */
876 u32 arg; /* enhanced mode arg */
877 u32 rsp; /* enhanced mode command response */
878 u32 autorsp; /* auto command response */
879  
880 gpd_t *gpd; /* pointer to gpd array */
881 bd_t *bd; /* pointer to bd array */
882 dma_addr_t gpd_addr; /* the physical address of gpd array */
883 dma_addr_t bd_addr; /* the physical address of bd array */
884 u32 used_gpd; /* the number of used gpd elements */
885 u32 used_bd; /* the number of used bd elements */
886 };
887  
888 struct msdc_host
889 {
890 struct msdc_hw *hw;
891  
892 struct mmc_host *mmc; /* mmc structure */
893 struct mmc_command *cmd;
894 struct mmc_data *data;
895 struct mmc_request *mrq;
896 int cmd_rsp;
897 int cmd_rsp_done;
898 int cmd_r1b_done;
899  
900 int error;
901 spinlock_t lock; /* mutex */
902 struct semaphore sem;
903  
904 u32 blksz; /* host block size */
905 u32 base; /* host base address */
906 int id; /* host id */
907 int pwr_ref; /* core power reference count */
908  
909 u32 xfer_size; /* total transferred size */
910  
911 struct msdc_dma dma; /* dma channel */
912 u32 dma_addr; /* dma transfer address */
913 u32 dma_left_size; /* dma transfer left size */
914 u32 dma_xfer_size; /* dma transfer size in bytes */
915 int dma_xfer; /* dma transfer mode */
916  
917 u32 timeout_ns; /* data timeout ns */
918 u32 timeout_clks; /* data timeout clks */
919  
920 atomic_t abort; /* abort transfer */
921  
922 int irq; /* host interrupt */
923  
924 struct tasklet_struct card_tasklet;
925 #if 0
926 struct work_struct card_workqueue;
927 #else
928 struct delayed_work card_delaywork;
929 #endif
930  
931 struct completion cmd_done;
932 struct completion xfer_done;
933 struct pm_message pm_state;
934  
935 u32 mclk; /* mmc subsystem clock */
936 u32 hclk; /* host clock speed */
937 u32 sclk; /* SD/MS clock speed */
938 u8 core_clkon; /* Host core clock on ? */
939 u8 card_clkon; /* Card clock on ? */
940 u8 core_power; /* core power */
941 u8 power_mode; /* host power mode */
942 u8 card_inserted; /* card inserted ? */
943 u8 suspend; /* host suspended ? */
944 u8 reserved;
945 u8 app_cmd; /* for app command */
946 u32 app_cmd_arg;
947 u64 starttime;
948 };
949  
950 static inline unsigned int uffs(unsigned int x)
951 {
952 unsigned int r = 1;
953  
954 if (!x)
955 return 0;
956 if (!(x & 0xffff)) {
957 x >>= 16;
958 r += 16;
959 }
960 if (!(x & 0xff)) {
961 x >>= 8;
962 r += 8;
963 }
964 if (!(x & 0xf)) {
965 x >>= 4;
966 r += 4;
967 }
968 if (!(x & 3)) {
969 x >>= 2;
970 r += 2;
971 }
972 if (!(x & 1)) {
973 x >>= 1;
974 r += 1;
975 }
976 return r;
977 }
978 #define sdr_read8(reg) __raw_readb(reg)
979 #define sdr_read16(reg) __raw_readw(reg)
980 #define sdr_read32(reg) __raw_readl(reg)
981 #define sdr_write8(reg,val) __raw_writeb(val,reg)
982 #define sdr_write16(reg,val) __raw_writew(val,reg)
983 #define sdr_write32(reg,val) __raw_writel(val,reg)
984  
985 #define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
986 #define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
987  
988 #define sdr_set_field(reg,field,val) \
989 do { \
990 volatile unsigned int tv = sdr_read32(reg); \
991 tv &= ~(field); \
992 tv |= ((val) << (uffs((unsigned int)field) - 1)); \
993 sdr_write32(reg,tv); \
994 } while(0)
995 #define sdr_get_field(reg,field,val) \
996 do { \
997 volatile unsigned int tv = sdr_read32(reg); \
998 val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
999 } while(0)
1000  
1001 #endif
1002