OpenWrt – Blame information for rev 4

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Rev Author Line No. Line
4 office 1 From 596c3a7300c0419dba71d58cbd4136e0d1e12a4e Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Tue, 5 Jan 2016 14:30:22 +0800
4 Subject: [PATCH 06/57] reset: mediatek: mt2701 reset driver
5  
6 In infrasys and perifsys, there are many reset
7 control bits for kinds of modules. These bits are
8 used as actual reset controllers to be registered
9 into kernel's generic reset controller framework.
10  
11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
12 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
13 ---
14 drivers/clk/mediatek/clk-mt2701.c | 4 ++++
15 1 file changed, 4 insertions(+)
16  
17 --- a/drivers/clk/mediatek/clk-mt2701.c
18 +++ b/drivers/clk/mediatek/clk-mt2701.c
19 @@ -772,6 +772,8 @@ static void mtk_infrasys_init_early(stru
20 if (r)
21 pr_err("%s(): could not register clock provider: %d\n",
22 __func__, r);
23 +
24 + mtk_register_reset_controller(node, 2, 0x30);
25 }
26 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
27 mtk_infrasys_init_early);